2 * Copyright 2014 Chen-Yu Tsai
4 * Chen-Yu Tsai <wens@csie.org>
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/clock/sun9i-a80-ccu.h>
48 #include <dt-bindings/clock/sun9i-a80-de.h>
49 #include <dt-bindings/clock/sun9i-a80-usb.h>
50 #include <dt-bindings/reset/sun9i-a80-ccu.h>
51 #include <dt-bindings/reset/sun9i-a80-de.h>
52 #include <dt-bindings/reset/sun9i-a80-usb.h>
57 interrupt-parent = <&gic>;
68 compatible = "arm,cortex-a7";
70 cci-control-port = <&cci_control0>;
71 clock-frequency = <12000000>;
72 enable-method = "allwinner,sun9i-a80-smp";
77 compatible = "arm,cortex-a7";
79 cci-control-port = <&cci_control0>;
80 clock-frequency = <12000000>;
81 enable-method = "allwinner,sun9i-a80-smp";
86 compatible = "arm,cortex-a7";
88 cci-control-port = <&cci_control0>;
89 clock-frequency = <12000000>;
90 enable-method = "allwinner,sun9i-a80-smp";
95 compatible = "arm,cortex-a7";
97 cci-control-port = <&cci_control0>;
98 clock-frequency = <12000000>;
99 enable-method = "allwinner,sun9i-a80-smp";
104 compatible = "arm,cortex-a15";
106 cci-control-port = <&cci_control1>;
107 clock-frequency = <18000000>;
108 enable-method = "allwinner,sun9i-a80-smp";
113 compatible = "arm,cortex-a15";
115 cci-control-port = <&cci_control1>;
116 clock-frequency = <18000000>;
117 enable-method = "allwinner,sun9i-a80-smp";
122 compatible = "arm,cortex-a15";
124 cci-control-port = <&cci_control1>;
125 clock-frequency = <18000000>;
126 enable-method = "allwinner,sun9i-a80-smp";
131 compatible = "arm,cortex-a15";
133 cci-control-port = <&cci_control1>;
134 clock-frequency = <18000000>;
135 enable-method = "allwinner,sun9i-a80-smp";
141 compatible = "arm,armv7-timer";
142 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
143 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
144 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
145 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
146 clock-frequency = <24000000>;
147 arm,cpu-registers-not-fw-configured;
151 #address-cells = <1>;
154 * map 64 bit address range down to 32 bits,
155 * as the peripherals are all under 512MB.
157 ranges = <0 0 0 0x20000000>;
160 * This clock is actually configurable from the PRCM address
161 * space. The external 24M oscillator can be turned off, and
162 * the clock switched to an internal 16M RC oscillator. Under
163 * normal operation there's no reason to do this, and the
164 * default is to use the external good one, so just model this
165 * as a fixed clock. Also it is not entirely clear if the
166 * osc24M mux in the PRCM affects the entire clock tree, which
167 * would also throw all the PLL clock rates off, or just the
168 * downstream clocks in the PRCM.
172 compatible = "fixed-clock";
173 clock-frequency = <24000000>;
174 clock-output-names = "osc24M";
178 * The 32k clock is from an external source, normally the
179 * AC100 codec/RTC chip. This serves as a placeholder for
180 * board dts files to specify the source.
184 compatible = "fixed-factor-clock";
187 clock-output-names = "osc32k";
191 * The following two are dummy clocks, placeholders
192 * used in the gmac_tx clock. The gmac driver will
193 * choose one parent depending on the PHY interface
194 * mode, using clk_set_rate auto-reparenting.
196 * The actual TX clock rate is not controlled by the
199 mii_phy_tx_clk: mii_phy_tx_clk {
201 compatible = "fixed-clock";
202 clock-frequency = <25000000>;
203 clock-output-names = "mii_phy_tx";
206 gmac_int_tx_clk: gmac_int_tx_clk {
208 compatible = "fixed-clock";
209 clock-frequency = <125000000>;
210 clock-output-names = "gmac_int_tx";
213 gmac_tx_clk: clk@800030 {
215 compatible = "allwinner,sun7i-a20-gmac-clk";
216 reg = <0x00800030 0x4>;
217 clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
218 clock-output-names = "gmac_tx";
221 cpus_clk: clk@8001410 {
222 compatible = "allwinner,sun9i-a80-cpus-clk";
223 reg = <0x08001410 0x4>;
225 clocks = <&osc32k>, <&osc24M>,
226 <&ccu CLK_PLL_PERIPH0>,
227 <&ccu CLK_PLL_AUDIO>;
228 clock-output-names = "cpus";
232 compatible = "fixed-factor-clock";
236 clocks = <&cpus_clk>;
237 clock-output-names = "ahbs";
241 compatible = "allwinner,sun8i-a23-apb0-clk";
242 reg = <0x0800141c 0x4>;
245 clock-output-names = "apbs";
248 apbs_gates: clk@8001428 {
249 compatible = "allwinner,sun9i-a80-apbs-gates-clk";
250 reg = <0x08001428 0x4>;
253 clock-indices = <0>, <1>,
260 clock-output-names = "apbs_pio", "apbs_ir",
261 "apbs_timer", "apbs_rsb",
262 "apbs_uart", "apbs_1wire",
263 "apbs_i2c0", "apbs_i2c1",
264 "apbs_ps2_0", "apbs_ps2_1",
265 "apbs_dma", "apbs_i2s0",
266 "apbs_i2s1", "apbs_twd";
269 r_1wire_clk: clk@8001450 {
270 reg = <0x08001450 0x4>;
272 compatible = "allwinner,sun4i-a10-mod0-clk";
273 clocks = <&osc32k>, <&osc24M>;
274 clock-output-names = "r_1wire";
277 r_ir_clk: clk@8001454 {
278 reg = <0x08001454 0x4>;
280 compatible = "allwinner,sun4i-a10-mod0-clk";
281 clocks = <&osc32k>, <&osc24M>;
282 clock-output-names = "r_ir";
287 compatible = "allwinner,sun9i-a80-display-engine";
288 allwinner,pipelines = <&fe0>, <&fe1>;
293 compatible = "simple-bus";
294 #address-cells = <1>;
297 * map 64 bit address range down to 32 bits,
298 * as the peripherals are all under 512MB.
300 ranges = <0 0 0 0x20000000>;
303 /* 256 KiB secure SRAM at 0x20000 */
304 compatible = "mmio-sram";
305 reg = <0x00020000 0x40000>;
307 #address-cells = <1>;
309 ranges = <0 0x00020000 0x40000>;
313 * This is checked by BROM to determine if
314 * cpu0 should jump to SMP entry vector
316 compatible = "allwinner,sun9i-a80-smp-sram";
321 gmac: ethernet@830000 {
322 compatible = "allwinner,sun7i-a20-gmac";
323 reg = <0x00830000 0x1054>;
324 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
325 interrupt-names = "macirq";
326 clocks = <&ccu CLK_BUS_GMAC>, <&gmac_tx_clk>;
327 clock-names = "stmmaceth", "allwinner_gmac_tx";
328 resets = <&ccu RST_BUS_GMAC>;
329 reset-names = "stmmaceth";
332 snps,force_sf_dma_mode;
334 #address-cells = <1>;
339 compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
340 reg = <0x00a00000 0x100>;
341 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
342 clocks = <&usb_clocks CLK_BUS_HCI0>;
343 resets = <&usb_clocks RST_USB0_HCI>;
350 compatible = "allwinner,sun9i-a80-ohci", "generic-ohci";
351 reg = <0x00a00400 0x100>;
352 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
353 clocks = <&usb_clocks CLK_BUS_HCI0>,
354 <&usb_clocks CLK_USB_OHCI0>;
355 resets = <&usb_clocks RST_USB0_HCI>;
361 usbphy1: phy@a00800 {
362 compatible = "allwinner,sun9i-a80-usb-phy";
363 reg = <0x00a00800 0x4>;
364 clocks = <&usb_clocks CLK_USB0_PHY>;
366 resets = <&usb_clocks RST_USB0_PHY>;
373 compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
374 reg = <0x00a01000 0x100>;
375 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
376 clocks = <&usb_clocks CLK_BUS_HCI1>;
377 resets = <&usb_clocks RST_USB1_HCI>;
383 usbphy2: phy@a01800 {
384 compatible = "allwinner,sun9i-a80-usb-phy";
385 reg = <0x00a01800 0x4>;
386 clocks = <&usb_clocks CLK_USB1_HSIC>,
387 <&usb_clocks CLK_USB_HSIC>,
388 <&usb_clocks CLK_USB1_PHY>;
389 clock-names = "hsic_480M",
392 resets = <&usb_clocks RST_USB1_HSIC>,
393 <&usb_clocks RST_USB1_PHY>;
394 reset-names = "hsic",
398 /* usb1 is always used with HSIC */
403 compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
404 reg = <0x00a02000 0x100>;
405 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
406 clocks = <&usb_clocks CLK_BUS_HCI2>;
407 resets = <&usb_clocks RST_USB2_HCI>;
414 compatible = "allwinner,sun9i-a80-ohci", "generic-ohci";
415 reg = <0x00a02400 0x100>;
416 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
417 clocks = <&usb_clocks CLK_BUS_HCI2>,
418 <&usb_clocks CLK_USB_OHCI2>;
419 resets = <&usb_clocks RST_USB2_HCI>;
425 usbphy3: phy@a02800 {
426 compatible = "allwinner,sun9i-a80-usb-phy";
427 reg = <0x00a02800 0x4>;
428 clocks = <&usb_clocks CLK_USB2_HSIC>,
429 <&usb_clocks CLK_USB_HSIC>,
430 <&usb_clocks CLK_USB2_PHY>;
431 clock-names = "hsic_480M",
434 resets = <&usb_clocks RST_USB2_HSIC>,
435 <&usb_clocks RST_USB2_PHY>;
436 reset-names = "hsic",
442 usb_clocks: clock@a08000 {
443 compatible = "allwinner,sun9i-a80-usb-clks";
444 reg = <0x00a08000 0x8>;
445 clocks = <&ccu CLK_BUS_USB>, <&osc24M>;
446 clock-names = "bus", "hosc";
452 compatible = "allwinner,sun9i-a80-cpucfg";
453 reg = <0x01700000 0x100>;
457 compatible = "allwinner,sun9i-a80-mmc";
458 reg = <0x01c0f000 0x1000>;
459 clocks = <&mmc_config_clk 0>, <&ccu CLK_MMC0>,
460 <&ccu CLK_MMC0_OUTPUT>,
461 <&ccu CLK_MMC0_SAMPLE>;
462 clock-names = "ahb", "mmc", "output", "sample";
463 resets = <&mmc_config_clk 0>;
465 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
467 #address-cells = <1>;
472 compatible = "allwinner,sun9i-a80-mmc";
473 reg = <0x01c10000 0x1000>;
474 clocks = <&mmc_config_clk 1>, <&ccu CLK_MMC1>,
475 <&ccu CLK_MMC1_OUTPUT>,
476 <&ccu CLK_MMC1_SAMPLE>;
477 clock-names = "ahb", "mmc", "output", "sample";
478 resets = <&mmc_config_clk 1>;
480 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
482 #address-cells = <1>;
487 compatible = "allwinner,sun9i-a80-mmc";
488 reg = <0x01c11000 0x1000>;
489 clocks = <&mmc_config_clk 2>, <&ccu CLK_MMC2>,
490 <&ccu CLK_MMC2_OUTPUT>,
491 <&ccu CLK_MMC2_SAMPLE>;
492 clock-names = "ahb", "mmc", "output", "sample";
493 resets = <&mmc_config_clk 2>;
495 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
497 #address-cells = <1>;
502 compatible = "allwinner,sun9i-a80-mmc";
503 reg = <0x01c12000 0x1000>;
504 clocks = <&mmc_config_clk 3>, <&ccu CLK_MMC3>,
505 <&ccu CLK_MMC3_OUTPUT>,
506 <&ccu CLK_MMC3_SAMPLE>;
507 clock-names = "ahb", "mmc", "output", "sample";
508 resets = <&mmc_config_clk 3>;
510 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
512 #address-cells = <1>;
516 mmc_config_clk: clk@1c13000 {
517 compatible = "allwinner,sun9i-a80-mmc-config-clk";
518 reg = <0x01c13000 0x10>;
519 clocks = <&ccu CLK_BUS_MMC>;
521 resets = <&ccu RST_BUS_MMC>;
525 clock-output-names = "mmc0_config", "mmc1_config",
526 "mmc2_config", "mmc3_config";
529 gic: interrupt-controller@1c41000 {
530 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
531 reg = <0x01c41000 0x1000>,
535 interrupt-controller;
536 #interrupt-cells = <3>;
537 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
541 compatible = "arm,cci-400";
542 #address-cells = <1>;
544 reg = <0x01c90000 0x1000>;
545 ranges = <0x0 0x01c90000 0x10000>;
547 cci_control0: slave-if@4000 {
548 compatible = "arm,cci-400-ctrl-if";
549 interface-type = "ace";
550 reg = <0x4000 0x1000>;
553 cci_control1: slave-if@5000 {
554 compatible = "arm,cci-400-ctrl-if";
555 interface-type = "ace";
556 reg = <0x5000 0x1000>;
560 compatible = "arm,cci-400-pmu,r1";
561 reg = <0x9000 0x5000>;
562 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
563 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
564 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
565 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
566 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
570 de_clocks: clock@3000000 {
571 compatible = "allwinner,sun9i-a80-de-clks";
572 reg = <0x03000000 0x30>;
573 clocks = <&ccu CLK_DE>,
579 resets = <&ccu RST_BUS_DE>;
584 fe0: display-frontend@3100000 {
585 compatible = "allwinner,sun9i-a80-display-frontend";
586 reg = <0x03100000 0x40000>;
587 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
588 clocks = <&de_clocks CLK_BUS_FE0>, <&de_clocks CLK_FE0>,
589 <&de_clocks CLK_DRAM_FE0>;
590 clock-names = "ahb", "mod",
592 resets = <&de_clocks RST_FE0>;
595 #address-cells = <1>;
599 #address-cells = <1>;
603 fe0_out_deu0: endpoint@0 {
605 remote-endpoint = <&deu0_in_fe0>;
611 fe1: display-frontend@3140000 {
612 compatible = "allwinner,sun9i-a80-display-frontend";
613 reg = <0x03140000 0x40000>;
614 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
615 clocks = <&de_clocks CLK_BUS_FE1>, <&de_clocks CLK_FE1>,
616 <&de_clocks CLK_DRAM_FE1>;
617 clock-names = "ahb", "mod",
619 resets = <&de_clocks RST_FE0>;
622 #address-cells = <1>;
626 #address-cells = <1>;
630 fe1_out_deu1: endpoint@0 {
632 remote-endpoint = <&deu1_in_fe1>;
638 be0: display-backend@3200000 {
639 compatible = "allwinner,sun9i-a80-display-backend";
640 reg = <0x03200000 0x40000>;
641 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
642 clocks = <&de_clocks CLK_BUS_BE0>, <&de_clocks CLK_BE0>,
643 <&de_clocks CLK_DRAM_BE0>;
644 clock-names = "ahb", "mod",
646 resets = <&de_clocks RST_BE0>;
649 #address-cells = <1>;
653 #address-cells = <1>;
657 be0_in_deu0: endpoint@0 {
659 remote-endpoint = <&deu0_out_be0>;
662 be0_in_deu1: endpoint@1 {
664 remote-endpoint = <&deu1_out_be0>;
669 #address-cells = <1>;
673 be0_out_drc0: endpoint@0 {
675 remote-endpoint = <&drc0_in_be0>;
681 be1: display-backend@3240000 {
682 compatible = "allwinner,sun9i-a80-display-backend";
683 reg = <0x03240000 0x40000>;
684 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
685 clocks = <&de_clocks CLK_BUS_BE1>, <&de_clocks CLK_BE1>,
686 <&de_clocks CLK_DRAM_BE1>;
687 clock-names = "ahb", "mod",
689 resets = <&de_clocks RST_BE1>;
692 #address-cells = <1>;
696 #address-cells = <1>;
700 be1_in_deu0: endpoint@0 {
702 remote-endpoint = <&deu0_out_be1>;
705 be1_in_deu1: endpoint@1 {
707 remote-endpoint = <&deu1_out_be1>;
712 #address-cells = <1>;
716 be1_out_drc1: endpoint@0 {
718 remote-endpoint = <&drc1_in_be1>;
725 compatible = "allwinner,sun9i-a80-deu";
726 reg = <0x03300000 0x40000>;
727 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
728 clocks = <&de_clocks CLK_BUS_DEU0>,
729 <&de_clocks CLK_IEP_DEU0>,
730 <&de_clocks CLK_DRAM_DEU0>;
734 resets = <&de_clocks RST_DEU0>;
737 #address-cells = <1>;
741 #address-cells = <1>;
745 deu0_in_fe0: endpoint@0 {
747 remote-endpoint = <&fe0_out_deu0>;
752 #address-cells = <1>;
756 deu0_out_be0: endpoint@0 {
758 remote-endpoint = <&be0_in_deu0>;
761 deu0_out_be1: endpoint@1 {
763 remote-endpoint = <&be1_in_deu0>;
770 compatible = "allwinner,sun9i-a80-deu";
771 reg = <0x03340000 0x40000>;
772 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
773 clocks = <&de_clocks CLK_BUS_DEU1>,
774 <&de_clocks CLK_IEP_DEU1>,
775 <&de_clocks CLK_DRAM_DEU1>;
779 resets = <&de_clocks RST_DEU1>;
782 #address-cells = <1>;
786 #address-cells = <1>;
790 deu1_in_fe1: endpoint@0 {
792 remote-endpoint = <&fe1_out_deu1>;
797 #address-cells = <1>;
801 deu1_out_be0: endpoint@0 {
803 remote-endpoint = <&be0_in_deu1>;
806 deu1_out_be1: endpoint@1 {
808 remote-endpoint = <&be1_in_deu1>;
815 compatible = "allwinner,sun9i-a80-drc";
816 reg = <0x03400000 0x40000>;
817 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
818 clocks = <&de_clocks CLK_BUS_DRC0>,
819 <&de_clocks CLK_IEP_DRC0>,
820 <&de_clocks CLK_DRAM_DRC0>;
824 resets = <&de_clocks RST_DRC0>;
827 #address-cells = <1>;
831 #address-cells = <1>;
835 drc0_in_be0: endpoint@0 {
837 remote-endpoint = <&be0_out_drc0>;
842 #address-cells = <1>;
846 drc0_out_tcon0: endpoint@0 {
848 remote-endpoint = <&tcon0_in_drc0>;
855 compatible = "allwinner,sun9i-a80-drc";
856 reg = <0x03440000 0x40000>;
857 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
858 clocks = <&de_clocks CLK_BUS_DRC1>,
859 <&de_clocks CLK_IEP_DRC1>,
860 <&de_clocks CLK_DRAM_DRC1>;
864 resets = <&de_clocks RST_DRC1>;
867 #address-cells = <1>;
871 #address-cells = <1>;
875 drc1_in_be1: endpoint@0 {
877 remote-endpoint = <&be1_out_drc1>;
882 #address-cells = <1>;
886 drc1_out_tcon1: endpoint@0 {
888 remote-endpoint = <&tcon1_in_drc1>;
894 tcon0: lcd-controller@3c00000 {
895 compatible = "allwinner,sun9i-a80-tcon-lcd";
896 reg = <0x03c00000 0x10000>;
897 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
898 clocks = <&ccu CLK_BUS_LCD0>, <&ccu CLK_LCD0>;
899 clock-names = "ahb", "tcon-ch0";
900 resets = <&ccu RST_BUS_LCD0>, <&ccu RST_BUS_EDP>;
901 reset-names = "lcd", "edp";
902 clock-output-names = "tcon0-pixel-clock";
905 #address-cells = <1>;
909 #address-cells = <1>;
913 tcon0_in_drc0: endpoint@0 {
915 remote-endpoint = <&drc0_out_tcon0>;
920 #address-cells = <1>;
927 tcon1: lcd-controller@3c10000 {
928 compatible = "allwinner,sun9i-a80-tcon-tv";
929 reg = <0x03c10000 0x10000>;
930 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
931 clocks = <&ccu CLK_BUS_LCD1>, <&ccu CLK_LCD1>;
932 clock-names = "ahb", "tcon-ch1";
933 resets = <&ccu RST_BUS_LCD1>, <&ccu RST_BUS_EDP>;
934 reset-names = "lcd", "edp";
937 #address-cells = <1>;
941 #address-cells = <1>;
945 tcon1_in_drc1: endpoint@0 {
947 remote-endpoint = <&drc1_out_tcon1>;
952 #address-cells = <1>;
960 compatible = "allwinner,sun9i-a80-ccu";
961 reg = <0x06000000 0x800>;
962 clocks = <&osc24M>, <&osc32k>;
963 clock-names = "hosc", "losc";
969 compatible = "allwinner,sun4i-a10-timer";
970 reg = <0x06000c00 0xa0>;
971 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
972 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
973 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
974 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
975 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
976 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
981 wdt: watchdog@6000ca0 {
982 compatible = "allwinner,sun6i-a31-wdt";
983 reg = <0x06000ca0 0x20>;
984 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
987 pio: pinctrl@6000800 {
988 compatible = "allwinner,sun9i-a80-pinctrl";
989 reg = <0x06000800 0x400>;
990 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
991 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
992 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
993 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
994 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
995 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
996 clock-names = "apb", "hosc", "losc";
998 interrupt-controller;
999 #interrupt-cells = <3>;
1003 gmac_rgmii_pins: gmac-rgmii-pins {
1004 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
1005 "PA4", "PA5", "PA7", "PA8",
1006 "PA9", "PA10", "PA12", "PA13",
1007 "PA15", "PA16", "PA17";
1008 allwinner,function = "gmac";
1010 * data lines in RGMII mode use DDR mode
1011 * and need a higher signal drive strength
1013 drive-strength = <40>;
1016 i2c3_pins: i2c3-pins {
1017 pins = "PG10", "PG11";
1021 lcd0_rgb888_pins: lcd0-rgb888-pins {
1022 pins = "PD0", "PD1", "PD2", "PD3",
1023 "PD4", "PD5", "PD6", "PD7",
1024 "PD8", "PD9", "PD10", "PD11",
1025 "PD12", "PD13", "PD14", "PD15",
1026 "PD16", "PD17", "PD18", "PD19",
1027 "PD20", "PD21", "PD22", "PD23",
1028 "PD24", "PD25", "PD26", "PD27";
1032 mmc0_pins: mmc0-pins {
1033 pins = "PF0", "PF1" ,"PF2", "PF3",
1036 drive-strength = <30>;
1040 mmc1_pins: mmc1-pins {
1041 pins = "PG0", "PG1" ,"PG2", "PG3",
1044 drive-strength = <30>;
1048 mmc2_8bit_pins: mmc2-8bit-pins {
1049 pins = "PC6", "PC7", "PC8", "PC9",
1050 "PC10", "PC11", "PC12",
1051 "PC13", "PC14", "PC15",
1054 drive-strength = <30>;
1058 uart0_ph_pins: uart0-ph-pins {
1059 pins = "PH12", "PH13";
1063 uart4_pins: uart4-pins {
1064 pins = "PG12", "PG13", "PG14", "PG15";
1069 uart0: serial@7000000 {
1070 compatible = "snps,dw-apb-uart";
1071 reg = <0x07000000 0x400>;
1072 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
1075 clocks = <&ccu CLK_BUS_UART0>;
1076 resets = <&ccu RST_BUS_UART0>;
1077 status = "disabled";
1080 uart1: serial@7000400 {
1081 compatible = "snps,dw-apb-uart";
1082 reg = <0x07000400 0x400>;
1083 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1086 clocks = <&ccu CLK_BUS_UART1>;
1087 resets = <&ccu RST_BUS_UART1>;
1088 status = "disabled";
1091 uart2: serial@7000800 {
1092 compatible = "snps,dw-apb-uart";
1093 reg = <0x07000800 0x400>;
1094 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1097 clocks = <&ccu CLK_BUS_UART2>;
1098 resets = <&ccu RST_BUS_UART2>;
1099 status = "disabled";
1102 uart3: serial@7000c00 {
1103 compatible = "snps,dw-apb-uart";
1104 reg = <0x07000c00 0x400>;
1105 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1108 clocks = <&ccu CLK_BUS_UART3>;
1109 resets = <&ccu RST_BUS_UART3>;
1110 status = "disabled";
1113 uart4: serial@7001000 {
1114 compatible = "snps,dw-apb-uart";
1115 reg = <0x07001000 0x400>;
1116 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1119 clocks = <&ccu CLK_BUS_UART4>;
1120 resets = <&ccu RST_BUS_UART4>;
1121 status = "disabled";
1124 uart5: serial@7001400 {
1125 compatible = "snps,dw-apb-uart";
1126 reg = <0x07001400 0x400>;
1127 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1130 clocks = <&ccu CLK_BUS_UART5>;
1131 resets = <&ccu RST_BUS_UART5>;
1132 status = "disabled";
1136 compatible = "allwinner,sun6i-a31-i2c";
1137 reg = <0x07002800 0x400>;
1138 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1139 clocks = <&ccu CLK_BUS_I2C0>;
1140 resets = <&ccu RST_BUS_I2C0>;
1141 status = "disabled";
1142 #address-cells = <1>;
1147 compatible = "allwinner,sun6i-a31-i2c";
1148 reg = <0x07002c00 0x400>;
1149 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1150 clocks = <&ccu CLK_BUS_I2C1>;
1151 resets = <&ccu RST_BUS_I2C1>;
1152 status = "disabled";
1153 #address-cells = <1>;
1158 compatible = "allwinner,sun6i-a31-i2c";
1159 reg = <0x07003000 0x400>;
1160 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1161 clocks = <&ccu CLK_BUS_I2C2>;
1162 resets = <&ccu RST_BUS_I2C2>;
1163 status = "disabled";
1164 #address-cells = <1>;
1169 compatible = "allwinner,sun6i-a31-i2c";
1170 reg = <0x07003400 0x400>;
1171 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1172 clocks = <&ccu CLK_BUS_I2C3>;
1173 resets = <&ccu RST_BUS_I2C3>;
1174 status = "disabled";
1175 #address-cells = <1>;
1180 compatible = "allwinner,sun6i-a31-i2c";
1181 reg = <0x07003800 0x400>;
1182 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1183 clocks = <&ccu CLK_BUS_I2C4>;
1184 resets = <&ccu RST_BUS_I2C4>;
1185 status = "disabled";
1186 #address-cells = <1>;
1190 r_wdt: watchdog@8001000 {
1191 compatible = "allwinner,sun6i-a31-wdt";
1192 reg = <0x08001000 0x20>;
1193 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
1197 compatible = "allwinner,sun9i-a80-prcm";
1198 reg = <0x08001400 0x200>;
1201 apbs_rst: reset@80014b0 {
1202 reg = <0x080014b0 0x4>;
1203 compatible = "allwinner,sun6i-a31-clock-reset";
1207 nmi_intc: interrupt-controller@80015a0 {
1208 compatible = "allwinner,sun9i-a80-nmi";
1209 interrupt-controller;
1210 #interrupt-cells = <2>;
1211 reg = <0x080015a0 0xc>;
1212 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1216 compatible = "allwinner,sun5i-a13-ir";
1217 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1218 pinctrl-names = "default";
1219 pinctrl-0 = <&r_ir_pins>;
1220 clocks = <&apbs_gates 1>, <&r_ir_clk>;
1221 clock-names = "apb", "ir";
1222 resets = <&apbs_rst 1>;
1223 reg = <0x08002000 0x40>;
1224 status = "disabled";
1227 r_uart: serial@8002800 {
1228 compatible = "snps,dw-apb-uart";
1229 reg = <0x08002800 0x400>;
1230 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
1233 clocks = <&apbs_gates 4>;
1234 resets = <&apbs_rst 4>;
1235 status = "disabled";
1238 r_pio: pinctrl@8002c00 {
1239 compatible = "allwinner,sun9i-a80-r-pinctrl";
1240 reg = <0x08002c00 0x400>;
1241 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
1242 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
1243 clocks = <&apbs_gates 0>, <&osc24M>, <&osc32k>;
1244 clock-names = "apb", "hosc", "losc";
1245 resets = <&apbs_rst 0>;
1247 interrupt-controller;
1248 #interrupt-cells = <3>;
1251 r_ir_pins: r-ir-pins {
1253 function = "s_cir_rx";
1256 r_rsb_pins: r-rsb-pins {
1257 pins = "PN0", "PN1";
1259 drive-strength = <20>;
1264 r_rsb: rsb@8003400 {
1265 compatible = "allwinner,sun8i-a23-rsb";
1266 reg = <0x08003400 0x400>;
1267 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1268 clocks = <&apbs_gates 3>;
1269 clock-frequency = <3000000>;
1270 resets = <&apbs_rst 3>;
1271 pinctrl-names = "default";
1272 pinctrl-0 = <&r_rsb_pins>;
1273 status = "disabled";
1274 #address-cells = <1>;