2 * Copyright 2014 Chen-Yu Tsai
4 * Chen-Yu Tsai <wens@csie.org>
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/clock/sun9i-a80-ccu.h>
48 #include <dt-bindings/clock/sun9i-a80-de.h>
49 #include <dt-bindings/clock/sun9i-a80-usb.h>
50 #include <dt-bindings/reset/sun9i-a80-ccu.h>
51 #include <dt-bindings/reset/sun9i-a80-de.h>
52 #include <dt-bindings/reset/sun9i-a80-usb.h>
57 interrupt-parent = <&gic>;
64 compatible = "arm,cortex-a7";
70 compatible = "arm,cortex-a7";
76 compatible = "arm,cortex-a7";
82 compatible = "arm,cortex-a7";
88 compatible = "arm,cortex-a15";
94 compatible = "arm,cortex-a15";
100 compatible = "arm,cortex-a15";
106 compatible = "arm,cortex-a15";
113 compatible = "arm,armv7-timer";
114 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
115 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
116 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
117 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
118 clock-frequency = <24000000>;
119 arm,cpu-registers-not-fw-configured;
123 #address-cells = <1>;
126 * map 64 bit address range down to 32 bits,
127 * as the peripherals are all under 512MB.
129 ranges = <0 0 0 0x20000000>;
132 * This clock is actually configurable from the PRCM address
133 * space. The external 24M oscillator can be turned off, and
134 * the clock switched to an internal 16M RC oscillator. Under
135 * normal operation there's no reason to do this, and the
136 * default is to use the external good one, so just model this
137 * as a fixed clock. Also it is not entirely clear if the
138 * osc24M mux in the PRCM affects the entire clock tree, which
139 * would also throw all the PLL clock rates off, or just the
140 * downstream clocks in the PRCM.
144 compatible = "fixed-clock";
145 clock-frequency = <24000000>;
146 clock-output-names = "osc24M";
150 * The 32k clock is from an external source, normally the
151 * AC100 codec/RTC chip. This serves as a placeholder for
152 * board dts files to specify the source.
156 compatible = "fixed-factor-clock";
159 clock-output-names = "osc32k";
162 cpus_clk: clk@8001410 {
163 compatible = "allwinner,sun9i-a80-cpus-clk";
164 reg = <0x08001410 0x4>;
166 clocks = <&osc32k>, <&osc24M>,
167 <&ccu CLK_PLL_PERIPH0>,
168 <&ccu CLK_PLL_AUDIO>;
169 clock-output-names = "cpus";
173 compatible = "fixed-factor-clock";
177 clocks = <&cpus_clk>;
178 clock-output-names = "ahbs";
182 compatible = "allwinner,sun8i-a23-apb0-clk";
183 reg = <0x0800141c 0x4>;
186 clock-output-names = "apbs";
189 apbs_gates: clk@8001428 {
190 compatible = "allwinner,sun9i-a80-apbs-gates-clk";
191 reg = <0x08001428 0x4>;
194 clock-indices = <0>, <1>,
201 clock-output-names = "apbs_pio", "apbs_ir",
202 "apbs_timer", "apbs_rsb",
203 "apbs_uart", "apbs_1wire",
204 "apbs_i2c0", "apbs_i2c1",
205 "apbs_ps2_0", "apbs_ps2_1",
206 "apbs_dma", "apbs_i2s0",
207 "apbs_i2s1", "apbs_twd";
210 r_1wire_clk: clk@8001450 {
211 reg = <0x08001450 0x4>;
213 compatible = "allwinner,sun4i-a10-mod0-clk";
214 clocks = <&osc32k>, <&osc24M>;
215 clock-output-names = "r_1wire";
218 r_ir_clk: clk@8001454 {
219 reg = <0x08001454 0x4>;
221 compatible = "allwinner,sun4i-a10-mod0-clk";
222 clocks = <&osc32k>, <&osc24M>;
223 clock-output-names = "r_ir";
228 compatible = "simple-bus";
229 #address-cells = <1>;
232 * map 64 bit address range down to 32 bits,
233 * as the peripherals are all under 512MB.
235 ranges = <0 0 0 0x20000000>;
238 compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
239 reg = <0x00a00000 0x100>;
240 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
241 clocks = <&usb_clocks CLK_BUS_HCI0>;
242 resets = <&usb_clocks RST_USB0_HCI>;
249 compatible = "allwinner,sun9i-a80-ohci", "generic-ohci";
250 reg = <0x00a00400 0x100>;
251 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
252 clocks = <&usb_clocks CLK_BUS_HCI0>,
253 <&usb_clocks CLK_USB_OHCI0>;
254 resets = <&usb_clocks RST_USB0_HCI>;
260 usbphy1: phy@a00800 {
261 compatible = "allwinner,sun9i-a80-usb-phy";
262 reg = <0x00a00800 0x4>;
263 clocks = <&usb_clocks CLK_USB0_PHY>;
265 resets = <&usb_clocks RST_USB0_PHY>;
272 compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
273 reg = <0x00a01000 0x100>;
274 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
275 clocks = <&usb_clocks CLK_BUS_HCI1>;
276 resets = <&usb_clocks RST_USB1_HCI>;
282 usbphy2: phy@a01800 {
283 compatible = "allwinner,sun9i-a80-usb-phy";
284 reg = <0x00a01800 0x4>;
285 clocks = <&usb_clocks CLK_USB1_HSIC>,
286 <&usb_clocks CLK_USB_HSIC>,
287 <&usb_clocks CLK_USB1_PHY>;
288 clock-names = "hsic_480M",
291 resets = <&usb_clocks RST_USB1_HSIC>,
292 <&usb_clocks RST_USB1_PHY>;
293 reset-names = "hsic",
297 /* usb1 is always used with HSIC */
302 compatible = "allwinner,sun9i-a80-ehci", "generic-ehci";
303 reg = <0x00a02000 0x100>;
304 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
305 clocks = <&usb_clocks CLK_BUS_HCI2>;
306 resets = <&usb_clocks RST_USB2_HCI>;
313 compatible = "allwinner,sun9i-a80-ohci", "generic-ohci";
314 reg = <0x00a02400 0x100>;
315 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
316 clocks = <&usb_clocks CLK_BUS_HCI2>,
317 <&usb_clocks CLK_USB_OHCI2>;
318 resets = <&usb_clocks RST_USB2_HCI>;
324 usbphy3: phy@a02800 {
325 compatible = "allwinner,sun9i-a80-usb-phy";
326 reg = <0x00a02800 0x4>;
327 clocks = <&usb_clocks CLK_USB2_HSIC>,
328 <&usb_clocks CLK_USB_HSIC>,
329 <&usb_clocks CLK_USB2_PHY>;
330 clock-names = "hsic_480M",
333 resets = <&usb_clocks RST_USB2_HSIC>,
334 <&usb_clocks RST_USB2_PHY>;
335 reset-names = "hsic",
341 usb_clocks: clock@a08000 {
342 compatible = "allwinner,sun9i-a80-usb-clks";
343 reg = <0x00a08000 0x8>;
344 clocks = <&ccu CLK_BUS_USB>, <&osc24M>;
345 clock-names = "bus", "hosc";
351 compatible = "allwinner,sun9i-a80-mmc";
352 reg = <0x01c0f000 0x1000>;
353 clocks = <&mmc_config_clk 0>, <&ccu CLK_MMC0>,
354 <&ccu CLK_MMC0_OUTPUT>,
355 <&ccu CLK_MMC0_SAMPLE>;
356 clock-names = "ahb", "mmc", "output", "sample";
357 resets = <&mmc_config_clk 0>;
359 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
361 #address-cells = <1>;
366 compatible = "allwinner,sun9i-a80-mmc";
367 reg = <0x01c10000 0x1000>;
368 clocks = <&mmc_config_clk 1>, <&ccu CLK_MMC1>,
369 <&ccu CLK_MMC1_OUTPUT>,
370 <&ccu CLK_MMC1_SAMPLE>;
371 clock-names = "ahb", "mmc", "output", "sample";
372 resets = <&mmc_config_clk 1>;
374 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
376 #address-cells = <1>;
381 compatible = "allwinner,sun9i-a80-mmc";
382 reg = <0x01c11000 0x1000>;
383 clocks = <&mmc_config_clk 2>, <&ccu CLK_MMC2>,
384 <&ccu CLK_MMC2_OUTPUT>,
385 <&ccu CLK_MMC2_SAMPLE>;
386 clock-names = "ahb", "mmc", "output", "sample";
387 resets = <&mmc_config_clk 2>;
389 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
391 #address-cells = <1>;
396 compatible = "allwinner,sun9i-a80-mmc";
397 reg = <0x01c12000 0x1000>;
398 clocks = <&mmc_config_clk 3>, <&ccu CLK_MMC3>,
399 <&ccu CLK_MMC3_OUTPUT>,
400 <&ccu CLK_MMC3_SAMPLE>;
401 clock-names = "ahb", "mmc", "output", "sample";
402 resets = <&mmc_config_clk 3>;
404 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
406 #address-cells = <1>;
410 mmc_config_clk: clk@1c13000 {
411 compatible = "allwinner,sun9i-a80-mmc-config-clk";
412 reg = <0x01c13000 0x10>;
413 clocks = <&ccu CLK_BUS_MMC>;
415 resets = <&ccu RST_BUS_MMC>;
419 clock-output-names = "mmc0_config", "mmc1_config",
420 "mmc2_config", "mmc3_config";
423 gic: interrupt-controller@1c41000 {
424 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
425 reg = <0x01c41000 0x1000>,
429 interrupt-controller;
430 #interrupt-cells = <3>;
431 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
434 de_clocks: clock@3000000 {
435 compatible = "allwinner,sun9i-a80-de-clks";
436 reg = <0x03000000 0x30>;
437 clocks = <&ccu CLK_DE>,
443 resets = <&ccu RST_BUS_DE>;
449 compatible = "allwinner,sun9i-a80-ccu";
450 reg = <0x06000000 0x800>;
451 clocks = <&osc24M>, <&osc32k>;
452 clock-names = "hosc", "losc";
458 compatible = "allwinner,sun4i-a10-timer";
459 reg = <0x06000c00 0xa0>;
460 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
461 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
462 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
463 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
464 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
465 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
470 wdt: watchdog@6000ca0 {
471 compatible = "allwinner,sun6i-a31-wdt";
472 reg = <0x06000ca0 0x20>;
473 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
476 pio: pinctrl@6000800 {
477 compatible = "allwinner,sun9i-a80-pinctrl";
478 reg = <0x06000800 0x400>;
479 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
480 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
481 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
482 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
483 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
484 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
485 clock-names = "apb", "hosc", "losc";
487 interrupt-controller;
488 #interrupt-cells = <3>;
492 i2c3_pins: i2c3-pins {
493 pins = "PG10", "PG11";
497 mmc0_pins: mmc0-pins {
498 pins = "PF0", "PF1" ,"PF2", "PF3",
501 drive-strength = <30>;
505 mmc1_pins: mmc1-pins {
506 pins = "PG0", "PG1" ,"PG2", "PG3",
509 drive-strength = <30>;
513 mmc2_8bit_pins: mmc2-8bit-pins {
514 pins = "PC6", "PC7", "PC8", "PC9",
515 "PC10", "PC11", "PC12",
516 "PC13", "PC14", "PC15",
519 drive-strength = <30>;
523 uart0_ph_pins: uart0-ph-pins {
524 pins = "PH12", "PH13";
528 uart4_pins: uart4-pins {
529 pins = "PG12", "PG13", "PG14", "PG15";
534 uart0: serial@7000000 {
535 compatible = "snps,dw-apb-uart";
536 reg = <0x07000000 0x400>;
537 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
540 clocks = <&ccu CLK_BUS_UART0>;
541 resets = <&ccu RST_BUS_UART0>;
545 uart1: serial@7000400 {
546 compatible = "snps,dw-apb-uart";
547 reg = <0x07000400 0x400>;
548 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
551 clocks = <&ccu CLK_BUS_UART1>;
552 resets = <&ccu RST_BUS_UART1>;
556 uart2: serial@7000800 {
557 compatible = "snps,dw-apb-uart";
558 reg = <0x07000800 0x400>;
559 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
562 clocks = <&ccu CLK_BUS_UART2>;
563 resets = <&ccu RST_BUS_UART2>;
567 uart3: serial@7000c00 {
568 compatible = "snps,dw-apb-uart";
569 reg = <0x07000c00 0x400>;
570 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
573 clocks = <&ccu CLK_BUS_UART3>;
574 resets = <&ccu RST_BUS_UART3>;
578 uart4: serial@7001000 {
579 compatible = "snps,dw-apb-uart";
580 reg = <0x07001000 0x400>;
581 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
584 clocks = <&ccu CLK_BUS_UART4>;
585 resets = <&ccu RST_BUS_UART4>;
589 uart5: serial@7001400 {
590 compatible = "snps,dw-apb-uart";
591 reg = <0x07001400 0x400>;
592 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
595 clocks = <&ccu CLK_BUS_UART5>;
596 resets = <&ccu RST_BUS_UART5>;
601 compatible = "allwinner,sun6i-a31-i2c";
602 reg = <0x07002800 0x400>;
603 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
604 clocks = <&ccu CLK_BUS_I2C0>;
605 resets = <&ccu RST_BUS_I2C0>;
607 #address-cells = <1>;
612 compatible = "allwinner,sun6i-a31-i2c";
613 reg = <0x07002c00 0x400>;
614 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
615 clocks = <&ccu CLK_BUS_I2C1>;
616 resets = <&ccu RST_BUS_I2C1>;
618 #address-cells = <1>;
623 compatible = "allwinner,sun6i-a31-i2c";
624 reg = <0x07003000 0x400>;
625 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
626 clocks = <&ccu CLK_BUS_I2C2>;
627 resets = <&ccu RST_BUS_I2C2>;
629 #address-cells = <1>;
634 compatible = "allwinner,sun6i-a31-i2c";
635 reg = <0x07003400 0x400>;
636 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
637 clocks = <&ccu CLK_BUS_I2C3>;
638 resets = <&ccu RST_BUS_I2C3>;
640 #address-cells = <1>;
645 compatible = "allwinner,sun6i-a31-i2c";
646 reg = <0x07003800 0x400>;
647 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
648 clocks = <&ccu CLK_BUS_I2C4>;
649 resets = <&ccu RST_BUS_I2C4>;
651 #address-cells = <1>;
655 r_wdt: watchdog@8001000 {
656 compatible = "allwinner,sun6i-a31-wdt";
657 reg = <0x08001000 0x20>;
658 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
661 apbs_rst: reset@80014b0 {
662 reg = <0x080014b0 0x4>;
663 compatible = "allwinner,sun6i-a31-clock-reset";
667 nmi_intc: interrupt-controller@80015a0 {
668 compatible = "allwinner,sun9i-a80-nmi";
669 interrupt-controller;
670 #interrupt-cells = <2>;
671 reg = <0x080015a0 0xc>;
672 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
676 compatible = "allwinner,sun5i-a13-ir";
677 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
678 pinctrl-names = "default";
679 pinctrl-0 = <&r_ir_pins>;
680 clocks = <&apbs_gates 1>, <&r_ir_clk>;
681 clock-names = "apb", "ir";
682 resets = <&apbs_rst 1>;
683 reg = <0x08002000 0x40>;
687 r_uart: serial@8002800 {
688 compatible = "snps,dw-apb-uart";
689 reg = <0x08002800 0x400>;
690 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
693 clocks = <&apbs_gates 4>;
694 resets = <&apbs_rst 4>;
698 r_pio: pinctrl@8002c00 {
699 compatible = "allwinner,sun9i-a80-r-pinctrl";
700 reg = <0x08002c00 0x400>;
701 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
702 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
703 clocks = <&apbs_gates 0>, <&osc24M>, <&osc32k>;
704 clock-names = "apb", "hosc", "losc";
705 resets = <&apbs_rst 0>;
707 interrupt-controller;
708 #interrupt-cells = <3>;
711 r_ir_pins: r-ir-pins {
713 function = "s_cir_rx";
716 r_rsb_pins: r-rsb-pins {
719 drive-strength = <20>;
725 compatible = "allwinner,sun8i-a23-rsb";
726 reg = <0x08003400 0x400>;
727 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
728 clocks = <&apbs_gates 3>;
729 clock-frequency = <3000000>;
730 resets = <&apbs_rst 3>;
731 pinctrl-names = "default";
732 pinctrl-0 = <&r_rsb_pins>;
734 #address-cells = <1>;