sys/gnu/dts/arm/sunxi-h3-h5.dtsi

   1 /*
   2  * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/sun8i-de2.h>
  44 #include <dt-bindings/clock/sun8i-h3-ccu.h>
  45 #include <dt-bindings/clock/sun8i-r-ccu.h>
  46 #include <dt-bindings/interrupt-controller/arm-gic.h>
  47 #include <dt-bindings/reset/sun8i-de2.h>
  48 #include <dt-bindings/reset/sun8i-h3-ccu.h>
  49 #include <dt-bindings/reset/sun8i-r-ccu.h>
  50
  51 / {
  52         interrupt-parent = <&gic>;
  53         #address-cells = <1>;
  54         #size-cells = <1>;
  55
  56         chosen {
  57                 #address-cells = <1>;
  58                 #size-cells = <1>;
  59                 ranges;
  60
  61                 framebuffer-hdmi {
  62                         compatible = "allwinner,simple-framebuffer",
  63                                      "simple-framebuffer";
  64                         allwinner,pipeline = "mixer0-lcd0-hdmi";
  65                         clocks = <&display_clocks CLK_MIXER0>,
  66                                  <&ccu CLK_TCON0>, <&ccu CLK_HDMI>;
  67                         status = "disabled";
  68                 };
  69
  70                 framebuffer-tve {
  71                         compatible = "allwinner,simple-framebuffer",
  72                                      "simple-framebuffer";
  73                         allwinner,pipeline = "mixer1-lcd1-tve";
  74                         clocks = <&display_clocks CLK_MIXER1>,
  75                                  <&ccu CLK_TVE>;
  76                         status = "disabled";
  77                 };
  78         };
  79
  80         clocks {
  81                 #address-cells = <1>;
  82                 #size-cells = <1>;
  83                 ranges;
  84
  85                 osc24M: osc24M_clk {
  86                         #clock-cells = <0>;
  87                         compatible = "fixed-clock";
  88                         clock-frequency = <24000000>;
  89                         clock-output-names = "osc24M";
  90                 };
  91
  92                 osc32k: osc32k_clk {
  93                         #clock-cells = <0>;
  94                         compatible = "fixed-clock";
  95                         clock-frequency = <32768>;
  96                         clock-output-names = "osc32k";
  97                 };
  98
  99                 iosc: internal-osc-clk {
 100                         #clock-cells = <0>;
 101                         compatible = "fixed-clock";
 102                         clock-frequency = <16000000>;
 103                         clock-accuracy = <300000000>;
 104                         clock-output-names = "iosc";
 105                 };
 106         };
 107
 108         soc {
 109                 compatible = "simple-bus";
 110                 #address-cells = <1>;
 111                 #size-cells = <1>;
 112                 ranges;
 113
 114                 display_clocks: clock@1000000 {
 115                         /* compatible is in per SoC .dtsi file */
 116                         reg = <0x01000000 0x100000>;
 117                         clocks = <&ccu CLK_DE>,
 118                                  <&ccu CLK_BUS_DE>;
 119                         clock-names = "mod",
 120                                       "bus";
 121                         resets = <&ccu RST_BUS_DE>;
 122                         #clock-cells = <1>;
 123                         #reset-cells = <1>;
 124                 };
 125
 126                 syscon: syscon@1c00000 {
 127                         compatible = "allwinner,sun8i-h3-system-controller",
 128                                 "syscon";
 129                         reg = <0x01c00000 0x1000>;
 130                 };
 131
 132                 dma: dma-controller@1c02000 {
 133                         compatible = "allwinner,sun8i-h3-dma";
 134                         reg = <0x01c02000 0x1000>;
 135                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 136                         clocks = <&ccu CLK_BUS_DMA>;
 137                         resets = <&ccu RST_BUS_DMA>;
 138                         #dma-cells = <1>;
 139                 };
 140
 141                 mmc0: mmc@1c0f000 {
 142                         /* compatible and clocks are in per SoC .dtsi file */
 143                         reg = <0x01c0f000 0x1000>;
 144                         resets = <&ccu RST_BUS_MMC0>;
 145                         reset-names = "ahb";
 146                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 147                         status = "disabled";
 148                         #address-cells = <1>;
 149                         #size-cells = <0>;
 150                 };
 151
 152                 mmc1: mmc@1c10000 {
 153                         /* compatible and clocks are in per SoC .dtsi file */
 154                         reg = <0x01c10000 0x1000>;
 155                         resets = <&ccu RST_BUS_MMC1>;
 156                         reset-names = "ahb";
 157                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 158                         status = "disabled";
 159                         #address-cells = <1>;
 160                         #size-cells = <0>;
 161                 };
 162
 163                 mmc2: mmc@1c11000 {
 164                         /* compatible and clocks are in per SoC .dtsi file */
 165                         reg = <0x01c11000 0x1000>;
 166                         resets = <&ccu RST_BUS_MMC2>;
 167                         reset-names = "ahb";
 168                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 169                         status = "disabled";
 170                         #address-cells = <1>;
 171                         #size-cells = <0>;
 172                 };
 173
 174                 usb_otg: usb@1c19000 {
 175                         compatible = "allwinner,sun8i-h3-musb";
 176                         reg = <0x01c19000 0x400>;
 177                         clocks = <&ccu CLK_BUS_OTG>;
 178                         resets = <&ccu RST_BUS_OTG>;
 179                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 180                         interrupt-names = "mc";
 181                         phys = <&usbphy 0>;
 182                         phy-names = "usb";
 183                         extcon = <&usbphy 0>;
 184                         status = "disabled";
 185                 };
 186
 187                 usbphy: phy@1c19400 {
 188                         compatible = "allwinner,sun8i-h3-usb-phy";
 189                         reg = <0x01c19400 0x2c>,
 190                               <0x01c1a800 0x4>,
 191                               <0x01c1b800 0x4>,
 192                               <0x01c1c800 0x4>,
 193                               <0x01c1d800 0x4>;
 194                         reg-names = "phy_ctrl",
 195                                     "pmu0",
 196                                     "pmu1",
 197                                     "pmu2",
 198                                     "pmu3";
 199                         clocks = <&ccu CLK_USB_PHY0>,
 200                                  <&ccu CLK_USB_PHY1>,
 201                                  <&ccu CLK_USB_PHY2>,
 202                                  <&ccu CLK_USB_PHY3>;
 203                         clock-names = "usb0_phy",
 204                                       "usb1_phy",
 205                                       "usb2_phy",
 206                                       "usb3_phy";
 207                         resets = <&ccu RST_USB_PHY0>,
 208                                  <&ccu RST_USB_PHY1>,
 209                                  <&ccu RST_USB_PHY2>,
 210                                  <&ccu RST_USB_PHY3>;
 211                         reset-names = "usb0_reset",
 212                                       "usb1_reset",
 213                                       "usb2_reset",
 214                                       "usb3_reset";
 215                         status = "disabled";
 216                         #phy-cells = <1>;
 217                 };
 218
 219                 ehci0: usb@1c1a000 {
 220                         compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
 221                         reg = <0x01c1a000 0x100>;
 222                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 223                         clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>;
 224                         resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
 225                         status = "disabled";
 226                 };
 227
 228                 ohci0: usb@1c1a400 {
 229                         compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
 230                         reg = <0x01c1a400 0x100>;
 231                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 232                         clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>,
 233                                  <&ccu CLK_USB_OHCI0>;
 234                         resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
 235                         status = "disabled";
 236                 };
 237
 238                 ehci1: usb@1c1b000 {
 239                         compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
 240                         reg = <0x01c1b000 0x100>;
 241                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 242                         clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>;
 243                         resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
 244                         phys = <&usbphy 1>;
 245                         phy-names = "usb";
 246                         status = "disabled";
 247                 };
 248
 249                 ohci1: usb@1c1b400 {
 250                         compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
 251                         reg = <0x01c1b400 0x100>;
 252                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 253                         clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>,
 254                                  <&ccu CLK_USB_OHCI1>;
 255                         resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
 256                         phys = <&usbphy 1>;
 257                         phy-names = "usb";
 258                         status = "disabled";
 259                 };
 260
 261                 ehci2: usb@1c1c000 {
 262                         compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
 263                         reg = <0x01c1c000 0x100>;
 264                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 265                         clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>;
 266                         resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
 267                         phys = <&usbphy 2>;
 268                         phy-names = "usb";
 269                         status = "disabled";
 270                 };
 271
 272                 ohci2: usb@1c1c400 {
 273                         compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
 274                         reg = <0x01c1c400 0x100>;
 275                         interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 276                         clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>,
 277                                  <&ccu CLK_USB_OHCI2>;
 278                         resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
 279                         phys = <&usbphy 2>;
 280                         phy-names = "usb";
 281                         status = "disabled";
 282                 };
 283
 284                 ehci3: usb@1c1d000 {
 285                         compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
 286                         reg = <0x01c1d000 0x100>;
 287                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 288                         clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>;
 289                         resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
 290                         phys = <&usbphy 3>;
 291                         phy-names = "usb";
 292                         status = "disabled";
 293                 };
 294
 295                 ohci3: usb@1c1d400 {
 296                         compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
 297                         reg = <0x01c1d400 0x100>;
 298                         interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 299                         clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>,
 300                                  <&ccu CLK_USB_OHCI3>;
 301                         resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
 302                         phys = <&usbphy 3>;
 303                         phy-names = "usb";
 304                         status = "disabled";
 305                 };
 306
 307                 ccu: clock@1c20000 {
 308                         /* compatible is in per SoC .dtsi file */
 309                         reg = <0x01c20000 0x400>;
 310                         clocks = <&osc24M>, <&osc32k>;
 311                         clock-names = "hosc", "losc";
 312                         #clock-cells = <1>;
 313                         #reset-cells = <1>;
 314                 };
 315
 316                 pio: pinctrl@1c20800 {
 317                         /* compatible is in per SoC .dtsi file */
 318                         reg = <0x01c20800 0x400>;
 319                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 320                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 321                         clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
 322                         clock-names = "apb", "hosc", "losc";
 323                         gpio-controller;
 324                         #gpio-cells = <3>;
 325                         interrupt-controller;
 326                         #interrupt-cells = <3>;
 327
 328                         emac_rgmii_pins: emac0 {
 329                                 pins = "PD0", "PD1", "PD2", "PD3", "PD4",
 330                                        "PD5", "PD7", "PD8", "PD9", "PD10",
 331                                        "PD12", "PD13", "PD15", "PD16", "PD17";
 332                                 function = "emac";
 333                                 drive-strength = <40>;
 334                         };
 335
 336                         i2c0_pins: i2c0 {
 337                                 pins = "PA11", "PA12";
 338                                 function = "i2c0";
 339                         };
 340
 341                         i2c1_pins: i2c1 {
 342                                 pins = "PA18", "PA19";
 343                                 function = "i2c1";
 344                         };
 345
 346                         i2c2_pins: i2c2 {
 347                                 pins = "PE12", "PE13";
 348                                 function = "i2c2";
 349                         };
 350
 351                         mmc0_pins_a: mmc0 {
 352                                 pins = "PF0", "PF1", "PF2", "PF3",
 353                                        "PF4", "PF5";
 354                                 function = "mmc0";
 355                                 drive-strength = <30>;
 356                                 bias-pull-up;
 357                         };
 358
 359                         mmc0_cd_pin: mmc0_cd_pin {
 360                                 pins = "PF6";
 361                                 function = "gpio_in";
 362                                 bias-pull-up;
 363                         };
 364
 365                         mmc1_pins_a: mmc1 {
 366                                 pins = "PG0", "PG1", "PG2", "PG3",
 367                                        "PG4", "PG5";
 368                                 function = "mmc1";
 369                                 drive-strength = <30>;
 370                                 bias-pull-up;
 371                         };
 372
 373                         mmc2_8bit_pins: mmc2_8bit {
 374                                 pins = "PC5", "PC6", "PC8",
 375                                        "PC9", "PC10", "PC11",
 376                                        "PC12", "PC13", "PC14",
 377                                        "PC15", "PC16";
 378                                 function = "mmc2";
 379                                 drive-strength = <30>;
 380                                 bias-pull-up;
 381                         };
 382
 383                         spdif_tx_pins_a: spdif {
 384                                 pins = "PA17";
 385                                 function = "spdif";
 386                         };
 387
 388                         spi0_pins: spi0 {
 389                                 pins = "PC0", "PC1", "PC2", "PC3";
 390                                 function = "spi0";
 391                         };
 392
 393                         spi1_pins: spi1 {
 394                                 pins = "PA15", "PA16", "PA14", "PA13";
 395                                 function = "spi1";
 396                         };
 397
 398                         uart0_pins_a: uart0 {
 399                                 pins = "PA4", "PA5";
 400                                 function = "uart0";
 401                         };
 402
 403                         uart1_pins: uart1 {
 404                                 pins = "PG6", "PG7";
 405                                 function = "uart1";
 406                         };
 407
 408                         uart1_rts_cts_pins: uart1_rts_cts {
 409                                 pins = "PG8", "PG9";
 410                                 function = "uart1";
 411                         };
 412
 413                         uart2_pins: uart2 {
 414                                 pins = "PA0", "PA1";
 415                                 function = "uart2";
 416                         };
 417
 418                         uart3_pins: uart3 {
 419                                 pins = "PA13", "PA14";
 420                                 function = "uart3";
 421                         };
 422
 423                         uart3_rts_cts_pins: uart3_rts_cts {
 424                                 pins = "PA15", "PA16";
 425                                 function = "uart3";
 426                         };
 427                 };
 428
 429                 timer@1c20c00 {
 430                         compatible = "allwinner,sun4i-a10-timer";
 431                         reg = <0x01c20c00 0xa0>;
 432                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 433                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 434                         clocks = <&osc24M>;
 435                 };
 436
 437                 emac: ethernet@1c30000 {
 438                         compatible = "allwinner,sun8i-h3-emac";
 439                         syscon = <&syscon>;
 440                         reg = <0x01c30000 0x10000>;
 441                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 442                         interrupt-names = "macirq";
 443                         resets = <&ccu RST_BUS_EMAC>;
 444                         reset-names = "stmmaceth";
 445                         clocks = <&ccu CLK_BUS_EMAC>;
 446                         clock-names = "stmmaceth";
 447                         #address-cells = <1>;
 448                         #size-cells = <0>;
 449                         status = "disabled";
 450
 451                         mdio: mdio {
 452                                 #address-cells = <1>;
 453                                 #size-cells = <0>;
 454                                 compatible = "snps,dwmac-mdio";
 455                         };
 456
 457                         mdio-mux {
 458                                 compatible = "allwinner,sun8i-h3-mdio-mux";
 459                                 #address-cells = <1>;
 460                                 #size-cells = <0>;
 461
 462                                 mdio-parent-bus = <&mdio>;
 463                                 /* Only one MDIO is usable at the time */
 464                                 internal_mdio: mdio@1 {
 465                                         compatible = "allwinner,sun8i-h3-mdio-internal";
 466                                         reg = <1>;
 467                                         #address-cells = <1>;
 468                                         #size-cells = <0>;
 469
 470                                         int_mii_phy: ethernet-phy@1 {
 471                                                 compatible = "ethernet-phy-ieee802.3-c22";
 472                                                 reg = <1>;
 473                                                 clocks = <&ccu CLK_BUS_EPHY>;
 474                                                 resets = <&ccu RST_BUS_EPHY>;
 475                                         };
 476                                 };
 477
 478                                 external_mdio: mdio@2 {
 479                                         reg = <2>;
 480                                         #address-cells = <1>;
 481                                         #size-cells = <0>;
 482                                 };
 483                         };
 484                 };
 485
 486                 spi0: spi@1c68000 {
 487                         compatible = "allwinner,sun8i-h3-spi";
 488                         reg = <0x01c68000 0x1000>;
 489                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 490                         clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
 491                         clock-names = "ahb", "mod";
 492                         dmas = <&dma 23>, <&dma 23>;
 493                         dma-names = "rx", "tx";
 494                         pinctrl-names = "default";
 495                         pinctrl-0 = <&spi0_pins>;
 496                         resets = <&ccu RST_BUS_SPI0>;
 497                         status = "disabled";
 498                         #address-cells = <1>;
 499                         #size-cells = <0>;
 500                 };
 501
 502                 spi1: spi@1c69000 {
 503                         compatible = "allwinner,sun8i-h3-spi";
 504                         reg = <0x01c69000 0x1000>;
 505                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 506                         clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
 507                         clock-names = "ahb", "mod";
 508                         dmas = <&dma 24>, <&dma 24>;
 509                         dma-names = "rx", "tx";
 510                         pinctrl-names = "default";
 511                         pinctrl-0 = <&spi1_pins>;
 512                         resets = <&ccu RST_BUS_SPI1>;
 513                         status = "disabled";
 514                         #address-cells = <1>;
 515                         #size-cells = <0>;
 516                 };
 517
 518                 wdt0: watchdog@1c20ca0 {
 519                         compatible = "allwinner,sun6i-a31-wdt";
 520                         reg = <0x01c20ca0 0x20>;
 521                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 522                 };
 523
 524                 spdif: spdif@1c21000 {
 525                         #sound-dai-cells = <0>;
 526                         compatible = "allwinner,sun8i-h3-spdif";
 527                         reg = <0x01c21000 0x400>;
 528                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 529                         clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
 530                         resets = <&ccu RST_BUS_SPDIF>;
 531                         clock-names = "apb", "spdif";
 532                         dmas = <&dma 2>;
 533                         dma-names = "tx";
 534                         status = "disabled";
 535                 };
 536
 537                 pwm: pwm@1c21400 {
 538                         compatible = "allwinner,sun8i-h3-pwm";
 539                         reg = <0x01c21400 0x8>;
 540                         clocks = <&osc24M>;
 541                         #pwm-cells = <3>;
 542                         status = "disabled";
 543                 };
 544
 545                 i2s0: i2s@1c22000 {
 546                         #sound-dai-cells = <0>;
 547                         compatible = "allwinner,sun8i-h3-i2s";
 548                         reg = <0x01c22000 0x400>;
 549                         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 550                         clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
 551                         clock-names = "apb", "mod";
 552                         dmas = <&dma 3>, <&dma 3>;
 553                         resets = <&ccu RST_BUS_I2S0>;
 554                         dma-names = "rx", "tx";
 555                         status = "disabled";
 556                 };
 557
 558                 i2s1: i2s@1c22400 {
 559                         #sound-dai-cells = <0>;
 560                         compatible = "allwinner,sun8i-h3-i2s";
 561                         reg = <0x01c22400 0x400>;
 562                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 563                         clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
 564                         clock-names = "apb", "mod";
 565                         dmas = <&dma 4>, <&dma 4>;
 566                         resets = <&ccu RST_BUS_I2S1>;
 567                         dma-names = "rx", "tx";
 568                         status = "disabled";
 569                 };
 570
 571                 codec: codec@1c22c00 {
 572                         #sound-dai-cells = <0>;
 573                         compatible = "allwinner,sun8i-h3-codec";
 574                         reg = <0x01c22c00 0x400>;
 575                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 576                         clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
 577                         clock-names = "apb", "codec";
 578                         resets = <&ccu RST_BUS_CODEC>;
 579                         dmas = <&dma 15>, <&dma 15>;
 580                         dma-names = "rx", "tx";
 581                         allwinner,codec-analog-controls = <&codec_analog>;
 582                         status = "disabled";
 583                 };
 584
 585                 uart0: serial@1c28000 {
 586                         compatible = "snps,dw-apb-uart";
 587                         reg = <0x01c28000 0x400>;
 588                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 589                         reg-shift = <2>;
 590                         reg-io-width = <4>;
 591                         clocks = <&ccu CLK_BUS_UART0>;
 592                         resets = <&ccu RST_BUS_UART0>;
 593                         dmas = <&dma 6>, <&dma 6>;
 594                         dma-names = "rx", "tx";
 595                         status = "disabled";
 596                 };
 597
 598                 uart1: serial@1c28400 {
 599                         compatible = "snps,dw-apb-uart";
 600                         reg = <0x01c28400 0x400>;
 601                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 602                         reg-shift = <2>;
 603                         reg-io-width = <4>;
 604                         clocks = <&ccu CLK_BUS_UART1>;
 605                         resets = <&ccu RST_BUS_UART1>;
 606                         dmas = <&dma 7>, <&dma 7>;
 607                         dma-names = "rx", "tx";
 608                         status = "disabled";
 609                 };
 610
 611                 uart2: serial@1c28800 {
 612                         compatible = "snps,dw-apb-uart";
 613                         reg = <0x01c28800 0x400>;
 614                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 615                         reg-shift = <2>;
 616                         reg-io-width = <4>;
 617                         clocks = <&ccu CLK_BUS_UART2>;
 618                         resets = <&ccu RST_BUS_UART2>;
 619                         dmas = <&dma 8>, <&dma 8>;
 620                         dma-names = "rx", "tx";
 621                         status = "disabled";
 622                 };
 623
 624                 uart3: serial@1c28c00 {
 625                         compatible = "snps,dw-apb-uart";
 626                         reg = <0x01c28c00 0x400>;
 627                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 628                         reg-shift = <2>;
 629                         reg-io-width = <4>;
 630                         clocks = <&ccu CLK_BUS_UART3>;
 631                         resets = <&ccu RST_BUS_UART3>;
 632                         dmas = <&dma 9>, <&dma 9>;
 633                         dma-names = "rx", "tx";
 634                         status = "disabled";
 635                 };
 636
 637                 i2c0: i2c@1c2ac00 {
 638                         compatible = "allwinner,sun6i-a31-i2c";
 639                         reg = <0x01c2ac00 0x400>;
 640                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 641                         clocks = <&ccu CLK_BUS_I2C0>;
 642                         resets = <&ccu RST_BUS_I2C0>;
 643                         pinctrl-names = "default";
 644                         pinctrl-0 = <&i2c0_pins>;
 645                         status = "disabled";
 646                         #address-cells = <1>;
 647                         #size-cells = <0>;
 648                 };
 649
 650                 i2c1: i2c@1c2b000 {
 651                         compatible = "allwinner,sun6i-a31-i2c";
 652                         reg = <0x01c2b000 0x400>;
 653                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 654                         clocks = <&ccu CLK_BUS_I2C1>;
 655                         resets = <&ccu RST_BUS_I2C1>;
 656                         pinctrl-names = "default";
 657                         pinctrl-0 = <&i2c1_pins>;
 658                         status = "disabled";
 659                         #address-cells = <1>;
 660                         #size-cells = <0>;
 661                 };
 662
 663                 i2c2: i2c@1c2b400 {
 664                         compatible = "allwinner,sun6i-a31-i2c";
 665                         reg = <0x01c2b400 0x400>;
 666                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 667                         clocks = <&ccu CLK_BUS_I2C2>;
 668                         resets = <&ccu RST_BUS_I2C2>;
 669                         pinctrl-names = "default";
 670                         pinctrl-0 = <&i2c2_pins>;
 671                         status = "disabled";
 672                         #address-cells = <1>;
 673                         #size-cells = <0>;
 674                 };
 675
 676                 gic: interrupt-controller@1c81000 {
 677                         compatible = "arm,gic-400";
 678                         reg = <0x01c81000 0x1000>,
 679                               <0x01c82000 0x2000>,
 680                               <0x01c84000 0x2000>,
 681                               <0x01c86000 0x2000>;
 682                         interrupt-controller;
 683                         #interrupt-cells = <3>;
 684                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 685                 };
 686
 687                 rtc: rtc@1f00000 {
 688                         compatible = "allwinner,sun6i-a31-rtc";
 689                         reg = <0x01f00000 0x54>;
 690                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 691                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 692                 };
 693
 694                 r_ccu: clock@1f01400 {
 695                         compatible = "allwinner,sun8i-h3-r-ccu";
 696                         reg = <0x01f01400 0x100>;
 697                         clocks = <&osc24M>, <&osc32k>, <&iosc>,
 698                                  <&ccu 9>;
 699                         clock-names = "hosc", "losc", "iosc", "pll-periph";
 700                         #clock-cells = <1>;
 701                         #reset-cells = <1>;
 702                 };
 703
 704                 codec_analog: codec-analog@1f015c0 {
 705                         compatible = "allwinner,sun8i-h3-codec-analog";
 706                         reg = <0x01f015c0 0x4>;
 707                 };
 708
 709                 ir: ir@1f02000 {
 710                         compatible = "allwinner,sun5i-a13-ir";
 711                         clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
 712                         clock-names = "apb", "ir";
 713                         resets = <&r_ccu RST_APB0_IR>;
 714                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 715                         reg = <0x01f02000 0x40>;
 716                         status = "disabled";
 717                 };
 718
 719                 r_pio: pinctrl@1f02c00 {
 720                         compatible = "allwinner,sun8i-h3-r-pinctrl";
 721                         reg = <0x01f02c00 0x400>;
 722                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 723                         clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
 724                         clock-names = "apb", "hosc", "losc";
 725                         gpio-controller;
 726                         #gpio-cells = <3>;
 727                         interrupt-controller;
 728                         #interrupt-cells = <3>;
 729
 730                         ir_pins_a: ir {
 731                                 pins = "PL11";
 732                                 function = "s_cir_rx";
 733                         };
 734                 };
 735         };
 736 };