sys/gnu/dts/arm/tegra114.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include <dt-bindings/clock/tegra114-car.h>
   3 #include <dt-bindings/gpio/tegra-gpio.h>
   4 #include <dt-bindings/memory/tegra114-mc.h>
   5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7
   8 #include "skeleton.dtsi"
   9
  10 / {
  11         compatible = "nvidia,tegra114";
  12         interrupt-parent = <&lic>;
  13
  14         host1x@50000000 {
  15                 compatible = "nvidia,tegra114-host1x", "simple-bus";
  16                 reg = <0x50000000 0x00028000>;
  17                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
  18                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
  19                 clocks = <&tegra_car TEGRA114_CLK_HOST1X>;
  20                 resets = <&tegra_car 28>;
  21                 reset-names = "host1x";
  22                 iommus = <&mc TEGRA_SWGROUP_HC>;
  23
  24                 #address-cells = <1>;
  25                 #size-cells = <1>;
  26
  27                 ranges = <0x54000000 0x54000000 0x01000000>;
  28
  29                 gr2d@54140000 {
  30                         compatible = "nvidia,tegra114-gr2d", "nvidia,tegra20-gr2d";
  31                         reg = <0x54140000 0x00040000>;
  32                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
  33                         clocks = <&tegra_car TEGRA114_CLK_GR2D>;
  34                         resets = <&tegra_car 21>;
  35                         reset-names = "2d";
  36
  37                         iommus = <&mc TEGRA_SWGROUP_G2>;
  38                 };
  39
  40                 gr3d@54180000 {
  41                         compatible = "nvidia,tegra114-gr3d", "nvidia,tegra20-gr3d";
  42                         reg = <0x54180000 0x00040000>;
  43                         clocks = <&tegra_car TEGRA114_CLK_GR3D>;
  44                         resets = <&tegra_car 24>;
  45                         reset-names = "3d";
  46
  47                         iommus = <&mc TEGRA_SWGROUP_NV>;
  48                 };
  49
  50                 dc@54200000 {
  51                         compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc";
  52                         reg = <0x54200000 0x00040000>;
  53                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
  54                         clocks = <&tegra_car TEGRA114_CLK_DISP1>,
  55                                  <&tegra_car TEGRA114_CLK_PLL_P>;
  56                         clock-names = "dc", "parent";
  57                         resets = <&tegra_car 27>;
  58                         reset-names = "dc";
  59
  60                         iommus = <&mc TEGRA_SWGROUP_DC>;
  61
  62                         nvidia,head = <0>;
  63
  64                         rgb {
  65                                 status = "disabled";
  66                         };
  67                 };
  68
  69                 dc@54240000 {
  70                         compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc";
  71                         reg = <0x54240000 0x00040000>;
  72                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
  73                         clocks = <&tegra_car TEGRA114_CLK_DISP2>,
  74                                  <&tegra_car TEGRA114_CLK_PLL_P>;
  75                         clock-names = "dc", "parent";
  76                         resets = <&tegra_car 26>;
  77                         reset-names = "dc";
  78
  79                         iommus = <&mc TEGRA_SWGROUP_DCB>;
  80
  81                         nvidia,head = <1>;
  82
  83                         rgb {
  84                                 status = "disabled";
  85                         };
  86                 };
  87
  88                 hdmi@54280000 {
  89                         compatible = "nvidia,tegra114-hdmi";
  90                         reg = <0x54280000 0x00040000>;
  91                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
  92                         clocks = <&tegra_car TEGRA114_CLK_HDMI>,
  93                                  <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>;
  94                         clock-names = "hdmi", "parent";
  95                         resets = <&tegra_car 51>;
  96                         reset-names = "hdmi";
  97                         status = "disabled";
  98                 };
  99
 100                 dsi@54300000 {
 101                         compatible = "nvidia,tegra114-dsi";
 102                         reg = <0x54300000 0x00040000>;
 103                         clocks = <&tegra_car TEGRA114_CLK_DSIA>,
 104                                  <&tegra_car TEGRA114_CLK_DSIALP>,
 105                                  <&tegra_car TEGRA114_CLK_PLL_D_OUT0>;
 106                         clock-names = "dsi", "lp", "parent";
 107                         resets = <&tegra_car 48>;
 108                         reset-names = "dsi";
 109                         nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */
 110                         status = "disabled";
 111
 112                         #address-cells = <1>;
 113                         #size-cells = <0>;
 114                 };
 115
 116                 dsi@54400000 {
 117                         compatible = "nvidia,tegra114-dsi";
 118                         reg = <0x54400000 0x00040000>;
 119                         clocks = <&tegra_car TEGRA114_CLK_DSIB>,
 120                                  <&tegra_car TEGRA114_CLK_DSIBLP>,
 121                                  <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>;
 122                         clock-names = "dsi", "lp", "parent";
 123                         resets = <&tegra_car 82>;
 124                         reset-names = "dsi";
 125                         nvidia,mipi-calibrate = <&mipi 0x180>; /* DSIC & DSID pads */
 126                         status = "disabled";
 127
 128                         #address-cells = <1>;
 129                         #size-cells = <0>;
 130                 };
 131         };
 132
 133         gic: interrupt-controller@50041000 {
 134                 compatible = "arm,cortex-a15-gic";
 135                 #interrupt-cells = <3>;
 136                 interrupt-controller;
 137                 reg = <0x50041000 0x1000>,
 138                       <0x50042000 0x1000>,
 139                       <0x50044000 0x2000>,
 140                       <0x50046000 0x2000>;
 141                 interrupts = <GIC_PPI 9
 142                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 143                 interrupt-parent = <&gic>;
 144         };
 145
 146         lic: interrupt-controller@60004000 {
 147                 compatible = "nvidia,tegra114-ictlr", "nvidia,tegra30-ictlr";
 148                 reg = <0x60004000 0x100>,
 149                       <0x60004100 0x50>,
 150                       <0x60004200 0x50>,
 151                       <0x60004300 0x50>,
 152                       <0x60004400 0x50>;
 153                 interrupt-controller;
 154                 #interrupt-cells = <3>;
 155                 interrupt-parent = <&gic>;
 156         };
 157
 158         timer@60005000 {
 159                 compatible = "nvidia,tegra114-timer", "nvidia,tegra30-timer", "nvidia,tegra20-timer";
 160                 reg = <0x60005000 0x400>;
 161                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 162                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 163                              <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 164                              <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
 165                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 166                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 167                 clocks = <&tegra_car TEGRA114_CLK_TIMER>;
 168         };
 169
 170         tegra_car: clock@60006000 {
 171                 compatible = "nvidia,tegra114-car";
 172                 reg = <0x60006000 0x1000>;
 173                 #clock-cells = <1>;
 174                 #reset-cells = <1>;
 175         };
 176
 177         flow-controller@60007000 {
 178                 compatible = "nvidia,tegra114-flowctrl";
 179                 reg = <0x60007000 0x1000>;
 180         };
 181
 182         apbdma: dma@6000a000 {
 183                 compatible = "nvidia,tegra114-apbdma";
 184                 reg = <0x6000a000 0x1400>;
 185                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 186                              <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 187                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 188                              <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 189                              <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
 190                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 191                              <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 192                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 193                              <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 194                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 195                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 196                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 197                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 198                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 199                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 200                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
 201                              <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
 202                              <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
 203                              <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
 204                              <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
 205                              <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
 206                              <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
 207                              <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 208                              <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 209                              <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
 210                              <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
 211                              <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
 212                              <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
 213                              <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
 214                              <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
 215                              <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 216                              <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 217                 clocks = <&tegra_car TEGRA114_CLK_APBDMA>;
 218                 resets = <&tegra_car 34>;
 219                 reset-names = "dma";
 220                 #dma-cells = <1>;
 221         };
 222
 223         ahb: ahb@6000c000 {
 224                 compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb";
 225                 reg = <0x6000c000 0x150>;
 226         };
 227
 228         gpio: gpio@6000d000 {
 229                 compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
 230                 reg = <0x6000d000 0x1000>;
 231                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
 232                              <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 233                              <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
 234                              <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
 235                              <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 236                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 237                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
 238                              <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 239                 #gpio-cells = <2>;
 240                 gpio-controller;
 241                 #interrupt-cells = <2>;
 242                 interrupt-controller;
 243                 /*
 244                 gpio-ranges = <&pinmux 0 0 246>;
 245                 */
 246         };
 247
 248         apbmisc@70000800 {
 249                 compatible = "nvidia,tegra114-apbmisc", "nvidia,tegra20-apbmisc";
 250                 reg = <0x70000800 0x64   /* Chip revision */
 251                        0x70000008 0x04>; /* Strapping options */
 252         };
 253
 254         pinmux: pinmux@70000868 {
 255                 compatible = "nvidia,tegra114-pinmux";
 256                 reg = <0x70000868 0x148         /* Pad control registers */
 257                        0x70003000 0x40c>;       /* Mux registers */
 258         };
 259
 260         /*
 261          * There are two serial driver i.e. 8250 based simple serial
 262          * driver and APB DMA based serial driver for higher baudrate
 263          * and performace. To enable the 8250 based driver, the compatible
 264          * is "nvidia,tegra114-uart", "nvidia,tegra20-uart" and to enable
 265          * the APB DMA based serial driver, the compatible is
 266          * "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart".
 267          */
 268         uarta: serial@70006000 {
 269                 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
 270                 reg = <0x70006000 0x40>;
 271                 reg-shift = <2>;
 272                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 273                 clocks = <&tegra_car TEGRA114_CLK_UARTA>;
 274                 resets = <&tegra_car 6>;
 275                 reset-names = "serial";
 276                 dmas = <&apbdma 8>, <&apbdma 8>;
 277                 dma-names = "rx", "tx";
 278                 status = "disabled";
 279         };
 280
 281         uartb: serial@70006040 {
 282                 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
 283                 reg = <0x70006040 0x40>;
 284                 reg-shift = <2>;
 285                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 286                 clocks = <&tegra_car TEGRA114_CLK_UARTB>;
 287                 resets = <&tegra_car 7>;
 288                 reset-names = "serial";
 289                 dmas = <&apbdma 9>, <&apbdma 9>;
 290                 dma-names = "rx", "tx";
 291                 status = "disabled";
 292         };
 293
 294         uartc: serial@70006200 {
 295                 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
 296                 reg = <0x70006200 0x100>;
 297                 reg-shift = <2>;
 298                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 299                 clocks = <&tegra_car TEGRA114_CLK_UARTC>;
 300                 resets = <&tegra_car 55>;
 301                 reset-names = "serial";
 302                 dmas = <&apbdma 10>, <&apbdma 10>;
 303                 dma-names = "rx", "tx";
 304                 status = "disabled";
 305         };
 306
 307         uartd: serial@70006300 {
 308                 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
 309                 reg = <0x70006300 0x100>;
 310                 reg-shift = <2>;
 311                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 312                 clocks = <&tegra_car TEGRA114_CLK_UARTD>;
 313                 resets = <&tegra_car 65>;
 314                 reset-names = "serial";
 315                 dmas = <&apbdma 19>, <&apbdma 19>;
 316                 dma-names = "rx", "tx";
 317                 status = "disabled";
 318         };
 319
 320         pwm: pwm@7000a000 {
 321                 compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm";
 322                 reg = <0x7000a000 0x100>;
 323                 #pwm-cells = <2>;
 324                 clocks = <&tegra_car TEGRA114_CLK_PWM>;
 325                 resets = <&tegra_car 17>;
 326                 reset-names = "pwm";
 327                 status = "disabled";
 328         };
 329
 330         i2c@7000c000 {
 331                 compatible = "nvidia,tegra114-i2c";
 332                 reg = <0x7000c000 0x100>;
 333                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 334                 #address-cells = <1>;
 335                 #size-cells = <0>;
 336                 clocks = <&tegra_car TEGRA114_CLK_I2C1>;
 337                 clock-names = "div-clk";
 338                 resets = <&tegra_car 12>;
 339                 reset-names = "i2c";
 340                 dmas = <&apbdma 21>, <&apbdma 21>;
 341                 dma-names = "rx", "tx";
 342                 status = "disabled";
 343         };
 344
 345         i2c@7000c400 {
 346                 compatible = "nvidia,tegra114-i2c";
 347                 reg = <0x7000c400 0x100>;
 348                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 349                 #address-cells = <1>;
 350                 #size-cells = <0>;
 351                 clocks = <&tegra_car TEGRA114_CLK_I2C2>;
 352                 clock-names = "div-clk";
 353                 resets = <&tegra_car 54>;
 354                 reset-names = "i2c";
 355                 dmas = <&apbdma 22>, <&apbdma 22>;
 356                 dma-names = "rx", "tx";
 357                 status = "disabled";
 358         };
 359
 360         i2c@7000c500 {
 361                 compatible = "nvidia,tegra114-i2c";
 362                 reg = <0x7000c500 0x100>;
 363                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 364                 #address-cells = <1>;
 365                 #size-cells = <0>;
 366                 clocks = <&tegra_car TEGRA114_CLK_I2C3>;
 367                 clock-names = "div-clk";
 368                 resets = <&tegra_car 67>;
 369                 reset-names = "i2c";
 370                 dmas = <&apbdma 23>, <&apbdma 23>;
 371                 dma-names = "rx", "tx";
 372                 status = "disabled";
 373         };
 374
 375         i2c@7000c700 {
 376                 compatible = "nvidia,tegra114-i2c";
 377                 reg = <0x7000c700 0x100>;
 378                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 379                 #address-cells = <1>;
 380                 #size-cells = <0>;
 381                 clocks = <&tegra_car TEGRA114_CLK_I2C4>;
 382                 clock-names = "div-clk";
 383                 resets = <&tegra_car 103>;
 384                 reset-names = "i2c";
 385                 dmas = <&apbdma 26>, <&apbdma 26>;
 386                 dma-names = "rx", "tx";
 387                 status = "disabled";
 388         };
 389
 390         i2c@7000d000 {
 391                 compatible = "nvidia,tegra114-i2c";
 392                 reg = <0x7000d000 0x100>;
 393                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 394                 #address-cells = <1>;
 395                 #size-cells = <0>;
 396                 clocks = <&tegra_car TEGRA114_CLK_I2C5>;
 397                 clock-names = "div-clk";
 398                 resets = <&tegra_car 47>;
 399                 reset-names = "i2c";
 400                 dmas = <&apbdma 24>, <&apbdma 24>;
 401                 dma-names = "rx", "tx";
 402                 status = "disabled";
 403         };
 404
 405         spi@7000d400 {
 406                 compatible = "nvidia,tegra114-spi";
 407                 reg = <0x7000d400 0x200>;
 408                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 409                 #address-cells = <1>;
 410                 #size-cells = <0>;
 411                 clocks = <&tegra_car TEGRA114_CLK_SBC1>;
 412                 clock-names = "spi";
 413                 resets = <&tegra_car 41>;
 414                 reset-names = "spi";
 415                 dmas = <&apbdma 15>, <&apbdma 15>;
 416                 dma-names = "rx", "tx";
 417                 status = "disabled";
 418         };
 419
 420         spi@7000d600 {
 421                 compatible = "nvidia,tegra114-spi";
 422                 reg = <0x7000d600 0x200>;
 423                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 424                 #address-cells = <1>;
 425                 #size-cells = <0>;
 426                 clocks = <&tegra_car TEGRA114_CLK_SBC2>;
 427                 clock-names = "spi";
 428                 resets = <&tegra_car 44>;
 429                 reset-names = "spi";
 430                 dmas = <&apbdma 16>, <&apbdma 16>;
 431                 dma-names = "rx", "tx";
 432                 status = "disabled";
 433         };
 434
 435         spi@7000d800 {
 436                 compatible = "nvidia,tegra114-spi";
 437                 reg = <0x7000d800 0x200>;
 438                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 439                 #address-cells = <1>;
 440                 #size-cells = <0>;
 441                 clocks = <&tegra_car TEGRA114_CLK_SBC3>;
 442                 clock-names = "spi";
 443                 resets = <&tegra_car 46>;
 444                 reset-names = "spi";
 445                 dmas = <&apbdma 17>, <&apbdma 17>;
 446                 dma-names = "rx", "tx";
 447                 status = "disabled";
 448         };
 449
 450         spi@7000da00 {
 451                 compatible = "nvidia,tegra114-spi";
 452                 reg = <0x7000da00 0x200>;
 453                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 454                 #address-cells = <1>;
 455                 #size-cells = <0>;
 456                 clocks = <&tegra_car TEGRA114_CLK_SBC4>;
 457                 clock-names = "spi";
 458                 resets = <&tegra_car 68>;
 459                 reset-names = "spi";
 460                 dmas = <&apbdma 18>, <&apbdma 18>;
 461                 dma-names = "rx", "tx";
 462                 status = "disabled";
 463         };
 464
 465         spi@7000dc00 {
 466                 compatible = "nvidia,tegra114-spi";
 467                 reg = <0x7000dc00 0x200>;
 468                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 469                 #address-cells = <1>;
 470                 #size-cells = <0>;
 471                 clocks = <&tegra_car TEGRA114_CLK_SBC5>;
 472                 clock-names = "spi";
 473                 resets = <&tegra_car 104>;
 474                 reset-names = "spi";
 475                 dmas = <&apbdma 27>, <&apbdma 27>;
 476                 dma-names = "rx", "tx";
 477                 status = "disabled";
 478         };
 479
 480         spi@7000de00 {
 481                 compatible = "nvidia,tegra114-spi";
 482                 reg = <0x7000de00 0x200>;
 483                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 484                 #address-cells = <1>;
 485                 #size-cells = <0>;
 486                 clocks = <&tegra_car TEGRA114_CLK_SBC6>;
 487                 clock-names = "spi";
 488                 resets = <&tegra_car 105>;
 489                 reset-names = "spi";
 490                 dmas = <&apbdma 28>, <&apbdma 28>;
 491                 dma-names = "rx", "tx";
 492                 status = "disabled";
 493         };
 494
 495         rtc@7000e000 {
 496                 compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
 497                 reg = <0x7000e000 0x100>;
 498                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 499                 clocks = <&tegra_car TEGRA114_CLK_RTC>;
 500         };
 501
 502         kbc@7000e200 {
 503                 compatible = "nvidia,tegra114-kbc";
 504                 reg = <0x7000e200 0x100>;
 505                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 506                 clocks = <&tegra_car TEGRA114_CLK_KBC>;
 507                 resets = <&tegra_car 36>;
 508                 reset-names = "kbc";
 509                 status = "disabled";
 510         };
 511
 512         pmc@7000e400 {
 513                 compatible = "nvidia,tegra114-pmc";
 514                 reg = <0x7000e400 0x400>;
 515                 clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>;
 516                 clock-names = "pclk", "clk32k_in";
 517         };
 518
 519         fuse@7000f800 {
 520                 compatible = "nvidia,tegra114-efuse";
 521                 reg = <0x7000f800 0x400>;
 522                 clocks = <&tegra_car TEGRA114_CLK_FUSE>;
 523                 clock-names = "fuse";
 524                 resets = <&tegra_car 39>;
 525                 reset-names = "fuse";
 526         };
 527
 528         mc: memory-controller@70019000 {
 529                 compatible = "nvidia,tegra114-mc";
 530                 reg = <0x70019000 0x1000>;
 531                 clocks = <&tegra_car TEGRA114_CLK_MC>;
 532                 clock-names = "mc";
 533
 534                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 535
 536                 #iommu-cells = <1>;
 537         };
 538
 539         ahub@70080000 {
 540                 compatible = "nvidia,tegra114-ahub";
 541                 reg = <0x70080000 0x200>,
 542                       <0x70080200 0x100>,
 543                       <0x70081000 0x200>;
 544                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 545                 clocks = <&tegra_car TEGRA114_CLK_D_AUDIO>,
 546                          <&tegra_car TEGRA114_CLK_APBIF>;
 547                 clock-names = "d_audio", "apbif";
 548                 resets = <&tegra_car 106>, /* d_audio */
 549                          <&tegra_car 107>, /* apbif */
 550                          <&tegra_car 30>,  /* i2s0 */
 551                          <&tegra_car 11>,  /* i2s1 */
 552                          <&tegra_car 18>,  /* i2s2 */
 553                          <&tegra_car 101>, /* i2s3 */
 554                          <&tegra_car 102>, /* i2s4 */
 555                          <&tegra_car 108>, /* dam0 */
 556                          <&tegra_car 109>, /* dam1 */
 557                          <&tegra_car 110>, /* dam2 */
 558                          <&tegra_car 10>,  /* spdif */
 559                          <&tegra_car 153>, /* amx */
 560                          <&tegra_car 154>; /* adx */
 561                 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
 562                               "i2s3", "i2s4", "dam0", "dam1", "dam2",
 563                               "spdif", "amx", "adx";
 564                 dmas = <&apbdma 1>, <&apbdma 1>,
 565                        <&apbdma 2>, <&apbdma 2>,
 566                        <&apbdma 3>, <&apbdma 3>,
 567                        <&apbdma 4>, <&apbdma 4>,
 568                        <&apbdma 6>, <&apbdma 6>,
 569                        <&apbdma 7>, <&apbdma 7>,
 570                        <&apbdma 12>, <&apbdma 12>,
 571                        <&apbdma 13>, <&apbdma 13>,
 572                        <&apbdma 14>, <&apbdma 14>,
 573                        <&apbdma 29>, <&apbdma 29>;
 574                 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
 575                             "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
 576                             "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
 577                             "rx9", "tx9";
 578                 ranges;
 579                 #address-cells = <1>;
 580                 #size-cells = <1>;
 581
 582                 tegra_i2s0: i2s@70080300 {
 583                         compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
 584                         reg = <0x70080300 0x100>;
 585                         nvidia,ahub-cif-ids = <4 4>;
 586                         clocks = <&tegra_car TEGRA114_CLK_I2S0>;
 587                         resets = <&tegra_car 30>;
 588                         reset-names = "i2s";
 589                         status = "disabled";
 590                 };
 591
 592                 tegra_i2s1: i2s@70080400 {
 593                         compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
 594                         reg = <0x70080400 0x100>;
 595                         nvidia,ahub-cif-ids = <5 5>;
 596                         clocks = <&tegra_car TEGRA114_CLK_I2S1>;
 597                         resets = <&tegra_car 11>;
 598                         reset-names = "i2s";
 599                         status = "disabled";
 600                 };
 601
 602                 tegra_i2s2: i2s@70080500 {
 603                         compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
 604                         reg = <0x70080500 0x100>;
 605                         nvidia,ahub-cif-ids = <6 6>;
 606                         clocks = <&tegra_car TEGRA114_CLK_I2S2>;
 607                         resets = <&tegra_car 18>;
 608                         reset-names = "i2s";
 609                         status = "disabled";
 610                 };
 611
 612                 tegra_i2s3: i2s@70080600 {
 613                         compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
 614                         reg = <0x70080600 0x100>;
 615                         nvidia,ahub-cif-ids = <7 7>;
 616                         clocks = <&tegra_car TEGRA114_CLK_I2S3>;
 617                         resets = <&tegra_car 101>;
 618                         reset-names = "i2s";
 619                         status = "disabled";
 620                 };
 621
 622                 tegra_i2s4: i2s@70080700 {
 623                         compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
 624                         reg = <0x70080700 0x100>;
 625                         nvidia,ahub-cif-ids = <8 8>;
 626                         clocks = <&tegra_car TEGRA114_CLK_I2S4>;
 627                         resets = <&tegra_car 102>;
 628                         reset-names = "i2s";
 629                         status = "disabled";
 630                 };
 631         };
 632
 633         mipi: mipi@700e3000 {
 634                 compatible = "nvidia,tegra114-mipi";
 635                 reg = <0x700e3000 0x100>;
 636                 clocks = <&tegra_car TEGRA114_CLK_MIPI_CAL>;
 637                 #nvidia,mipi-calibrate-cells = <1>;
 638         };
 639
 640         sdhci@78000000 {
 641                 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
 642                 reg = <0x78000000 0x200>;
 643                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 644                 clocks = <&tegra_car TEGRA114_CLK_SDMMC1>;
 645                 resets = <&tegra_car 14>;
 646                 reset-names = "sdhci";
 647                 status = "disabled";
 648         };
 649
 650         sdhci@78000200 {
 651                 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
 652                 reg = <0x78000200 0x200>;
 653                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 654                 clocks = <&tegra_car TEGRA114_CLK_SDMMC2>;
 655                 resets = <&tegra_car 9>;
 656                 reset-names = "sdhci";
 657                 status = "disabled";
 658         };
 659
 660         sdhci@78000400 {
 661                 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
 662                 reg = <0x78000400 0x200>;
 663                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 664                 clocks = <&tegra_car TEGRA114_CLK_SDMMC3>;
 665                 resets = <&tegra_car 69>;
 666                 reset-names = "sdhci";
 667                 status = "disabled";
 668         };
 669
 670         sdhci@78000600 {
 671                 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
 672                 reg = <0x78000600 0x200>;
 673                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 674                 clocks = <&tegra_car TEGRA114_CLK_SDMMC4>;
 675                 resets = <&tegra_car 15>;
 676                 reset-names = "sdhci";
 677                 status = "disabled";
 678         };
 679
 680         usb@7d000000 {
 681                 compatible = "nvidia,tegra114-ehci", "nvidia,tegra30-ehci", "usb-ehci";
 682                 reg = <0x7d000000 0x4000>;
 683                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 684                 phy_type = "utmi";
 685                 clocks = <&tegra_car TEGRA114_CLK_USBD>;
 686                 resets = <&tegra_car 22>;
 687                 reset-names = "usb";
 688                 nvidia,phy = <&phy1>;
 689                 status = "disabled";
 690         };
 691
 692         phy1: usb-phy@7d000000 {
 693                 compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy";
 694                 reg = <0x7d000000 0x4000 0x7d000000 0x4000>;
 695                 phy_type = "utmi";
 696                 clocks = <&tegra_car TEGRA114_CLK_USBD>,
 697                          <&tegra_car TEGRA114_CLK_PLL_U>,
 698                          <&tegra_car TEGRA114_CLK_USBD>;
 699                 clock-names = "reg", "pll_u", "utmi-pads";
 700                 resets = <&tegra_car 22>, <&tegra_car 22>;
 701                 reset-names = "usb", "utmi-pads";
 702                 nvidia,hssync-start-delay = <0>;
 703                 nvidia,idle-wait-delay = <17>;
 704                 nvidia,elastic-limit = <16>;
 705                 nvidia,term-range-adj = <6>;
 706                 nvidia,xcvr-setup = <9>;
 707                 nvidia,xcvr-lsfslew = <0>;
 708                 nvidia,xcvr-lsrslew = <3>;
 709                 nvidia,hssquelch-level = <2>;
 710                 nvidia,hsdiscon-level = <5>;
 711                 nvidia,xcvr-hsslew = <12>;
 712                 nvidia,has-utmi-pad-registers;
 713                 status = "disabled";
 714         };
 715
 716         usb@7d008000 {
 717                 compatible = "nvidia,tegra114-ehci", "nvidia,tegra30-ehci", "usb-ehci";
 718                 reg = <0x7d008000 0x4000>;
 719                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 720                 phy_type = "utmi";
 721                 clocks = <&tegra_car TEGRA114_CLK_USB3>;
 722                 resets = <&tegra_car 59>;
 723                 reset-names = "usb";
 724                 nvidia,phy = <&phy3>;
 725                 status = "disabled";
 726         };
 727
 728         phy3: usb-phy@7d008000 {
 729                 compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy";
 730                 reg = <0x7d008000 0x4000 0x7d000000 0x4000>;
 731                 phy_type = "utmi";
 732                 clocks = <&tegra_car TEGRA114_CLK_USB3>,
 733                          <&tegra_car TEGRA114_CLK_PLL_U>,
 734                          <&tegra_car TEGRA114_CLK_USBD>;
 735                 clock-names = "reg", "pll_u", "utmi-pads";
 736                 resets = <&tegra_car 59>, <&tegra_car 22>;
 737                 reset-names = "usb", "utmi-pads";
 738                 nvidia,hssync-start-delay = <0>;
 739                 nvidia,idle-wait-delay = <17>;
 740                 nvidia,elastic-limit = <16>;
 741                 nvidia,term-range-adj = <6>;
 742                 nvidia,xcvr-setup = <9>;
 743                 nvidia,xcvr-lsfslew = <0>;
 744                 nvidia,xcvr-lsrslew = <3>;
 745                 nvidia,hssquelch-level = <2>;
 746                 nvidia,hsdiscon-level = <5>;
 747                 nvidia,xcvr-hsslew = <12>;
 748                 status = "disabled";
 749         };
 750
 751         cpus {
 752                 #address-cells = <1>;
 753                 #size-cells = <0>;
 754
 755                 cpu@0 {
 756                         device_type = "cpu";
 757                         compatible = "arm,cortex-a15";
 758                         reg = <0>;
 759                 };
 760
 761                 cpu@1 {
 762                         device_type = "cpu";
 763                         compatible = "arm,cortex-a15";
 764                         reg = <1>;
 765                 };
 766
 767                 cpu@2 {
 768                         device_type = "cpu";
 769                         compatible = "arm,cortex-a15";
 770                         reg = <2>;
 771                 };
 772
 773                 cpu@3 {
 774                         device_type = "cpu";
 775                         compatible = "arm,cortex-a15";
 776                         reg = <3>;
 777                 };
 778         };
 779
 780         timer {
 781                 compatible = "arm,armv7-timer";
 782                 interrupts =
 783                         <GIC_PPI 13
 784                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 785                         <GIC_PPI 14
 786                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 787                         <GIC_PPI 11
 788                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 789                         <GIC_PPI 10
 790                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 791                 interrupt-parent = <&gic>;
 792         };
 793 };