sys/gnu/dts/arm/tegra20.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include <dt-bindings/clock/tegra20-car.h>
   3 #include <dt-bindings/gpio/tegra-gpio.h>
   4 #include <dt-bindings/memory/tegra20-mc.h>
   5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/soc/tegra-pmc.h>
   8
   9 / {
  10         compatible = "nvidia,tegra20";
  11         interrupt-parent = <&lic>;
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14
  15         memory@0 {
  16                 device_type = "memory";
  17                 reg = <0 0>;
  18         };
  19
  20         iram@40000000 {
  21                 compatible = "mmio-sram";
  22                 reg = <0x40000000 0x40000>;
  23                 #address-cells = <1>;
  24                 #size-cells = <1>;
  25                 ranges = <0 0x40000000 0x40000>;
  26
  27                 vde_pool: vde@400 {
  28                         reg = <0x400 0x3fc00>;
  29                         pool;
  30                 };
  31         };
  32
  33         host1x@50000000 {
  34                 compatible = "nvidia,tegra20-host1x", "simple-bus";
  35                 reg = <0x50000000 0x00024000>;
  36                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
  37                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
  38                 clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
  39                 resets = <&tegra_car 28>;
  40                 reset-names = "host1x";
  41
  42                 #address-cells = <1>;
  43                 #size-cells = <1>;
  44
  45                 ranges = <0x54000000 0x54000000 0x04000000>;
  46
  47                 mpe@54040000 {
  48                         compatible = "nvidia,tegra20-mpe";
  49                         reg = <0x54040000 0x00040000>;
  50                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
  51                         clocks = <&tegra_car TEGRA20_CLK_MPE>;
  52                         resets = <&tegra_car 60>;
  53                         reset-names = "mpe";
  54                 };
  55
  56                 vi@54080000 {
  57                         compatible = "nvidia,tegra20-vi";
  58                         reg = <0x54080000 0x00040000>;
  59                         interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
  60                         clocks = <&tegra_car TEGRA20_CLK_VI>;
  61                         resets = <&tegra_car 20>;
  62                         reset-names = "vi";
  63                 };
  64
  65                 epp@540c0000 {
  66                         compatible = "nvidia,tegra20-epp";
  67                         reg = <0x540c0000 0x00040000>;
  68                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
  69                         clocks = <&tegra_car TEGRA20_CLK_EPP>;
  70                         resets = <&tegra_car 19>;
  71                         reset-names = "epp";
  72                 };
  73
  74                 isp@54100000 {
  75                         compatible = "nvidia,tegra20-isp";
  76                         reg = <0x54100000 0x00040000>;
  77                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
  78                         clocks = <&tegra_car TEGRA20_CLK_ISP>;
  79                         resets = <&tegra_car 23>;
  80                         reset-names = "isp";
  81                 };
  82
  83                 gr2d@54140000 {
  84                         compatible = "nvidia,tegra20-gr2d";
  85                         reg = <0x54140000 0x00040000>;
  86                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
  87                         clocks = <&tegra_car TEGRA20_CLK_GR2D>;
  88                         resets = <&tegra_car 21>;
  89                         reset-names = "2d";
  90                 };
  91
  92                 gr3d@54180000 {
  93                         compatible = "nvidia,tegra20-gr3d";
  94                         reg = <0x54180000 0x00040000>;
  95                         clocks = <&tegra_car TEGRA20_CLK_GR3D>;
  96                         resets = <&tegra_car 24>;
  97                         reset-names = "3d";
  98                 };
  99
 100                 dc@54200000 {
 101                         compatible = "nvidia,tegra20-dc";
 102                         reg = <0x54200000 0x00040000>;
 103                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 104                         clocks = <&tegra_car TEGRA20_CLK_DISP1>,
 105                                  <&tegra_car TEGRA20_CLK_PLL_P>;
 106                         clock-names = "dc", "parent";
 107                         resets = <&tegra_car 27>;
 108                         reset-names = "dc";
 109
 110                         nvidia,head = <0>;
 111
 112                         rgb {
 113                                 status = "disabled";
 114                         };
 115                 };
 116
 117                 dc@54240000 {
 118                         compatible = "nvidia,tegra20-dc";
 119                         reg = <0x54240000 0x00040000>;
 120                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 121                         clocks = <&tegra_car TEGRA20_CLK_DISP2>,
 122                                  <&tegra_car TEGRA20_CLK_PLL_P>;
 123                         clock-names = "dc", "parent";
 124                         resets = <&tegra_car 26>;
 125                         reset-names = "dc";
 126
 127                         nvidia,head = <1>;
 128
 129                         rgb {
 130                                 status = "disabled";
 131                         };
 132                 };
 133
 134                 hdmi@54280000 {
 135                         compatible = "nvidia,tegra20-hdmi";
 136                         reg = <0x54280000 0x00040000>;
 137                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 138                         clocks = <&tegra_car TEGRA20_CLK_HDMI>,
 139                                  <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
 140                         clock-names = "hdmi", "parent";
 141                         resets = <&tegra_car 51>;
 142                         reset-names = "hdmi";
 143                         status = "disabled";
 144                 };
 145
 146                 tvo@542c0000 {
 147                         compatible = "nvidia,tegra20-tvo";
 148                         reg = <0x542c0000 0x00040000>;
 149                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 150                         clocks = <&tegra_car TEGRA20_CLK_TVO>;
 151                         status = "disabled";
 152                 };
 153
 154                 dsi@54300000 {
 155                         compatible = "nvidia,tegra20-dsi";
 156                         reg = <0x54300000 0x00040000>;
 157                         clocks = <&tegra_car TEGRA20_CLK_DSI>;
 158                         resets = <&tegra_car 48>;
 159                         reset-names = "dsi";
 160                         status = "disabled";
 161                 };
 162         };
 163
 164         timer@50040600 {
 165                 compatible = "arm,cortex-a9-twd-timer";
 166                 interrupt-parent = <&intc>;
 167                 reg = <0x50040600 0x20>;
 168                 interrupts = <GIC_PPI 13
 169                         (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
 170                 clocks = <&tegra_car TEGRA20_CLK_TWD>;
 171         };
 172
 173         intc: interrupt-controller@50041000 {
 174                 compatible = "arm,cortex-a9-gic";
 175                 reg = <0x50041000 0x1000
 176                        0x50040100 0x0100>;
 177                 interrupt-controller;
 178                 #interrupt-cells = <3>;
 179                 interrupt-parent = <&intc>;
 180         };
 181
 182         cache-controller@50043000 {
 183                 compatible = "arm,pl310-cache";
 184                 reg = <0x50043000 0x1000>;
 185                 arm,data-latency = <5 5 2>;
 186                 arm,tag-latency = <4 4 2>;
 187                 cache-unified;
 188                 cache-level = <2>;
 189         };
 190
 191         lic: interrupt-controller@60004000 {
 192                 compatible = "nvidia,tegra20-ictlr";
 193                 reg = <0x60004000 0x100>,
 194                       <0x60004100 0x50>,
 195                       <0x60004200 0x50>,
 196                       <0x60004300 0x50>;
 197                 interrupt-controller;
 198                 #interrupt-cells = <3>;
 199                 interrupt-parent = <&intc>;
 200         };
 201
 202         timer@60005000 {
 203                 compatible = "nvidia,tegra20-timer";
 204                 reg = <0x60005000 0x60>;
 205                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 206                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 207                              <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 208                              <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 209                 clocks = <&tegra_car TEGRA20_CLK_TIMER>;
 210         };
 211
 212         tegra_car: clock@60006000 {
 213                 compatible = "nvidia,tegra20-car";
 214                 reg = <0x60006000 0x1000>;
 215                 #clock-cells = <1>;
 216                 #reset-cells = <1>;
 217         };
 218
 219         flow-controller@60007000 {
 220                 compatible = "nvidia,tegra20-flowctrl";
 221                 reg = <0x60007000 0x1000>;
 222         };
 223
 224         apbdma: dma@6000a000 {
 225                 compatible = "nvidia,tegra20-apbdma";
 226                 reg = <0x6000a000 0x1200>;
 227                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 228                              <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 229                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 230                              <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 231                              <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
 232                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 233                              <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 234                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 235                              <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 236                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 237                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 238                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 239                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 240                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 241                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 242                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 243                 clocks = <&tegra_car TEGRA20_CLK_APBDMA>;
 244                 resets = <&tegra_car 34>;
 245                 reset-names = "dma";
 246                 #dma-cells = <1>;
 247         };
 248
 249         ahb@6000c000 {
 250                 compatible = "nvidia,tegra20-ahb";
 251                 reg = <0x6000c000 0x110>; /* AHB Arbitration + Gizmo Controller */
 252         };
 253
 254         gpio: gpio@6000d000 {
 255                 compatible = "nvidia,tegra20-gpio";
 256                 reg = <0x6000d000 0x1000>;
 257                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
 258                              <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 259                              <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
 260                              <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
 261                              <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 262                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 263                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 264                 #gpio-cells = <2>;
 265                 gpio-controller;
 266                 #interrupt-cells = <2>;
 267                 interrupt-controller;
 268                 /*
 269                 gpio-ranges = <&pinmux 0 0 224>;
 270                 */
 271         };
 272
 273         vde@6001a000 {
 274                 compatible = "nvidia,tegra20-vde";
 275                 reg = <0x6001a000 0x1000   /* Syntax Engine */
 276                        0x6001b000 0x1000   /* Video Bitstream Engine */
 277                        0x6001c000  0x100   /* Macroblock Engine */
 278                        0x6001c200  0x100   /* Post-processing Engine */
 279                        0x6001c400  0x100   /* Motion Compensation Engine */
 280                        0x6001c600  0x100   /* Transform Engine */
 281                        0x6001c800  0x100   /* Pixel prediction block */
 282                        0x6001ca00  0x100   /* Video DMA */
 283                        0x6001d800  0x300>; /* Video frame controls */
 284                 reg-names = "sxe", "bsev", "mbe", "ppe", "mce",
 285                             "tfe", "ppb", "vdma", "frameid";
 286                 iram = <&vde_pool>; /* IRAM region */
 287                 interrupts = <GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token interrupt */
 288                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */
 289                              <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */
 290                 interrupt-names = "sync-token", "bsev", "sxe";
 291                 clocks = <&tegra_car TEGRA20_CLK_VDE>;
 292                 reset-names = "vde", "mc";
 293                 resets = <&tegra_car 61>, <&mc TEGRA20_MC_RESET_VDE>;
 294         };
 295
 296         apbmisc@70000800 {
 297                 compatible = "nvidia,tegra20-apbmisc";
 298                 reg = <0x70000800 0x64   /* Chip revision */
 299                        0x70000008 0x04>; /* Strapping options */
 300         };
 301
 302         pinmux: pinmux@70000014 {
 303                 compatible = "nvidia,tegra20-pinmux";
 304                 reg = <0x70000014 0x10   /* Tri-state registers */
 305                        0x70000080 0x20   /* Mux registers */
 306                        0x700000a0 0x14   /* Pull-up/down registers */
 307                        0x70000868 0xa8>; /* Pad control registers */
 308         };
 309
 310         das@70000c00 {
 311                 compatible = "nvidia,tegra20-das";
 312                 reg = <0x70000c00 0x80>;
 313         };
 314
 315         tegra_ac97: ac97@70002000 {
 316                 compatible = "nvidia,tegra20-ac97";
 317                 reg = <0x70002000 0x200>;
 318                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 319                 clocks = <&tegra_car TEGRA20_CLK_AC97>;
 320                 resets = <&tegra_car 3>;
 321                 reset-names = "ac97";
 322                 dmas = <&apbdma 12>, <&apbdma 12>;
 323                 dma-names = "rx", "tx";
 324                 status = "disabled";
 325         };
 326
 327         tegra_i2s1: i2s@70002800 {
 328                 compatible = "nvidia,tegra20-i2s";
 329                 reg = <0x70002800 0x200>;
 330                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 331                 clocks = <&tegra_car TEGRA20_CLK_I2S1>;
 332                 resets = <&tegra_car 11>;
 333                 reset-names = "i2s";
 334                 dmas = <&apbdma 2>, <&apbdma 2>;
 335                 dma-names = "rx", "tx";
 336                 status = "disabled";
 337         };
 338
 339         tegra_i2s2: i2s@70002a00 {
 340                 compatible = "nvidia,tegra20-i2s";
 341                 reg = <0x70002a00 0x200>;
 342                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 343                 clocks = <&tegra_car TEGRA20_CLK_I2S2>;
 344                 resets = <&tegra_car 18>;
 345                 reset-names = "i2s";
 346                 dmas = <&apbdma 1>, <&apbdma 1>;
 347                 dma-names = "rx", "tx";
 348                 status = "disabled";
 349         };
 350
 351         /*
 352          * There are two serial driver i.e. 8250 based simple serial
 353          * driver and APB DMA based serial driver for higher baudrate
 354          * and performace. To enable the 8250 based driver, the compatible
 355          * is "nvidia,tegra20-uart" and to enable the APB DMA based serial
 356          * driver, the compatible is "nvidia,tegra20-hsuart".
 357          */
 358         uarta: serial@70006000 {
 359                 compatible = "nvidia,tegra20-uart";
 360                 reg = <0x70006000 0x40>;
 361                 reg-shift = <2>;
 362                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 363                 clocks = <&tegra_car TEGRA20_CLK_UARTA>;
 364                 resets = <&tegra_car 6>;
 365                 reset-names = "serial";
 366                 dmas = <&apbdma 8>, <&apbdma 8>;
 367                 dma-names = "rx", "tx";
 368                 status = "disabled";
 369         };
 370
 371         uartb: serial@70006040 {
 372                 compatible = "nvidia,tegra20-uart";
 373                 reg = <0x70006040 0x40>;
 374                 reg-shift = <2>;
 375                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 376                 clocks = <&tegra_car TEGRA20_CLK_UARTB>;
 377                 resets = <&tegra_car 7>;
 378                 reset-names = "serial";
 379                 dmas = <&apbdma 9>, <&apbdma 9>;
 380                 dma-names = "rx", "tx";
 381                 status = "disabled";
 382         };
 383
 384         uartc: serial@70006200 {
 385                 compatible = "nvidia,tegra20-uart";
 386                 reg = <0x70006200 0x100>;
 387                 reg-shift = <2>;
 388                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 389                 clocks = <&tegra_car TEGRA20_CLK_UARTC>;
 390                 resets = <&tegra_car 55>;
 391                 reset-names = "serial";
 392                 dmas = <&apbdma 10>, <&apbdma 10>;
 393                 dma-names = "rx", "tx";
 394                 status = "disabled";
 395         };
 396
 397         uartd: serial@70006300 {
 398                 compatible = "nvidia,tegra20-uart";
 399                 reg = <0x70006300 0x100>;
 400                 reg-shift = <2>;
 401                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 402                 clocks = <&tegra_car TEGRA20_CLK_UARTD>;
 403                 resets = <&tegra_car 65>;
 404                 reset-names = "serial";
 405                 dmas = <&apbdma 19>, <&apbdma 19>;
 406                 dma-names = "rx", "tx";
 407                 status = "disabled";
 408         };
 409
 410         uarte: serial@70006400 {
 411                 compatible = "nvidia,tegra20-uart";
 412                 reg = <0x70006400 0x100>;
 413                 reg-shift = <2>;
 414                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 415                 clocks = <&tegra_car TEGRA20_CLK_UARTE>;
 416                 resets = <&tegra_car 66>;
 417                 reset-names = "serial";
 418                 dmas = <&apbdma 20>, <&apbdma 20>;
 419                 dma-names = "rx", "tx";
 420                 status = "disabled";
 421         };
 422
 423         nand-controller@70008000 {
 424                 compatible = "nvidia,tegra20-nand";
 425                 reg = <0x70008000 0x100>;
 426                 #address-cells = <1>;
 427                 #size-cells = <0>;
 428                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 429                 clocks = <&tegra_car TEGRA20_CLK_NDFLASH>;
 430                 clock-names = "nand";
 431                 resets = <&tegra_car 13>;
 432                 reset-names = "nand";
 433                 assigned-clocks = <&tegra_car TEGRA20_CLK_NDFLASH>;
 434                 assigned-clock-rates = <150000000>;
 435                 status = "disabled";
 436         };
 437
 438         gmi@70009000 {
 439                 compatible = "nvidia,tegra20-gmi";
 440                 reg = <0x70009000 0x1000>;
 441                 #address-cells = <2>;
 442                 #size-cells = <1>;
 443                 ranges = <0 0 0xd0000000 0xfffffff>;
 444                 clocks = <&tegra_car TEGRA20_CLK_NOR>;
 445                 clock-names = "gmi";
 446                 resets = <&tegra_car 42>;
 447                 reset-names = "gmi";
 448                 status = "disabled";
 449         };
 450
 451         pwm: pwm@7000a000 {
 452                 compatible = "nvidia,tegra20-pwm";
 453                 reg = <0x7000a000 0x100>;
 454                 #pwm-cells = <2>;
 455                 clocks = <&tegra_car TEGRA20_CLK_PWM>;
 456                 resets = <&tegra_car 17>;
 457                 reset-names = "pwm";
 458                 status = "disabled";
 459         };
 460
 461         rtc@7000e000 {
 462                 compatible = "nvidia,tegra20-rtc";
 463                 reg = <0x7000e000 0x100>;
 464                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 465                 clocks = <&tegra_car TEGRA20_CLK_RTC>;
 466         };
 467
 468         i2c@7000c000 {
 469                 compatible = "nvidia,tegra20-i2c";
 470                 reg = <0x7000c000 0x100>;
 471                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 472                 #address-cells = <1>;
 473                 #size-cells = <0>;
 474                 clocks = <&tegra_car TEGRA20_CLK_I2C1>,
 475                          <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
 476                 clock-names = "div-clk", "fast-clk";
 477                 resets = <&tegra_car 12>;
 478                 reset-names = "i2c";
 479                 dmas = <&apbdma 21>, <&apbdma 21>;
 480                 dma-names = "rx", "tx";
 481                 status = "disabled";
 482         };
 483
 484         spi@7000c380 {
 485                 compatible = "nvidia,tegra20-sflash";
 486                 reg = <0x7000c380 0x80>;
 487                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 488                 #address-cells = <1>;
 489                 #size-cells = <0>;
 490                 clocks = <&tegra_car TEGRA20_CLK_SPI>;
 491                 resets = <&tegra_car 43>;
 492                 reset-names = "spi";
 493                 dmas = <&apbdma 11>, <&apbdma 11>;
 494                 dma-names = "rx", "tx";
 495                 status = "disabled";
 496         };
 497
 498         i2c@7000c400 {
 499                 compatible = "nvidia,tegra20-i2c";
 500                 reg = <0x7000c400 0x100>;
 501                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 502                 #address-cells = <1>;
 503                 #size-cells = <0>;
 504                 clocks = <&tegra_car TEGRA20_CLK_I2C2>,
 505                          <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
 506                 clock-names = "div-clk", "fast-clk";
 507                 resets = <&tegra_car 54>;
 508                 reset-names = "i2c";
 509                 dmas = <&apbdma 22>, <&apbdma 22>;
 510                 dma-names = "rx", "tx";
 511                 status = "disabled";
 512         };
 513
 514         i2c@7000c500 {
 515                 compatible = "nvidia,tegra20-i2c";
 516                 reg = <0x7000c500 0x100>;
 517                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 518                 #address-cells = <1>;
 519                 #size-cells = <0>;
 520                 clocks = <&tegra_car TEGRA20_CLK_I2C3>,
 521                          <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
 522                 clock-names = "div-clk", "fast-clk";
 523                 resets = <&tegra_car 67>;
 524                 reset-names = "i2c";
 525                 dmas = <&apbdma 23>, <&apbdma 23>;
 526                 dma-names = "rx", "tx";
 527                 status = "disabled";
 528         };
 529
 530         i2c@7000d000 {
 531                 compatible = "nvidia,tegra20-i2c-dvc";
 532                 reg = <0x7000d000 0x200>;
 533                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 534                 #address-cells = <1>;
 535                 #size-cells = <0>;
 536                 clocks = <&tegra_car TEGRA20_CLK_DVC>,
 537                          <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
 538                 clock-names = "div-clk", "fast-clk";
 539                 resets = <&tegra_car 47>;
 540                 reset-names = "i2c";
 541                 dmas = <&apbdma 24>, <&apbdma 24>;
 542                 dma-names = "rx", "tx";
 543                 status = "disabled";
 544         };
 545
 546         spi@7000d400 {
 547                 compatible = "nvidia,tegra20-slink";
 548                 reg = <0x7000d400 0x200>;
 549                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 550                 #address-cells = <1>;
 551                 #size-cells = <0>;
 552                 clocks = <&tegra_car TEGRA20_CLK_SBC1>;
 553                 resets = <&tegra_car 41>;
 554                 reset-names = "spi";
 555                 dmas = <&apbdma 15>, <&apbdma 15>;
 556                 dma-names = "rx", "tx";
 557                 status = "disabled";
 558         };
 559
 560         spi@7000d600 {
 561                 compatible = "nvidia,tegra20-slink";
 562                 reg = <0x7000d600 0x200>;
 563                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 564                 #address-cells = <1>;
 565                 #size-cells = <0>;
 566                 clocks = <&tegra_car TEGRA20_CLK_SBC2>;
 567                 resets = <&tegra_car 44>;
 568                 reset-names = "spi";
 569                 dmas = <&apbdma 16>, <&apbdma 16>;
 570                 dma-names = "rx", "tx";
 571                 status = "disabled";
 572         };
 573
 574         spi@7000d800 {
 575                 compatible = "nvidia,tegra20-slink";
 576                 reg = <0x7000d800 0x200>;
 577                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 578                 #address-cells = <1>;
 579                 #size-cells = <0>;
 580                 clocks = <&tegra_car TEGRA20_CLK_SBC3>;
 581                 resets = <&tegra_car 46>;
 582                 reset-names = "spi";
 583                 dmas = <&apbdma 17>, <&apbdma 17>;
 584                 dma-names = "rx", "tx";
 585                 status = "disabled";
 586         };
 587
 588         spi@7000da00 {
 589                 compatible = "nvidia,tegra20-slink";
 590                 reg = <0x7000da00 0x200>;
 591                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 592                 #address-cells = <1>;
 593                 #size-cells = <0>;
 594                 clocks = <&tegra_car TEGRA20_CLK_SBC4>;
 595                 resets = <&tegra_car 68>;
 596                 reset-names = "spi";
 597                 dmas = <&apbdma 18>, <&apbdma 18>;
 598                 dma-names = "rx", "tx";
 599                 status = "disabled";
 600         };
 601
 602         kbc@7000e200 {
 603                 compatible = "nvidia,tegra20-kbc";
 604                 reg = <0x7000e200 0x100>;
 605                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 606                 clocks = <&tegra_car TEGRA20_CLK_KBC>;
 607                 resets = <&tegra_car 36>;
 608                 reset-names = "kbc";
 609                 status = "disabled";
 610         };
 611
 612         tegra_pmc: pmc@7000e400 {
 613                 compatible = "nvidia,tegra20-pmc";
 614                 reg = <0x7000e400 0x400>;
 615                 clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>;
 616                 clock-names = "pclk", "clk32k_in";
 617                 #clock-cells = <1>;
 618         };
 619
 620         mc: memory-controller@7000f000 {
 621                 compatible = "nvidia,tegra20-mc-gart";
 622                 reg = <0x7000f000 0x400         /* controller registers */
 623                        0x58000000 0x02000000>;  /* GART aperture */
 624                 clocks = <&tegra_car TEGRA20_CLK_MC>;
 625                 clock-names = "mc";
 626                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 627                 #reset-cells = <1>;
 628                 #iommu-cells = <0>;
 629         };
 630
 631         memory-controller@7000f400 {
 632                 compatible = "nvidia,tegra20-emc";
 633                 reg = <0x7000f400 0x200>;
 634                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 635                 clocks = <&tegra_car TEGRA20_CLK_EMC>;
 636                 #address-cells = <1>;
 637                 #size-cells = <0>;
 638         };
 639
 640         fuse@7000f800 {
 641                 compatible = "nvidia,tegra20-efuse";
 642                 reg = <0x7000f800 0x400>;
 643                 clocks = <&tegra_car TEGRA20_CLK_FUSE>;
 644                 clock-names = "fuse";
 645                 resets = <&tegra_car 39>;
 646                 reset-names = "fuse";
 647         };
 648
 649         pcie@80003000 {
 650                 compatible = "nvidia,tegra20-pcie";
 651                 device_type = "pci";
 652                 reg = <0x80003000 0x00000800   /* PADS registers */
 653                        0x80003800 0x00000200   /* AFI registers */
 654                        0x90000000 0x10000000>; /* configuration space */
 655                 reg-names = "pads", "afi", "cs";
 656                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH   /* controller interrupt */
 657                               GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
 658                 interrupt-names = "intr", "msi";
 659
 660                 #interrupt-cells = <1>;
 661                 interrupt-map-mask = <0 0 0 0>;
 662                 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 663
 664                 bus-range = <0x00 0xff>;
 665                 #address-cells = <3>;
 666                 #size-cells = <2>;
 667
 668                 ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000   /* port 0 registers */
 669                           0x82000000 0 0x80001000 0x80001000 0 0x00001000   /* port 1 registers */
 670                           0x81000000 0 0          0x82000000 0 0x00010000   /* downstream I/O */
 671                           0x82000000 0 0xa0000000 0xa0000000 0 0x08000000   /* non-prefetchable memory */
 672                           0xc2000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */
 673
 674                 clocks = <&tegra_car TEGRA20_CLK_PEX>,
 675                          <&tegra_car TEGRA20_CLK_AFI>,
 676                          <&tegra_car TEGRA20_CLK_PLL_E>;
 677                 clock-names = "pex", "afi", "pll_e";
 678                 resets = <&tegra_car 70>,
 679                          <&tegra_car 72>,
 680                          <&tegra_car 74>;
 681                 reset-names = "pex", "afi", "pcie_x";
 682                 status = "disabled";
 683
 684                 pci@1,0 {
 685                         device_type = "pci";
 686                         assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>;
 687                         reg = <0x000800 0 0 0 0>;
 688                         bus-range = <0x00 0xff>;
 689                         status = "disabled";
 690
 691                         #address-cells = <3>;
 692                         #size-cells = <2>;
 693                         ranges;
 694
 695                         nvidia,num-lanes = <2>;
 696                 };
 697
 698                 pci@2,0 {
 699                         device_type = "pci";
 700                         assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>;
 701                         reg = <0x001000 0 0 0 0>;
 702                         bus-range = <0x00 0xff>;
 703                         status = "disabled";
 704
 705                         #address-cells = <3>;
 706                         #size-cells = <2>;
 707                         ranges;
 708
 709                         nvidia,num-lanes = <2>;
 710                 };
 711         };
 712
 713         usb@c5000000 {
 714                 compatible = "nvidia,tegra20-ehci", "usb-ehci";
 715                 reg = <0xc5000000 0x4000>;
 716                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 717                 phy_type = "utmi";
 718                 nvidia,has-legacy-mode;
 719                 clocks = <&tegra_car TEGRA20_CLK_USBD>;
 720                 resets = <&tegra_car 22>;
 721                 reset-names = "usb";
 722                 nvidia,needs-double-reset;
 723                 nvidia,phy = <&phy1>;
 724                 status = "disabled";
 725         };
 726
 727         phy1: usb-phy@c5000000 {
 728                 compatible = "nvidia,tegra20-usb-phy";
 729                 reg = <0xc5000000 0x4000 0xc5000000 0x4000>;
 730                 phy_type = "utmi";
 731                 clocks = <&tegra_car TEGRA20_CLK_USBD>,
 732                          <&tegra_car TEGRA20_CLK_PLL_U>,
 733                          <&tegra_car TEGRA20_CLK_CLK_M>,
 734                          <&tegra_car TEGRA20_CLK_USBD>;
 735                 clock-names = "reg", "pll_u", "timer", "utmi-pads";
 736                 resets = <&tegra_car 22>, <&tegra_car 22>;
 737                 reset-names = "usb", "utmi-pads";
 738                 nvidia,has-legacy-mode;
 739                 nvidia,hssync-start-delay = <9>;
 740                 nvidia,idle-wait-delay = <17>;
 741                 nvidia,elastic-limit = <16>;
 742                 nvidia,term-range-adj = <6>;
 743                 nvidia,xcvr-setup = <9>;
 744                 nvidia,xcvr-lsfslew = <1>;
 745                 nvidia,xcvr-lsrslew = <1>;
 746                 nvidia,has-utmi-pad-registers;
 747                 status = "disabled";
 748         };
 749
 750         usb@c5004000 {
 751                 compatible = "nvidia,tegra20-ehci", "usb-ehci";
 752                 reg = <0xc5004000 0x4000>;
 753                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 754                 phy_type = "ulpi";
 755                 clocks = <&tegra_car TEGRA20_CLK_USB2>;
 756                 resets = <&tegra_car 58>;
 757                 reset-names = "usb";
 758                 nvidia,phy = <&phy2>;
 759                 status = "disabled";
 760         };
 761
 762         phy2: usb-phy@c5004000 {
 763                 compatible = "nvidia,tegra20-usb-phy";
 764                 reg = <0xc5004000 0x4000>;
 765                 phy_type = "ulpi";
 766                 clocks = <&tegra_car TEGRA20_CLK_USB2>,
 767                          <&tegra_car TEGRA20_CLK_PLL_U>,
 768                          <&tegra_car TEGRA20_CLK_CDEV2>;
 769                 clock-names = "reg", "pll_u", "ulpi-link";
 770                 resets = <&tegra_car 58>, <&tegra_car 22>;
 771                 reset-names = "usb", "utmi-pads";
 772                 status = "disabled";
 773         };
 774
 775         usb@c5008000 {
 776                 compatible = "nvidia,tegra20-ehci", "usb-ehci";
 777                 reg = <0xc5008000 0x4000>;
 778                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 779                 phy_type = "utmi";
 780                 clocks = <&tegra_car TEGRA20_CLK_USB3>;
 781                 resets = <&tegra_car 59>;
 782                 reset-names = "usb";
 783                 nvidia,phy = <&phy3>;
 784                 status = "disabled";
 785         };
 786
 787         phy3: usb-phy@c5008000 {
 788                 compatible = "nvidia,tegra20-usb-phy";
 789                 reg = <0xc5008000 0x4000 0xc5000000 0x4000>;
 790                 phy_type = "utmi";
 791                 clocks = <&tegra_car TEGRA20_CLK_USB3>,
 792                          <&tegra_car TEGRA20_CLK_PLL_U>,
 793                          <&tegra_car TEGRA20_CLK_CLK_M>,
 794                          <&tegra_car TEGRA20_CLK_USBD>;
 795                 clock-names = "reg", "pll_u", "timer", "utmi-pads";
 796                 resets = <&tegra_car 59>, <&tegra_car 22>;
 797                 reset-names = "usb", "utmi-pads";
 798                 nvidia,hssync-start-delay = <9>;
 799                 nvidia,idle-wait-delay = <17>;
 800                 nvidia,elastic-limit = <16>;
 801                 nvidia,term-range-adj = <6>;
 802                 nvidia,xcvr-setup = <9>;
 803                 nvidia,xcvr-lsfslew = <2>;
 804                 nvidia,xcvr-lsrslew = <2>;
 805                 status = "disabled";
 806         };
 807
 808         sdhci@c8000000 {
 809                 compatible = "nvidia,tegra20-sdhci";
 810                 reg = <0xc8000000 0x200>;
 811                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 812                 clocks = <&tegra_car TEGRA20_CLK_SDMMC1>;
 813                 resets = <&tegra_car 14>;
 814                 reset-names = "sdhci";
 815                 status = "disabled";
 816         };
 817
 818         sdhci@c8000200 {
 819                 compatible = "nvidia,tegra20-sdhci";
 820                 reg = <0xc8000200 0x200>;
 821                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 822                 clocks = <&tegra_car TEGRA20_CLK_SDMMC2>;
 823                 resets = <&tegra_car 9>;
 824                 reset-names = "sdhci";
 825                 status = "disabled";
 826         };
 827
 828         sdhci@c8000400 {
 829                 compatible = "nvidia,tegra20-sdhci";
 830                 reg = <0xc8000400 0x200>;
 831                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 832                 clocks = <&tegra_car TEGRA20_CLK_SDMMC3>;
 833                 resets = <&tegra_car 69>;
 834                 reset-names = "sdhci";
 835                 status = "disabled";
 836         };
 837
 838         sdhci@c8000600 {
 839                 compatible = "nvidia,tegra20-sdhci";
 840                 reg = <0xc8000600 0x200>;
 841                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 842                 clocks = <&tegra_car TEGRA20_CLK_SDMMC4>;
 843                 resets = <&tegra_car 15>;
 844                 reset-names = "sdhci";
 845                 status = "disabled";
 846         };
 847
 848         cpus {
 849                 #address-cells = <1>;
 850                 #size-cells = <0>;
 851
 852                 cpu@0 {
 853                         device_type = "cpu";
 854                         compatible = "arm,cortex-a9";
 855                         reg = <0>;
 856                         clocks = <&tegra_car TEGRA20_CLK_CCLK>;
 857                 };
 858
 859                 cpu@1 {
 860                         device_type = "cpu";
 861                         compatible = "arm,cortex-a9";
 862                         reg = <1>;
 863                         clocks = <&tegra_car TEGRA20_CLK_CCLK>;
 864                 };
 865         };
 866
 867         pmu {
 868                 compatible = "arm,cortex-a9-pmu";
 869                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
 870                              <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 871                 interrupt-affinity = <&{/cpus/cpu@0}>,
 872                                      <&{/cpus/cpu@1}>;
 873         };
 874 };