sys/gnu/dts/arm/tegra30.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include <dt-bindings/clock/tegra30-car.h>
   3 #include <dt-bindings/gpio/tegra-gpio.h>
   4 #include <dt-bindings/memory/tegra30-mc.h>
   5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7
   8 / {
   9         compatible = "nvidia,tegra30";
  10         interrupt-parent = <&lic>;
  11         #address-cells = <1>;
  12         #size-cells = <1>;
  13
  14         memory@80000000 {
  15                 device_type = "memory";
  16                 reg = <0x80000000 0x0>;
  17         };
  18
  19         pcie@3000 {
  20                 compatible = "nvidia,tegra30-pcie";
  21                 device_type = "pci";
  22                 reg = <0x00003000 0x00000800   /* PADS registers */
  23                        0x00003800 0x00000200   /* AFI registers */
  24                        0x10000000 0x10000000>; /* configuration space */
  25                 reg-names = "pads", "afi", "cs";
  26                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH   /* controller interrupt */
  27                               GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
  28                 interrupt-names = "intr", "msi";
  29
  30                 #interrupt-cells = <1>;
  31                 interrupt-map-mask = <0 0 0 0>;
  32                 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
  33
  34                 bus-range = <0x00 0xff>;
  35                 #address-cells = <3>;
  36                 #size-cells = <2>;
  37
  38                 ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000   /* port 0 configuration space */
  39                           0x82000000 0 0x00001000 0x00001000 0 0x00001000   /* port 1 configuration space */
  40                           0x82000000 0 0x00004000 0x00004000 0 0x00001000   /* port 2 configuration space */
  41                           0x81000000 0 0          0x02000000 0 0x00010000   /* downstream I/O */
  42                           0x82000000 0 0x20000000 0x20000000 0 0x08000000   /* non-prefetchable memory */
  43                           0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */
  44
  45                 clocks = <&tegra_car TEGRA30_CLK_PCIE>,
  46                          <&tegra_car TEGRA30_CLK_AFI>,
  47                          <&tegra_car TEGRA30_CLK_PLL_E>,
  48                          <&tegra_car TEGRA30_CLK_CML0>;
  49                 clock-names = "pex", "afi", "pll_e", "cml";
  50                 resets = <&tegra_car 70>,
  51                          <&tegra_car 72>,
  52                          <&tegra_car 74>;
  53                 reset-names = "pex", "afi", "pcie_x";
  54                 status = "disabled";
  55
  56                 pci@1,0 {
  57                         device_type = "pci";
  58                         assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;
  59                         reg = <0x000800 0 0 0 0>;
  60                         bus-range = <0x00 0xff>;
  61                         status = "disabled";
  62
  63                         #address-cells = <3>;
  64                         #size-cells = <2>;
  65                         ranges;
  66
  67                         nvidia,num-lanes = <2>;
  68                 };
  69
  70                 pci@2,0 {
  71                         device_type = "pci";
  72                         assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;
  73                         reg = <0x001000 0 0 0 0>;
  74                         bus-range = <0x00 0xff>;
  75                         status = "disabled";
  76
  77                         #address-cells = <3>;
  78                         #size-cells = <2>;
  79                         ranges;
  80
  81                         nvidia,num-lanes = <2>;
  82                 };
  83
  84                 pci@3,0 {
  85                         device_type = "pci";
  86                         assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;
  87                         reg = <0x001800 0 0 0 0>;
  88                         bus-range = <0x00 0xff>;
  89                         status = "disabled";
  90
  91                         #address-cells = <3>;
  92                         #size-cells = <2>;
  93                         ranges;
  94
  95                         nvidia,num-lanes = <2>;
  96                 };
  97         };
  98
  99         iram@40000000 {
 100                 compatible = "mmio-sram";
 101                 reg = <0x40000000 0x40000>;
 102                 #address-cells = <1>;
 103                 #size-cells = <1>;
 104                 ranges = <0 0x40000000 0x40000>;
 105
 106                 vde_pool: vde@400 {
 107                         reg = <0x400 0x3fc00>;
 108                         pool;
 109                 };
 110         };
 111
 112         host1x@50000000 {
 113                 compatible = "nvidia,tegra30-host1x", "simple-bus";
 114                 reg = <0x50000000 0x00024000>;
 115                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
 116                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
 117                 clocks = <&tegra_car TEGRA30_CLK_HOST1X>;
 118                 resets = <&tegra_car 28>;
 119                 reset-names = "host1x";
 120                 iommus = <&mc TEGRA_SWGROUP_HC>;
 121
 122                 #address-cells = <1>;
 123                 #size-cells = <1>;
 124
 125                 ranges = <0x54000000 0x54000000 0x04000000>;
 126
 127                 mpe@54040000 {
 128                         compatible = "nvidia,tegra30-mpe";
 129                         reg = <0x54040000 0x00040000>;
 130                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 131                         clocks = <&tegra_car TEGRA30_CLK_MPE>;
 132                         resets = <&tegra_car 60>;
 133                         reset-names = "mpe";
 134
 135                         iommus = <&mc TEGRA_SWGROUP_MPE>;
 136                 };
 137
 138                 vi@54080000 {
 139                         compatible = "nvidia,tegra30-vi";
 140                         reg = <0x54080000 0x00040000>;
 141                         interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 142                         clocks = <&tegra_car TEGRA30_CLK_VI>;
 143                         resets = <&tegra_car 20>;
 144                         reset-names = "vi";
 145
 146                         iommus = <&mc TEGRA_SWGROUP_VI>;
 147                 };
 148
 149                 epp@540c0000 {
 150                         compatible = "nvidia,tegra30-epp";
 151                         reg = <0x540c0000 0x00040000>;
 152                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 153                         clocks = <&tegra_car TEGRA30_CLK_EPP>;
 154                         resets = <&tegra_car 19>;
 155                         reset-names = "epp";
 156
 157                         iommus = <&mc TEGRA_SWGROUP_EPP>;
 158                 };
 159
 160                 isp@54100000 {
 161                         compatible = "nvidia,tegra30-isp";
 162                         reg = <0x54100000 0x00040000>;
 163                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 164                         clocks = <&tegra_car TEGRA30_CLK_ISP>;
 165                         resets = <&tegra_car 23>;
 166                         reset-names = "isp";
 167
 168                         iommus = <&mc TEGRA_SWGROUP_ISP>;
 169                 };
 170
 171                 gr2d@54140000 {
 172                         compatible = "nvidia,tegra30-gr2d";
 173                         reg = <0x54140000 0x00040000>;
 174                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 175                         clocks = <&tegra_car TEGRA30_CLK_GR2D>;
 176                         resets = <&tegra_car 21>;
 177                         reset-names = "2d";
 178
 179                         iommus = <&mc TEGRA_SWGROUP_G2>;
 180                 };
 181
 182                 gr3d@54180000 {
 183                         compatible = "nvidia,tegra30-gr3d";
 184                         reg = <0x54180000 0x00040000>;
 185                         clocks = <&tegra_car TEGRA30_CLK_GR3D
 186                                   &tegra_car TEGRA30_CLK_GR3D2>;
 187                         clock-names = "3d", "3d2";
 188                         resets = <&tegra_car 24>,
 189                                  <&tegra_car 98>;
 190                         reset-names = "3d", "3d2";
 191
 192                         iommus = <&mc TEGRA_SWGROUP_NV>,
 193                                  <&mc TEGRA_SWGROUP_NV2>;
 194                 };
 195
 196                 dc@54200000 {
 197                         compatible = "nvidia,tegra30-dc", "nvidia,tegra20-dc";
 198                         reg = <0x54200000 0x00040000>;
 199                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 200                         clocks = <&tegra_car TEGRA30_CLK_DISP1>,
 201                                  <&tegra_car TEGRA30_CLK_PLL_P>;
 202                         clock-names = "dc", "parent";
 203                         resets = <&tegra_car 27>;
 204                         reset-names = "dc";
 205
 206                         iommus = <&mc TEGRA_SWGROUP_DC>;
 207
 208                         nvidia,head = <0>;
 209
 210                         rgb {
 211                                 status = "disabled";
 212                         };
 213                 };
 214
 215                 dc@54240000 {
 216                         compatible = "nvidia,tegra30-dc";
 217                         reg = <0x54240000 0x00040000>;
 218                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 219                         clocks = <&tegra_car TEGRA30_CLK_DISP2>,
 220                                  <&tegra_car TEGRA30_CLK_PLL_P>;
 221                         clock-names = "dc", "parent";
 222                         resets = <&tegra_car 26>;
 223                         reset-names = "dc";
 224
 225                         iommus = <&mc TEGRA_SWGROUP_DCB>;
 226
 227                         nvidia,head = <1>;
 228
 229                         rgb {
 230                                 status = "disabled";
 231                         };
 232                 };
 233
 234                 hdmi@54280000 {
 235                         compatible = "nvidia,tegra30-hdmi";
 236                         reg = <0x54280000 0x00040000>;
 237                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 238                         clocks = <&tegra_car TEGRA30_CLK_HDMI>,
 239                                  <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>;
 240                         clock-names = "hdmi", "parent";
 241                         resets = <&tegra_car 51>;
 242                         reset-names = "hdmi";
 243                         status = "disabled";
 244                 };
 245
 246                 tvo@542c0000 {
 247                         compatible = "nvidia,tegra30-tvo";
 248                         reg = <0x542c0000 0x00040000>;
 249                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 250                         clocks = <&tegra_car TEGRA30_CLK_TVO>;
 251                         status = "disabled";
 252                 };
 253
 254                 dsi@54300000 {
 255                         compatible = "nvidia,tegra30-dsi";
 256                         reg = <0x54300000 0x00040000>;
 257                         clocks = <&tegra_car TEGRA30_CLK_DSIA>;
 258                         resets = <&tegra_car 48>;
 259                         reset-names = "dsi";
 260                         status = "disabled";
 261                 };
 262         };
 263
 264         timer@50040600 {
 265                 compatible = "arm,cortex-a9-twd-timer";
 266                 reg = <0x50040600 0x20>;
 267                 interrupt-parent = <&intc>;
 268                 interrupts = <GIC_PPI 13
 269                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
 270                 clocks = <&tegra_car TEGRA30_CLK_TWD>;
 271         };
 272
 273         intc: interrupt-controller@50041000 {
 274                 compatible = "arm,cortex-a9-gic";
 275                 reg = <0x50041000 0x1000
 276                        0x50040100 0x0100>;
 277                 interrupt-controller;
 278                 #interrupt-cells = <3>;
 279                 interrupt-parent = <&intc>;
 280         };
 281
 282         cache-controller@50043000 {
 283                 compatible = "arm,pl310-cache";
 284                 reg = <0x50043000 0x1000>;
 285                 arm,data-latency = <6 6 2>;
 286                 arm,tag-latency = <5 5 2>;
 287                 cache-unified;
 288                 cache-level = <2>;
 289         };
 290
 291         lic: interrupt-controller@60004000 {
 292                 compatible = "nvidia,tegra30-ictlr";
 293                 reg = <0x60004000 0x100>,
 294                       <0x60004100 0x50>,
 295                       <0x60004200 0x50>,
 296                       <0x60004300 0x50>,
 297                       <0x60004400 0x50>;
 298                 interrupt-controller;
 299                 #interrupt-cells = <3>;
 300                 interrupt-parent = <&intc>;
 301         };
 302
 303         timer@60005000 {
 304                 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
 305                 reg = <0x60005000 0x400>;
 306                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 307                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 308                              <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 309                              <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
 310                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 311                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
 312                 clocks = <&tegra_car TEGRA30_CLK_TIMER>;
 313         };
 314
 315         tegra_car: clock@60006000 {
 316                 compatible = "nvidia,tegra30-car";
 317                 reg = <0x60006000 0x1000>;
 318                 #clock-cells = <1>;
 319                 #reset-cells = <1>;
 320         };
 321
 322         flow-controller@60007000 {
 323                 compatible = "nvidia,tegra30-flowctrl";
 324                 reg = <0x60007000 0x1000>;
 325         };
 326
 327         apbdma: dma@6000a000 {
 328                 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
 329                 reg = <0x6000a000 0x1400>;
 330                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 331                              <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 332                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 333                              <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 334                              <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
 335                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 336                              <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 337                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 338                              <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 339                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 340                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 341                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 342                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 343                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 344                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 345                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
 346                              <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
 347                              <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
 348                              <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
 349                              <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
 350                              <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
 351                              <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
 352                              <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 353                              <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 354                              <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
 355                              <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
 356                              <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
 357                              <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
 358                              <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
 359                              <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
 360                              <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 361                              <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 362                 clocks = <&tegra_car TEGRA30_CLK_APBDMA>;
 363                 resets = <&tegra_car 34>;
 364                 reset-names = "dma";
 365                 #dma-cells = <1>;
 366         };
 367
 368         ahb: ahb@6000c000 {
 369                 compatible = "nvidia,tegra30-ahb";
 370                 reg = <0x6000c000 0x150>; /* AHB Arbitration + Gizmo Controller */
 371         };
 372
 373         actmon@6000c800 {
 374                 compatible = "nvidia,tegra30-actmon";
 375                 reg = <0x6000c800 0x400>;
 376                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 377                 clocks = <&tegra_car TEGRA30_CLK_ACTMON>,
 378                          <&tegra_car TEGRA30_CLK_EMC>;
 379                 clock-names = "actmon", "emc";
 380                 resets = <&tegra_car TEGRA30_CLK_ACTMON>;
 381                 reset-names = "actmon";
 382         };
 383
 384         gpio: gpio@6000d000 {
 385                 compatible = "nvidia,tegra30-gpio";
 386                 reg = <0x6000d000 0x1000>;
 387                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
 388                              <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 389                              <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
 390                              <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
 391                              <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 392                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 393                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
 394                              <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 395                 #gpio-cells = <2>;
 396                 gpio-controller;
 397                 #interrupt-cells = <2>;
 398                 interrupt-controller;
 399                 /*
 400                 gpio-ranges = <&pinmux 0 0 248>;
 401                 */
 402         };
 403
 404         vde@6001a000 {
 405                 compatible = "nvidia,tegra30-vde", "nvidia,tegra20-vde";
 406                 reg = <0x6001a000 0x1000   /* Syntax Engine */
 407                        0x6001b000 0x1000   /* Video Bitstream Engine */
 408                        0x6001c000  0x100   /* Macroblock Engine */
 409                        0x6001c200  0x100   /* Post-processing Engine */
 410                        0x6001c400  0x100   /* Motion Compensation Engine */
 411                        0x6001c600  0x100   /* Transform Engine */
 412                        0x6001c800  0x100   /* Pixel prediction block */
 413                        0x6001ca00  0x100   /* Video DMA */
 414                        0x6001d800  0x400>; /* Video frame controls */
 415                 reg-names = "sxe", "bsev", "mbe", "ppe", "mce",
 416                             "tfe", "ppb", "vdma", "frameid";
 417                 iram = <&vde_pool>; /* IRAM region */
 418                 interrupts = <GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token interrupt */
 419                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */
 420                              <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */
 421                 interrupt-names = "sync-token", "bsev", "sxe";
 422                 clocks = <&tegra_car TEGRA30_CLK_VDE>;
 423                 reset-names = "vde", "mc";
 424                 resets = <&tegra_car 61>, <&mc TEGRA30_MC_RESET_VDE>;
 425                 iommus = <&mc TEGRA_SWGROUP_VDE>;
 426         };
 427
 428         apbmisc@70000800 {
 429                 compatible = "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc";
 430                 reg = <0x70000800 0x64   /* Chip revision */
 431                        0x70000008 0x04>; /* Strapping options */
 432         };
 433
 434         pinmux: pinmux@70000868 {
 435                 compatible = "nvidia,tegra30-pinmux";
 436                 reg = <0x70000868 0xd4    /* Pad control registers */
 437                        0x70003000 0x3e4>; /* Mux registers */
 438         };
 439
 440         /*
 441          * There are two serial driver i.e. 8250 based simple serial
 442          * driver and APB DMA based serial driver for higher baudrate
 443          * and performace. To enable the 8250 based driver, the compatible
 444          * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
 445          * the APB DMA based serial driver, the compatible is
 446          * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
 447          */
 448         uarta: serial@70006000 {
 449                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 450                 reg = <0x70006000 0x40>;
 451                 reg-shift = <2>;
 452                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 453                 clocks = <&tegra_car TEGRA30_CLK_UARTA>;
 454                 resets = <&tegra_car 6>;
 455                 reset-names = "serial";
 456                 dmas = <&apbdma 8>, <&apbdma 8>;
 457                 dma-names = "rx", "tx";
 458                 status = "disabled";
 459         };
 460
 461         uartb: serial@70006040 {
 462                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 463                 reg = <0x70006040 0x40>;
 464                 reg-shift = <2>;
 465                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 466                 clocks = <&tegra_car TEGRA30_CLK_UARTB>;
 467                 resets = <&tegra_car 7>;
 468                 reset-names = "serial";
 469                 dmas = <&apbdma 9>, <&apbdma 9>;
 470                 dma-names = "rx", "tx";
 471                 status = "disabled";
 472         };
 473
 474         uartc: serial@70006200 {
 475                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 476                 reg = <0x70006200 0x100>;
 477                 reg-shift = <2>;
 478                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 479                 clocks = <&tegra_car TEGRA30_CLK_UARTC>;
 480                 resets = <&tegra_car 55>;
 481                 reset-names = "serial";
 482                 dmas = <&apbdma 10>, <&apbdma 10>;
 483                 dma-names = "rx", "tx";
 484                 status = "disabled";
 485         };
 486
 487         uartd: serial@70006300 {
 488                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 489                 reg = <0x70006300 0x100>;
 490                 reg-shift = <2>;
 491                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 492                 clocks = <&tegra_car TEGRA30_CLK_UARTD>;
 493                 resets = <&tegra_car 65>;
 494                 reset-names = "serial";
 495                 dmas = <&apbdma 19>, <&apbdma 19>;
 496                 dma-names = "rx", "tx";
 497                 status = "disabled";
 498         };
 499
 500         uarte: serial@70006400 {
 501                 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
 502                 reg = <0x70006400 0x100>;
 503                 reg-shift = <2>;
 504                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 505                 clocks = <&tegra_car TEGRA30_CLK_UARTE>;
 506                 resets = <&tegra_car 66>;
 507                 reset-names = "serial";
 508                 dmas = <&apbdma 20>, <&apbdma 20>;
 509                 dma-names = "rx", "tx";
 510                 status = "disabled";
 511         };
 512
 513         gmi@70009000 {
 514                 compatible = "nvidia,tegra30-gmi";
 515                 reg = <0x70009000 0x1000>;
 516                 #address-cells = <2>;
 517                 #size-cells = <1>;
 518                 ranges = <0 0 0x48000000 0x7ffffff>;
 519                 clocks = <&tegra_car TEGRA30_CLK_NOR>;
 520                 clock-names = "gmi";
 521                 resets = <&tegra_car 42>;
 522                 reset-names = "gmi";
 523                 status = "disabled";
 524         };
 525
 526         pwm: pwm@7000a000 {
 527                 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
 528                 reg = <0x7000a000 0x100>;
 529                 #pwm-cells = <2>;
 530                 clocks = <&tegra_car TEGRA30_CLK_PWM>;
 531                 resets = <&tegra_car 17>;
 532                 reset-names = "pwm";
 533                 status = "disabled";
 534         };
 535
 536         rtc@7000e000 {
 537                 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
 538                 reg = <0x7000e000 0x100>;
 539                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 540                 clocks = <&tegra_car TEGRA30_CLK_RTC>;
 541         };
 542
 543         i2c@7000c000 {
 544                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 545                 reg = <0x7000c000 0x100>;
 546                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 547                 #address-cells = <1>;
 548                 #size-cells = <0>;
 549                 clocks = <&tegra_car TEGRA30_CLK_I2C1>,
 550                          <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 551                 clock-names = "div-clk", "fast-clk";
 552                 resets = <&tegra_car 12>;
 553                 reset-names = "i2c";
 554                 dmas = <&apbdma 21>, <&apbdma 21>;
 555                 dma-names = "rx", "tx";
 556                 status = "disabled";
 557         };
 558
 559         i2c@7000c400 {
 560                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 561                 reg = <0x7000c400 0x100>;
 562                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 563                 #address-cells = <1>;
 564                 #size-cells = <0>;
 565                 clocks = <&tegra_car TEGRA30_CLK_I2C2>,
 566                          <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 567                 clock-names = "div-clk", "fast-clk";
 568                 resets = <&tegra_car 54>;
 569                 reset-names = "i2c";
 570                 dmas = <&apbdma 22>, <&apbdma 22>;
 571                 dma-names = "rx", "tx";
 572                 status = "disabled";
 573         };
 574
 575         i2c@7000c500 {
 576                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 577                 reg = <0x7000c500 0x100>;
 578                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 579                 #address-cells = <1>;
 580                 #size-cells = <0>;
 581                 clocks = <&tegra_car TEGRA30_CLK_I2C3>,
 582                          <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 583                 clock-names = "div-clk", "fast-clk";
 584                 resets = <&tegra_car 67>;
 585                 reset-names = "i2c";
 586                 dmas = <&apbdma 23>, <&apbdma 23>;
 587                 dma-names = "rx", "tx";
 588                 status = "disabled";
 589         };
 590
 591         i2c@7000c700 {
 592                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 593                 reg = <0x7000c700 0x100>;
 594                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 595                 #address-cells = <1>;
 596                 #size-cells = <0>;
 597                 clocks = <&tegra_car TEGRA30_CLK_I2C4>,
 598                          <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 599                 resets = <&tegra_car 103>;
 600                 reset-names = "i2c";
 601                 clock-names = "div-clk", "fast-clk";
 602                 dmas = <&apbdma 26>, <&apbdma 26>;
 603                 dma-names = "rx", "tx";
 604                 status = "disabled";
 605         };
 606
 607         i2c@7000d000 {
 608                 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
 609                 reg = <0x7000d000 0x100>;
 610                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 611                 #address-cells = <1>;
 612                 #size-cells = <0>;
 613                 clocks = <&tegra_car TEGRA30_CLK_I2C5>,
 614                          <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
 615                 clock-names = "div-clk", "fast-clk";
 616                 resets = <&tegra_car 47>;
 617                 reset-names = "i2c";
 618                 dmas = <&apbdma 24>, <&apbdma 24>;
 619                 dma-names = "rx", "tx";
 620                 status = "disabled";
 621         };
 622
 623         spi@7000d400 {
 624                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 625                 reg = <0x7000d400 0x200>;
 626                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 627                 #address-cells = <1>;
 628                 #size-cells = <0>;
 629                 clocks = <&tegra_car TEGRA30_CLK_SBC1>;
 630                 resets = <&tegra_car 41>;
 631                 reset-names = "spi";
 632                 dmas = <&apbdma 15>, <&apbdma 15>;
 633                 dma-names = "rx", "tx";
 634                 status = "disabled";
 635         };
 636
 637         spi@7000d600 {
 638                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 639                 reg = <0x7000d600 0x200>;
 640                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 641                 #address-cells = <1>;
 642                 #size-cells = <0>;
 643                 clocks = <&tegra_car TEGRA30_CLK_SBC2>;
 644                 resets = <&tegra_car 44>;
 645                 reset-names = "spi";
 646                 dmas = <&apbdma 16>, <&apbdma 16>;
 647                 dma-names = "rx", "tx";
 648                 status = "disabled";
 649         };
 650
 651         spi@7000d800 {
 652                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 653                 reg = <0x7000d800 0x200>;
 654                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 655                 #address-cells = <1>;
 656                 #size-cells = <0>;
 657                 clocks = <&tegra_car TEGRA30_CLK_SBC3>;
 658                 resets = <&tegra_car 46>;
 659                 reset-names = "spi";
 660                 dmas = <&apbdma 17>, <&apbdma 17>;
 661                 dma-names = "rx", "tx";
 662                 status = "disabled";
 663         };
 664
 665         spi@7000da00 {
 666                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 667                 reg = <0x7000da00 0x200>;
 668                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 669                 #address-cells = <1>;
 670                 #size-cells = <0>;
 671                 clocks = <&tegra_car TEGRA30_CLK_SBC4>;
 672                 resets = <&tegra_car 68>;
 673                 reset-names = "spi";
 674                 dmas = <&apbdma 18>, <&apbdma 18>;
 675                 dma-names = "rx", "tx";
 676                 status = "disabled";
 677         };
 678
 679         spi@7000dc00 {
 680                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 681                 reg = <0x7000dc00 0x200>;
 682                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 683                 #address-cells = <1>;
 684                 #size-cells = <0>;
 685                 clocks = <&tegra_car TEGRA30_CLK_SBC5>;
 686                 resets = <&tegra_car 104>;
 687                 reset-names = "spi";
 688                 dmas = <&apbdma 27>, <&apbdma 27>;
 689                 dma-names = "rx", "tx";
 690                 status = "disabled";
 691         };
 692
 693         spi@7000de00 {
 694                 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 695                 reg = <0x7000de00 0x200>;
 696                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 697                 #address-cells = <1>;
 698                 #size-cells = <0>;
 699                 clocks = <&tegra_car TEGRA30_CLK_SBC6>;
 700                 resets = <&tegra_car 106>;
 701                 reset-names = "spi";
 702                 dmas = <&apbdma 28>, <&apbdma 28>;
 703                 dma-names = "rx", "tx";
 704                 status = "disabled";
 705         };
 706
 707         kbc@7000e200 {
 708                 compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
 709                 reg = <0x7000e200 0x100>;
 710                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 711                 clocks = <&tegra_car TEGRA30_CLK_KBC>;
 712                 resets = <&tegra_car 36>;
 713                 reset-names = "kbc";
 714                 status = "disabled";
 715         };
 716
 717         pmc@7000e400 {
 718                 compatible = "nvidia,tegra30-pmc";
 719                 reg = <0x7000e400 0x400>;
 720                 clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>;
 721                 clock-names = "pclk", "clk32k_in";
 722         };
 723
 724         mc: memory-controller@7000f000 {
 725                 compatible = "nvidia,tegra30-mc";
 726                 reg = <0x7000f000 0x400>;
 727                 clocks = <&tegra_car TEGRA30_CLK_MC>;
 728                 clock-names = "mc";
 729
 730                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 731
 732                 #iommu-cells = <1>;
 733                 #reset-cells = <1>;
 734         };
 735
 736         memory-controller@7000f400 {
 737                 compatible = "nvidia,tegra30-emc";
 738                 reg = <0x7000f400 0x400>;
 739                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 740                 clocks = <&tegra_car TEGRA30_CLK_EMC>;
 741
 742                 nvidia,memory-controller = <&mc>;
 743         };
 744
 745         fuse@7000f800 {
 746                 compatible = "nvidia,tegra30-efuse";
 747                 reg = <0x7000f800 0x400>;
 748                 clocks = <&tegra_car TEGRA30_CLK_FUSE>;
 749                 clock-names = "fuse";
 750                 resets = <&tegra_car 39>;
 751                 reset-names = "fuse";
 752         };
 753
 754         hda@70030000 {
 755                 compatible = "nvidia,tegra30-hda";
 756                 reg = <0x70030000 0x10000>;
 757                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 758                 clocks = <&tegra_car TEGRA30_CLK_HDA>,
 759                          <&tegra_car TEGRA30_CLK_HDA2HDMI>,
 760                          <&tegra_car TEGRA30_CLK_HDA2CODEC_2X>;
 761                 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
 762                 resets = <&tegra_car 125>, /* hda */
 763                          <&tegra_car 128>, /* hda2hdmi */
 764                          <&tegra_car 111>; /* hda2codec_2x */
 765                 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
 766                 status = "disabled";
 767         };
 768
 769         ahub@70080000 {
 770                 compatible = "nvidia,tegra30-ahub";
 771                 reg = <0x70080000 0x200
 772                        0x70080200 0x100>;
 773                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 774                 clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>,
 775                          <&tegra_car TEGRA30_CLK_APBIF>;
 776                 clock-names = "d_audio", "apbif";
 777                 resets = <&tegra_car 106>, /* d_audio */
 778                          <&tegra_car 107>, /* apbif */
 779                          <&tegra_car 30>,  /* i2s0 */
 780                          <&tegra_car 11>,  /* i2s1 */
 781                          <&tegra_car 18>,  /* i2s2 */
 782                          <&tegra_car 101>, /* i2s3 */
 783                          <&tegra_car 102>, /* i2s4 */
 784                          <&tegra_car 108>, /* dam0 */
 785                          <&tegra_car 109>, /* dam1 */
 786                          <&tegra_car 110>, /* dam2 */
 787                          <&tegra_car 10>;  /* spdif */
 788                 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
 789                               "i2s3", "i2s4", "dam0", "dam1", "dam2",
 790                               "spdif";
 791                 dmas = <&apbdma 1>, <&apbdma 1>,
 792                        <&apbdma 2>, <&apbdma 2>,
 793                        <&apbdma 3>, <&apbdma 3>,
 794                        <&apbdma 4>, <&apbdma 4>;
 795                 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
 796                             "rx3", "tx3";
 797                 ranges;
 798                 #address-cells = <1>;
 799                 #size-cells = <1>;
 800
 801                 tegra_i2s0: i2s@70080300 {
 802                         compatible = "nvidia,tegra30-i2s";
 803                         reg = <0x70080300 0x100>;
 804                         nvidia,ahub-cif-ids = <4 4>;
 805                         clocks = <&tegra_car TEGRA30_CLK_I2S0>;
 806                         resets = <&tegra_car 30>;
 807                         reset-names = "i2s";
 808                         status = "disabled";
 809                 };
 810
 811                 tegra_i2s1: i2s@70080400 {
 812                         compatible = "nvidia,tegra30-i2s";
 813                         reg = <0x70080400 0x100>;
 814                         nvidia,ahub-cif-ids = <5 5>;
 815                         clocks = <&tegra_car TEGRA30_CLK_I2S1>;
 816                         resets = <&tegra_car 11>;
 817                         reset-names = "i2s";
 818                         status = "disabled";
 819                 };
 820
 821                 tegra_i2s2: i2s@70080500 {
 822                         compatible = "nvidia,tegra30-i2s";
 823                         reg = <0x70080500 0x100>;
 824                         nvidia,ahub-cif-ids = <6 6>;
 825                         clocks = <&tegra_car TEGRA30_CLK_I2S2>;
 826                         resets = <&tegra_car 18>;
 827                         reset-names = "i2s";
 828                         status = "disabled";
 829                 };
 830
 831                 tegra_i2s3: i2s@70080600 {
 832                         compatible = "nvidia,tegra30-i2s";
 833                         reg = <0x70080600 0x100>;
 834                         nvidia,ahub-cif-ids = <7 7>;
 835                         clocks = <&tegra_car TEGRA30_CLK_I2S3>;
 836                         resets = <&tegra_car 101>;
 837                         reset-names = "i2s";
 838                         status = "disabled";
 839                 };
 840
 841                 tegra_i2s4: i2s@70080700 {
 842                         compatible = "nvidia,tegra30-i2s";
 843                         reg = <0x70080700 0x100>;
 844                         nvidia,ahub-cif-ids = <8 8>;
 845                         clocks = <&tegra_car TEGRA30_CLK_I2S4>;
 846                         resets = <&tegra_car 102>;
 847                         reset-names = "i2s";
 848                         status = "disabled";
 849                 };
 850         };
 851
 852         sdhci@78000000 {
 853                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 854                 reg = <0x78000000 0x200>;
 855                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 856                 clocks = <&tegra_car TEGRA30_CLK_SDMMC1>;
 857                 resets = <&tegra_car 14>;
 858                 reset-names = "sdhci";
 859                 status = "disabled";
 860         };
 861
 862         sdhci@78000200 {
 863                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 864                 reg = <0x78000200 0x200>;
 865                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 866                 clocks = <&tegra_car TEGRA30_CLK_SDMMC2>;
 867                 resets = <&tegra_car 9>;
 868                 reset-names = "sdhci";
 869                 status = "disabled";
 870         };
 871
 872         sdhci@78000400 {
 873                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 874                 reg = <0x78000400 0x200>;
 875                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 876                 clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
 877                 resets = <&tegra_car 69>;
 878                 reset-names = "sdhci";
 879                 status = "disabled";
 880         };
 881
 882         sdhci@78000600 {
 883                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
 884                 reg = <0x78000600 0x200>;
 885                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 886                 clocks = <&tegra_car TEGRA30_CLK_SDMMC4>;
 887                 resets = <&tegra_car 15>;
 888                 reset-names = "sdhci";
 889                 status = "disabled";
 890         };
 891
 892         usb@7d000000 {
 893                 compatible = "nvidia,tegra30-ehci", "usb-ehci";
 894                 reg = <0x7d000000 0x4000>;
 895                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 896                 phy_type = "utmi";
 897                 clocks = <&tegra_car TEGRA30_CLK_USBD>;
 898                 resets = <&tegra_car 22>;
 899                 reset-names = "usb";
 900                 nvidia,needs-double-reset;
 901                 nvidia,phy = <&phy1>;
 902                 status = "disabled";
 903         };
 904
 905         phy1: usb-phy@7d000000 {
 906                 compatible = "nvidia,tegra30-usb-phy";
 907                 reg = <0x7d000000 0x4000 0x7d000000 0x4000>;
 908                 phy_type = "utmi";
 909                 clocks = <&tegra_car TEGRA30_CLK_USBD>,
 910                          <&tegra_car TEGRA30_CLK_PLL_U>,
 911                          <&tegra_car TEGRA30_CLK_USBD>;
 912                 clock-names = "reg", "pll_u", "utmi-pads";
 913                 resets = <&tegra_car 22>, <&tegra_car 22>;
 914                 reset-names = "usb", "utmi-pads";
 915                 nvidia,hssync-start-delay = <9>;
 916                 nvidia,idle-wait-delay = <17>;
 917                 nvidia,elastic-limit = <16>;
 918                 nvidia,term-range-adj = <6>;
 919                 nvidia,xcvr-setup = <51>;
 920                 nvidia,xcvr-setup-use-fuses;
 921                 nvidia,xcvr-lsfslew = <1>;
 922                 nvidia,xcvr-lsrslew = <1>;
 923                 nvidia,xcvr-hsslew = <32>;
 924                 nvidia,hssquelch-level = <2>;
 925                 nvidia,hsdiscon-level = <5>;
 926                 nvidia,has-utmi-pad-registers;
 927                 status = "disabled";
 928         };
 929
 930         usb@7d004000 {
 931                 compatible = "nvidia,tegra30-ehci", "usb-ehci";
 932                 reg = <0x7d004000 0x4000>;
 933                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 934                 phy_type = "utmi";
 935                 clocks = <&tegra_car TEGRA30_CLK_USB2>;
 936                 resets = <&tegra_car 58>;
 937                 reset-names = "usb";
 938                 nvidia,phy = <&phy2>;
 939                 status = "disabled";
 940         };
 941
 942         phy2: usb-phy@7d004000 {
 943                 compatible = "nvidia,tegra30-usb-phy";
 944                 reg = <0x7d004000 0x4000 0x7d000000 0x4000>;
 945                 phy_type = "utmi";
 946                 clocks = <&tegra_car TEGRA30_CLK_USB2>,
 947                          <&tegra_car TEGRA30_CLK_PLL_U>,
 948                          <&tegra_car TEGRA30_CLK_USBD>;
 949                 clock-names = "reg", "pll_u", "utmi-pads";
 950                 resets = <&tegra_car 58>, <&tegra_car 22>;
 951                 reset-names = "usb", "utmi-pads";
 952                 nvidia,hssync-start-delay = <9>;
 953                 nvidia,idle-wait-delay = <17>;
 954                 nvidia,elastic-limit = <16>;
 955                 nvidia,term-range-adj = <6>;
 956                 nvidia,xcvr-setup = <51>;
 957                 nvidia,xcvr-setup-use-fuses;
 958                 nvidia,xcvr-lsfslew = <2>;
 959                 nvidia,xcvr-lsrslew = <2>;
 960                 nvidia,xcvr-hsslew = <32>;
 961                 nvidia,hssquelch-level = <2>;
 962                 nvidia,hsdiscon-level = <5>;
 963                 status = "disabled";
 964         };
 965
 966         usb@7d008000 {
 967                 compatible = "nvidia,tegra30-ehci", "usb-ehci";
 968                 reg = <0x7d008000 0x4000>;
 969                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 970                 phy_type = "utmi";
 971                 clocks = <&tegra_car TEGRA30_CLK_USB3>;
 972                 resets = <&tegra_car 59>;
 973                 reset-names = "usb";
 974                 nvidia,phy = <&phy3>;
 975                 status = "disabled";
 976         };
 977
 978         phy3: usb-phy@7d008000 {
 979                 compatible = "nvidia,tegra30-usb-phy";
 980                 reg = <0x7d008000 0x4000 0x7d000000 0x4000>;
 981                 phy_type = "utmi";
 982                 clocks = <&tegra_car TEGRA30_CLK_USB3>,
 983                          <&tegra_car TEGRA30_CLK_PLL_U>,
 984                          <&tegra_car TEGRA30_CLK_USBD>;
 985                 clock-names = "reg", "pll_u", "utmi-pads";
 986                 resets = <&tegra_car 59>, <&tegra_car 22>;
 987                 reset-names = "usb", "utmi-pads";
 988                 nvidia,hssync-start-delay = <0>;
 989                 nvidia,idle-wait-delay = <17>;
 990                 nvidia,elastic-limit = <16>;
 991                 nvidia,term-range-adj = <6>;
 992                 nvidia,xcvr-setup = <51>;
 993                 nvidia,xcvr-setup-use-fuses;
 994                 nvidia,xcvr-lsfslew = <2>;
 995                 nvidia,xcvr-lsrslew = <2>;
 996                 nvidia,xcvr-hsslew = <32>;
 997                 nvidia,hssquelch-level = <2>;
 998                 nvidia,hsdiscon-level = <5>;
 999                 status = "disabled";
1000         };
1001
1002         cpus {
1003                 #address-cells = <1>;
1004                 #size-cells = <0>;
1005
1006                 cpu@0 {
1007                         device_type = "cpu";
1008                         compatible = "arm,cortex-a9";
1009                         reg = <0>;
1010                         clocks = <&tegra_car TEGRA30_CLK_CCLK_G>;
1011                 };
1012
1013                 cpu@1 {
1014                         device_type = "cpu";
1015                         compatible = "arm,cortex-a9";
1016                         reg = <1>;
1017                         clocks = <&tegra_car TEGRA30_CLK_CCLK_G>;
1018                 };
1019
1020                 cpu@2 {
1021                         device_type = "cpu";
1022                         compatible = "arm,cortex-a9";
1023                         reg = <2>;
1024                         clocks = <&tegra_car TEGRA30_CLK_CCLK_G>;
1025                 };
1026
1027                 cpu@3 {
1028                         device_type = "cpu";
1029                         compatible = "arm,cortex-a9";
1030                         reg = <3>;
1031                         clocks = <&tegra_car TEGRA30_CLK_CCLK_G>;
1032                 };
1033         };
1034
1035         pmu {
1036                 compatible = "arm,cortex-a9-pmu";
1037                 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
1038                              <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1039                              <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1040                              <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
1041                 interrupt-affinity = <&{/cpus/cpu@0}>,
1042                                      <&{/cpus/cpu@1}>,
1043                                      <&{/cpus/cpu@2}>,
1044                                      <&{/cpus/cpu@3}>;
1045         };
1046 };