2 * Device Tree Source for UniPhier PXs2 SoC
4 * Copyright (C) 2015-2016 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
10 #include <dt-bindings/gpio/uniphier-gpio.h>
11 #include <dt-bindings/thermal/thermal.h>
14 compatible = "socionext,uniphier-pxs2";
24 compatible = "arm,cortex-a9";
26 clocks = <&sys_clk 32>;
27 enable-method = "psci";
28 next-level-cache = <&l2>;
29 operating-points-v2 = <&cpu_opp>;
35 compatible = "arm,cortex-a9";
37 clocks = <&sys_clk 32>;
38 enable-method = "psci";
39 next-level-cache = <&l2>;
40 operating-points-v2 = <&cpu_opp>;
45 compatible = "arm,cortex-a9";
47 clocks = <&sys_clk 32>;
48 enable-method = "psci";
49 next-level-cache = <&l2>;
50 operating-points-v2 = <&cpu_opp>;
55 compatible = "arm,cortex-a9";
57 clocks = <&sys_clk 32>;
58 enable-method = "psci";
59 next-level-cache = <&l2>;
60 operating-points-v2 = <&cpu_opp>;
65 compatible = "operating-points-v2";
69 opp-hz = /bits/ 64 <100000000>;
70 clock-latency-ns = <300>;
73 opp-hz = /bits/ 64 <150000000>;
74 clock-latency-ns = <300>;
77 opp-hz = /bits/ 64 <200000000>;
78 clock-latency-ns = <300>;
81 opp-hz = /bits/ 64 <300000000>;
82 clock-latency-ns = <300>;
85 opp-hz = /bits/ 64 <400000000>;
86 clock-latency-ns = <300>;
89 opp-hz = /bits/ 64 <600000000>;
90 clock-latency-ns = <300>;
93 opp-hz = /bits/ 64 <800000000>;
94 clock-latency-ns = <300>;
97 opp-hz = /bits/ 64 <1200000000>;
98 clock-latency-ns = <300>;
103 compatible = "arm,psci-0.2";
109 compatible = "fixed-clock";
111 clock-frequency = <25000000>;
114 arm_timer_clk: arm-timer {
116 compatible = "fixed-clock";
117 clock-frequency = <50000000>;
123 polling-delay-passive = <250>; /* 250ms */
124 polling-delay = <1000>; /* 1000ms */
125 thermal-sensors = <&pvtctl>;
129 temperature = <95000>; /* 95C */
133 cpu_alert: cpu-alert {
134 temperature = <85000>; /* 85C */
143 cooling-device = <&cpu0
144 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
151 compatible = "simple-bus";
152 #address-cells = <1>;
155 interrupt-parent = <&intc>;
157 l2: l2-cache@500c0000 {
158 compatible = "socionext,uniphier-system-cache";
159 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
161 interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
163 cache-size = <(1280 * 1024)>;
165 cache-line-size = <128>;
169 serial0: serial@54006800 {
170 compatible = "socionext,uniphier-uart";
172 reg = <0x54006800 0x40>;
173 interrupts = <0 33 4>;
174 pinctrl-names = "default";
175 pinctrl-0 = <&pinctrl_uart0>;
176 clocks = <&peri_clk 0>;
177 resets = <&peri_rst 0>;
180 serial1: serial@54006900 {
181 compatible = "socionext,uniphier-uart";
183 reg = <0x54006900 0x40>;
184 interrupts = <0 35 4>;
185 pinctrl-names = "default";
186 pinctrl-0 = <&pinctrl_uart1>;
187 clocks = <&peri_clk 1>;
188 resets = <&peri_rst 1>;
191 serial2: serial@54006a00 {
192 compatible = "socionext,uniphier-uart";
194 reg = <0x54006a00 0x40>;
195 interrupts = <0 37 4>;
196 pinctrl-names = "default";
197 pinctrl-0 = <&pinctrl_uart2>;
198 clocks = <&peri_clk 2>;
199 resets = <&peri_rst 2>;
202 serial3: serial@54006b00 {
203 compatible = "socionext,uniphier-uart";
205 reg = <0x54006b00 0x40>;
206 interrupts = <0 177 4>;
207 pinctrl-names = "default";
208 pinctrl-0 = <&pinctrl_uart3>;
209 clocks = <&peri_clk 3>;
210 resets = <&peri_rst 3>;
213 gpio: gpio@55000000 {
214 compatible = "socionext,uniphier-gpio";
215 reg = <0x55000000 0x200>;
216 interrupt-parent = <&aidet>;
217 interrupt-controller;
218 #interrupt-cells = <2>;
221 gpio-ranges = <&pinctrl 0 0 0>,
223 gpio-ranges-group-names = "gpio_range0",
226 socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
231 compatible = "socionext,uniphier-fi2c";
233 reg = <0x58780000 0x80>;
234 #address-cells = <1>;
236 interrupts = <0 41 4>;
237 pinctrl-names = "default";
238 pinctrl-0 = <&pinctrl_i2c0>;
239 clocks = <&peri_clk 4>;
240 resets = <&peri_rst 4>;
241 clock-frequency = <100000>;
245 compatible = "socionext,uniphier-fi2c";
247 reg = <0x58781000 0x80>;
248 #address-cells = <1>;
250 interrupts = <0 42 4>;
251 pinctrl-names = "default";
252 pinctrl-0 = <&pinctrl_i2c1>;
253 clocks = <&peri_clk 5>;
254 resets = <&peri_rst 5>;
255 clock-frequency = <100000>;
259 compatible = "socionext,uniphier-fi2c";
261 reg = <0x58782000 0x80>;
262 #address-cells = <1>;
264 interrupts = <0 43 4>;
265 pinctrl-names = "default";
266 pinctrl-0 = <&pinctrl_i2c2>;
267 clocks = <&peri_clk 6>;
268 resets = <&peri_rst 6>;
269 clock-frequency = <100000>;
273 compatible = "socionext,uniphier-fi2c";
275 reg = <0x58783000 0x80>;
276 #address-cells = <1>;
278 interrupts = <0 44 4>;
279 pinctrl-names = "default";
280 pinctrl-0 = <&pinctrl_i2c3>;
281 clocks = <&peri_clk 7>;
282 resets = <&peri_rst 7>;
283 clock-frequency = <100000>;
286 /* chip-internal connection for DMD */
288 compatible = "socionext,uniphier-fi2c";
289 reg = <0x58784000 0x80>;
290 #address-cells = <1>;
292 interrupts = <0 45 4>;
293 clocks = <&peri_clk 8>;
294 resets = <&peri_rst 8>;
295 clock-frequency = <400000>;
298 /* chip-internal connection for STM */
300 compatible = "socionext,uniphier-fi2c";
301 reg = <0x58785000 0x80>;
302 #address-cells = <1>;
304 interrupts = <0 25 4>;
305 clocks = <&peri_clk 9>;
306 resets = <&peri_rst 9>;
307 clock-frequency = <400000>;
310 /* chip-internal connection for HDMI */
312 compatible = "socionext,uniphier-fi2c";
313 reg = <0x58786000 0x80>;
314 #address-cells = <1>;
316 interrupts = <0 26 4>;
317 clocks = <&peri_clk 10>;
318 resets = <&peri_rst 10>;
319 clock-frequency = <400000>;
322 system_bus: system-bus@58c00000 {
323 compatible = "socionext,uniphier-system-bus";
325 reg = <0x58c00000 0x400>;
326 #address-cells = <2>;
328 pinctrl-names = "default";
329 pinctrl-0 = <&pinctrl_system_bus>;
333 compatible = "socionext,uniphier-smpctrl";
334 reg = <0x59801000 0x400>;
338 compatible = "socionext,uniphier-pxs2-sdctrl",
339 "simple-mfd", "syscon";
340 reg = <0x59810000 0x400>;
343 compatible = "socionext,uniphier-pxs2-sd-clock";
348 compatible = "socionext,uniphier-pxs2-sd-reset";
354 compatible = "socionext,uniphier-pxs2-perictrl",
355 "simple-mfd", "syscon";
356 reg = <0x59820000 0x200>;
359 compatible = "socionext,uniphier-pxs2-peri-clock";
364 compatible = "socionext,uniphier-pxs2-peri-reset";
370 compatible = "socionext,uniphier-pxs2-soc-glue",
371 "simple-mfd", "syscon";
372 reg = <0x5f800000 0x2000>;
375 compatible = "socionext,uniphier-pxs2-pinctrl";
380 compatible = "socionext,uniphier-pxs2-soc-glue-debug",
382 #address-cells = <1>;
384 ranges = <0 0x5f900000 0x2000>;
387 compatible = "socionext,uniphier-efuse";
392 compatible = "socionext,uniphier-efuse";
397 aidet: aidet@5fc20000 {
398 compatible = "socionext,uniphier-pxs2-aidet";
399 reg = <0x5fc20000 0x200>;
400 interrupt-controller;
401 #interrupt-cells = <2>;
405 compatible = "arm,cortex-a9-global-timer";
406 reg = <0x60000200 0x20>;
407 interrupts = <1 11 0xf04>;
408 clocks = <&arm_timer_clk>;
412 compatible = "arm,cortex-a9-twd-timer";
413 reg = <0x60000600 0x20>;
414 interrupts = <1 13 0xf04>;
415 clocks = <&arm_timer_clk>;
418 intc: interrupt-controller@60001000 {
419 compatible = "arm,cortex-a9-gic";
420 reg = <0x60001000 0x1000>,
422 #interrupt-cells = <3>;
423 interrupt-controller;
427 compatible = "socionext,uniphier-pxs2-sysctrl",
428 "simple-mfd", "syscon";
429 reg = <0x61840000 0x10000>;
432 compatible = "socionext,uniphier-pxs2-clock";
437 compatible = "socionext,uniphier-pxs2-reset";
442 compatible = "socionext,uniphier-pxs2-thermal";
443 interrupts = <0 3 4>;
444 #thermal-sensor-cells = <0>;
445 socionext,tmod-calibration = <0x0f86 0x6844>;
449 nand: nand@68000000 {
450 compatible = "socionext,uniphier-denali-nand-v5b";
452 reg-names = "nand_data", "denali_reg";
453 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
454 interrupts = <0 65 4>;
455 pinctrl-names = "default";
456 pinctrl-0 = <&pinctrl_nand2cs>;
457 clocks = <&sys_clk 2>;
458 resets = <&sys_rst 2>;
463 #include "uniphier-pinctrl.dtsi"