2 * Device Tree Source for UniPhier PXs2 SoC
4 * Copyright (C) 2015-2016 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
7 * This file is dual-licensed: you can use it either under the terms
8 * of the GPL or the X11 license, at your option. Note that this dual
9 * licensing only applies to this file, and not this project as a
12 * a) This file is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
17 * This file is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
24 * b) Permission is hereby granted, free of charge, to any person
25 * obtaining a copy of this software and associated documentation
26 * files (the "Software"), to deal in the Software without
27 * restriction, including without limitation the rights to use,
28 * copy, modify, merge, publish, distribute, sublicense, and/or
29 * sell copies of the Software, and to permit persons to whom the
30 * Software is furnished to do so, subject to the following
33 * The above copyright notice and this permission notice shall be
34 * included in all copies or substantial portions of the Software.
36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43 * OTHER DEALINGS IN THE SOFTWARE.
46 /include/ "skeleton.dtsi"
49 compatible = "socionext,uniphier-pxs2";
57 compatible = "arm,cortex-a9";
59 clocks = <&sys_clk 32>;
60 enable-method = "psci";
61 next-level-cache = <&l2>;
62 operating-points-v2 = <&cpu_opp>;
67 compatible = "arm,cortex-a9";
69 clocks = <&sys_clk 32>;
70 enable-method = "psci";
71 next-level-cache = <&l2>;
72 operating-points-v2 = <&cpu_opp>;
77 compatible = "arm,cortex-a9";
79 clocks = <&sys_clk 32>;
80 enable-method = "psci";
81 next-level-cache = <&l2>;
82 operating-points-v2 = <&cpu_opp>;
87 compatible = "arm,cortex-a9";
89 clocks = <&sys_clk 32>;
90 enable-method = "psci";
91 next-level-cache = <&l2>;
92 operating-points-v2 = <&cpu_opp>;
97 compatible = "operating-points-v2";
101 opp-hz = /bits/ 64 <100000000>;
102 clock-latency-ns = <300>;
105 opp-hz = /bits/ 64 <150000000>;
106 clock-latency-ns = <300>;
109 opp-hz = /bits/ 64 <200000000>;
110 clock-latency-ns = <300>;
113 opp-hz = /bits/ 64 <300000000>;
114 clock-latency-ns = <300>;
117 opp-hz = /bits/ 64 <400000000>;
118 clock-latency-ns = <300>;
121 opp-hz = /bits/ 64 <600000000>;
122 clock-latency-ns = <300>;
125 opp-hz = /bits/ 64 <800000000>;
126 clock-latency-ns = <300>;
129 opp-hz = /bits/ 64 <1200000000>;
130 clock-latency-ns = <300>;
135 compatible = "arm,psci-0.2";
141 compatible = "fixed-clock";
143 clock-frequency = <25000000>;
146 arm_timer_clk: arm_timer_clk {
148 compatible = "fixed-clock";
149 clock-frequency = <50000000>;
154 compatible = "simple-bus";
155 #address-cells = <1>;
158 interrupt-parent = <&intc>;
160 l2: l2-cache@500c0000 {
161 compatible = "socionext,uniphier-system-cache";
162 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
164 interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
166 cache-size = <(1280 * 1024)>;
168 cache-line-size = <128>;
172 serial0: serial@54006800 {
173 compatible = "socionext,uniphier-uart";
175 reg = <0x54006800 0x40>;
176 interrupts = <0 33 4>;
177 pinctrl-names = "default";
178 pinctrl-0 = <&pinctrl_uart0>;
179 clocks = <&peri_clk 0>;
182 serial1: serial@54006900 {
183 compatible = "socionext,uniphier-uart";
185 reg = <0x54006900 0x40>;
186 interrupts = <0 35 4>;
187 pinctrl-names = "default";
188 pinctrl-0 = <&pinctrl_uart1>;
189 clocks = <&peri_clk 1>;
192 serial2: serial@54006a00 {
193 compatible = "socionext,uniphier-uart";
195 reg = <0x54006a00 0x40>;
196 interrupts = <0 37 4>;
197 pinctrl-names = "default";
198 pinctrl-0 = <&pinctrl_uart2>;
199 clocks = <&peri_clk 2>;
202 serial3: serial@54006b00 {
203 compatible = "socionext,uniphier-uart";
205 reg = <0x54006b00 0x40>;
206 interrupts = <0 177 4>;
207 pinctrl-names = "default";
208 pinctrl-0 = <&pinctrl_uart3>;
209 clocks = <&peri_clk 3>;
213 compatible = "socionext,uniphier-fi2c";
215 reg = <0x58780000 0x80>;
216 #address-cells = <1>;
218 interrupts = <0 41 4>;
219 pinctrl-names = "default";
220 pinctrl-0 = <&pinctrl_i2c0>;
221 clocks = <&peri_clk 4>;
222 clock-frequency = <100000>;
226 compatible = "socionext,uniphier-fi2c";
228 reg = <0x58781000 0x80>;
229 #address-cells = <1>;
231 interrupts = <0 42 4>;
232 pinctrl-names = "default";
233 pinctrl-0 = <&pinctrl_i2c1>;
234 clocks = <&peri_clk 5>;
235 clock-frequency = <100000>;
239 compatible = "socionext,uniphier-fi2c";
241 reg = <0x58782000 0x80>;
242 #address-cells = <1>;
244 interrupts = <0 43 4>;
245 pinctrl-names = "default";
246 pinctrl-0 = <&pinctrl_i2c2>;
247 clocks = <&peri_clk 6>;
248 clock-frequency = <100000>;
252 compatible = "socionext,uniphier-fi2c";
254 reg = <0x58783000 0x80>;
255 #address-cells = <1>;
257 interrupts = <0 44 4>;
258 pinctrl-names = "default";
259 pinctrl-0 = <&pinctrl_i2c3>;
260 clocks = <&peri_clk 7>;
261 clock-frequency = <100000>;
264 /* chip-internal connection for DMD */
266 compatible = "socionext,uniphier-fi2c";
267 reg = <0x58784000 0x80>;
268 #address-cells = <1>;
270 interrupts = <0 45 4>;
271 clocks = <&peri_clk 8>;
272 clock-frequency = <400000>;
275 /* chip-internal connection for STM */
277 compatible = "socionext,uniphier-fi2c";
278 reg = <0x58785000 0x80>;
279 #address-cells = <1>;
281 interrupts = <0 25 4>;
282 clocks = <&peri_clk 9>;
283 clock-frequency = <400000>;
286 /* chip-internal connection for HDMI */
288 compatible = "socionext,uniphier-fi2c";
289 reg = <0x58786000 0x80>;
290 #address-cells = <1>;
292 interrupts = <0 26 4>;
293 clocks = <&peri_clk 10>;
294 clock-frequency = <400000>;
297 system_bus: system-bus@58c00000 {
298 compatible = "socionext,uniphier-system-bus";
300 reg = <0x58c00000 0x400>;
301 #address-cells = <2>;
303 pinctrl-names = "default";
304 pinctrl-0 = <&pinctrl_system_bus>;
308 compatible = "socionext,uniphier-smpctrl";
309 reg = <0x59801000 0x400>;
313 compatible = "socionext,uniphier-pxs2-sdctrl",
314 "simple-mfd", "syscon";
315 reg = <0x59810000 0x800>;
318 compatible = "socionext,uniphier-pxs2-sd-clock";
323 compatible = "socionext,uniphier-pxs2-sd-reset";
329 compatible = "socionext,uniphier-pxs2-perictrl",
330 "simple-mfd", "syscon";
331 reg = <0x59820000 0x200>;
334 compatible = "socionext,uniphier-pxs2-peri-clock";
339 compatible = "socionext,uniphier-pxs2-peri-reset";
345 compatible = "socionext,uniphier-pxs2-soc-glue",
346 "simple-mfd", "syscon";
347 reg = <0x5f800000 0x2000>;
350 compatible = "socionext,uniphier-pxs2-pinctrl";
355 compatible = "arm,cortex-a9-global-timer";
356 reg = <0x60000200 0x20>;
357 interrupts = <1 11 0xf04>;
358 clocks = <&arm_timer_clk>;
362 compatible = "arm,cortex-a9-twd-timer";
363 reg = <0x60000600 0x20>;
364 interrupts = <1 13 0xf04>;
365 clocks = <&arm_timer_clk>;
368 intc: interrupt-controller@60001000 {
369 compatible = "arm,cortex-a9-gic";
370 reg = <0x60001000 0x1000>,
372 #interrupt-cells = <3>;
373 interrupt-controller;
377 compatible = "socionext,uniphier-pxs2-sysctrl",
378 "simple-mfd", "syscon";
379 reg = <0x61840000 0x10000>;
382 compatible = "socionext,uniphier-pxs2-clock";
387 compatible = "socionext,uniphier-pxs2-reset";
394 /include/ "uniphier-pinctrl.dtsi"