1 // SPDX-License-Identifier: GPL-2.0
3 * ARM Ltd. Versatile Express
5 * CoreTile Express A15x2 A7x3
6 * Cortex-A15_A7 MPCore (V2P-CA15_A7)
14 model = "V2P-CA15_CA7";
16 arm,vexpress,site = <0xf>;
17 compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress";
18 interrupt-parent = <&gic>;
25 serial0 = &v2m_serial0;
26 serial1 = &v2m_serial1;
27 serial2 = &v2m_serial2;
28 serial3 = &v2m_serial3;
39 compatible = "arm,cortex-a15";
41 cci-control-port = <&cci_control1>;
42 cpu-idle-states = <&CLUSTER_SLEEP_BIG>;
43 capacity-dmips-mhz = <1024>;
48 compatible = "arm,cortex-a15";
50 cci-control-port = <&cci_control1>;
51 cpu-idle-states = <&CLUSTER_SLEEP_BIG>;
52 capacity-dmips-mhz = <1024>;
57 compatible = "arm,cortex-a7";
59 cci-control-port = <&cci_control2>;
60 cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
61 capacity-dmips-mhz = <516>;
66 compatible = "arm,cortex-a7";
68 cci-control-port = <&cci_control2>;
69 cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
70 capacity-dmips-mhz = <516>;
75 compatible = "arm,cortex-a7";
77 cci-control-port = <&cci_control2>;
78 cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
79 capacity-dmips-mhz = <516>;
83 CLUSTER_SLEEP_BIG: cluster-sleep-big {
84 compatible = "arm,idle-state";
86 entry-latency-us = <1000>;
87 exit-latency-us = <700>;
88 min-residency-us = <2000>;
91 CLUSTER_SLEEP_LITTLE: cluster-sleep-little {
92 compatible = "arm,idle-state";
94 entry-latency-us = <1000>;
95 exit-latency-us = <500>;
96 min-residency-us = <2500>;
102 device_type = "memory";
103 reg = <0 0x80000000 0 0x40000000>;
107 compatible = "arm,sp805", "arm,primecell";
108 reg = <0 0x2a490000 0 0x1000>;
109 interrupts = <0 98 4>;
110 clocks = <&oscclk6a>, <&oscclk6a>;
111 clock-names = "wdogclk", "apb_pclk";
115 compatible = "arm,hdlcd";
116 reg = <0 0x2b000000 0 0x1000>;
117 interrupts = <0 85 4>;
118 clocks = <&hdlcd_clk>;
119 clock-names = "pxlclk";
122 memory-controller@2b0a0000 {
123 compatible = "arm,pl341", "arm,primecell";
124 reg = <0 0x2b0a0000 0 0x1000>;
125 clocks = <&oscclk6a>;
126 clock-names = "apb_pclk";
129 gic: interrupt-controller@2c001000 {
130 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
131 #interrupt-cells = <3>;
132 #address-cells = <0>;
133 interrupt-controller;
134 reg = <0 0x2c001000 0 0x1000>,
135 <0 0x2c002000 0 0x2000>,
136 <0 0x2c004000 0 0x2000>,
137 <0 0x2c006000 0 0x2000>;
138 interrupts = <1 9 0xf04>;
142 compatible = "arm,cci-400";
143 #address-cells = <1>;
145 reg = <0 0x2c090000 0 0x1000>;
146 ranges = <0x0 0x0 0x2c090000 0x10000>;
148 cci_control1: slave-if@4000 {
149 compatible = "arm,cci-400-ctrl-if";
150 interface-type = "ace";
151 reg = <0x4000 0x1000>;
154 cci_control2: slave-if@5000 {
155 compatible = "arm,cci-400-ctrl-if";
156 interface-type = "ace";
157 reg = <0x5000 0x1000>;
161 compatible = "arm,cci-400-pmu,r0";
162 reg = <0x9000 0x5000>;
163 interrupts = <0 105 4>,
171 memory-controller@7ffd0000 {
172 compatible = "arm,pl354", "arm,primecell";
173 reg = <0 0x7ffd0000 0 0x1000>;
174 interrupts = <0 86 4>,
176 clocks = <&oscclk6a>;
177 clock-names = "apb_pclk";
181 compatible = "arm,pl330", "arm,primecell";
182 reg = <0 0x7ff00000 0 0x1000>;
183 interrupts = <0 92 4>,
188 clocks = <&oscclk6a>;
189 clock-names = "apb_pclk";
193 compatible = "arm,vexpress-scc,v2p-ca15_a7", "arm,vexpress-scc";
194 reg = <0 0x7fff0000 0 0x1000>;
195 interrupts = <0 95 4>;
199 compatible = "arm,armv7-timer";
200 interrupts = <1 13 0xf08>,
207 compatible = "arm,cortex-a15-pmu";
208 interrupts = <0 68 4>,
210 interrupt-affinity = <&cpu0>,
215 compatible = "arm,cortex-a7-pmu";
216 interrupts = <0 128 4>,
219 interrupt-affinity = <&cpu2>,
225 /* Reference 24MHz clock */
226 compatible = "fixed-clock";
228 clock-frequency = <24000000>;
229 clock-output-names = "oscclk6a";
233 compatible = "arm,vexpress,config-bus";
234 arm,vexpress,config-bridge = <&v2m_sysreg>;
237 /* A15 PLL 0 reference clock */
238 compatible = "arm,vexpress-osc";
239 arm,vexpress-sysreg,func = <1 0>;
240 freq-range = <17000000 50000000>;
242 clock-output-names = "oscclk0";
246 /* A15 PLL 1 reference clock */
247 compatible = "arm,vexpress-osc";
248 arm,vexpress-sysreg,func = <1 1>;
249 freq-range = <17000000 50000000>;
251 clock-output-names = "oscclk1";
255 /* A7 PLL 0 reference clock */
256 compatible = "arm,vexpress-osc";
257 arm,vexpress-sysreg,func = <1 2>;
258 freq-range = <17000000 50000000>;
260 clock-output-names = "oscclk2";
264 /* A7 PLL 1 reference clock */
265 compatible = "arm,vexpress-osc";
266 arm,vexpress-sysreg,func = <1 3>;
267 freq-range = <17000000 50000000>;
269 clock-output-names = "oscclk3";
273 /* External AXI master clock */
274 compatible = "arm,vexpress-osc";
275 arm,vexpress-sysreg,func = <1 4>;
276 freq-range = <20000000 40000000>;
278 clock-output-names = "oscclk4";
282 /* HDLCD PLL reference clock */
283 compatible = "arm,vexpress-osc";
284 arm,vexpress-sysreg,func = <1 5>;
285 freq-range = <23750000 165000000>;
287 clock-output-names = "oscclk5";
291 /* Static memory controller clock */
292 compatible = "arm,vexpress-osc";
293 arm,vexpress-sysreg,func = <1 6>;
294 freq-range = <20000000 40000000>;
296 clock-output-names = "oscclk6";
300 /* SYS PLL reference clock */
301 compatible = "arm,vexpress-osc";
302 arm,vexpress-sysreg,func = <1 7>;
303 freq-range = <17000000 50000000>;
305 clock-output-names = "oscclk7";
309 /* DDR2 PLL reference clock */
310 compatible = "arm,vexpress-osc";
311 arm,vexpress-sysreg,func = <1 8>;
312 freq-range = <20000000 50000000>;
314 clock-output-names = "oscclk8";
318 /* A15 CPU core voltage */
319 compatible = "arm,vexpress-volt";
320 arm,vexpress-sysreg,func = <2 0>;
321 regulator-name = "A15 Vcore";
322 regulator-min-microvolt = <800000>;
323 regulator-max-microvolt = <1050000>;
329 /* A7 CPU core voltage */
330 compatible = "arm,vexpress-volt";
331 arm,vexpress-sysreg,func = <2 1>;
332 regulator-name = "A7 Vcore";
333 regulator-min-microvolt = <800000>;
334 regulator-max-microvolt = <1050000>;
340 /* Total current for the two A15 cores */
341 compatible = "arm,vexpress-amp";
342 arm,vexpress-sysreg,func = <3 0>;
347 /* Total current for the three A7 cores */
348 compatible = "arm,vexpress-amp";
349 arm,vexpress-sysreg,func = <3 1>;
354 /* DCC internal temperature */
355 compatible = "arm,vexpress-temp";
356 arm,vexpress-sysreg,func = <4 0>;
361 /* Total power for the two A15 cores */
362 compatible = "arm,vexpress-power";
363 arm,vexpress-sysreg,func = <12 0>;
368 /* Total power for the three A7 cores */
369 compatible = "arm,vexpress-power";
370 arm,vexpress-sysreg,func = <12 1>;
375 /* Total energy for the two A15 cores */
376 compatible = "arm,vexpress-energy";
377 arm,vexpress-sysreg,func = <13 0>, <13 1>;
382 /* Total energy for the three A7 cores */
383 compatible = "arm,vexpress-energy";
384 arm,vexpress-sysreg,func = <13 2>, <13 3>;
390 compatible = "arm,coresight-etb10", "arm,primecell";
391 reg = <0 0x20010000 0 0x1000>;
393 clocks = <&oscclk6a>;
394 clock-names = "apb_pclk";
396 etb_in_port: endpoint {
398 remote-endpoint = <&replicator_out_port0>;
404 compatible = "arm,coresight-tpiu", "arm,primecell";
405 reg = <0 0x20030000 0 0x1000>;
407 clocks = <&oscclk6a>;
408 clock-names = "apb_pclk";
410 tpiu_in_port: endpoint {
412 remote-endpoint = <&replicator_out_port1>;
418 /* non-configurable replicators don't show up on the
419 * AMBA bus. As such no need to add "arm,primecell".
421 compatible = "arm,coresight-replicator";
424 #address-cells = <1>;
427 /* replicator output ports */
430 replicator_out_port0: endpoint {
431 remote-endpoint = <&etb_in_port>;
437 replicator_out_port1: endpoint {
438 remote-endpoint = <&tpiu_in_port>;
442 /* replicator input port */
445 replicator_in_port0: endpoint {
447 remote-endpoint = <&funnel_out_port0>;
454 compatible = "arm,coresight-funnel", "arm,primecell";
455 reg = <0 0x20040000 0 0x1000>;
457 clocks = <&oscclk6a>;
458 clock-names = "apb_pclk";
460 #address-cells = <1>;
463 /* funnel output port */
466 funnel_out_port0: endpoint {
468 <&replicator_in_port0>;
472 /* funnel input ports */
475 funnel_in_port0: endpoint {
477 remote-endpoint = <&ptm0_out_port>;
483 funnel_in_port1: endpoint {
485 remote-endpoint = <&ptm1_out_port>;
491 funnel_in_port2: endpoint {
493 remote-endpoint = <&etm0_out_port>;
497 /* Input port #3 is for ITM, not supported here */
501 funnel_in_port4: endpoint {
503 remote-endpoint = <&etm1_out_port>;
509 funnel_in_port5: endpoint {
511 remote-endpoint = <&etm2_out_port>;
518 compatible = "arm,coresight-etm3x", "arm,primecell";
519 reg = <0 0x2201c000 0 0x1000>;
522 clocks = <&oscclk6a>;
523 clock-names = "apb_pclk";
525 ptm0_out_port: endpoint {
526 remote-endpoint = <&funnel_in_port0>;
532 compatible = "arm,coresight-etm3x", "arm,primecell";
533 reg = <0 0x2201d000 0 0x1000>;
536 clocks = <&oscclk6a>;
537 clock-names = "apb_pclk";
539 ptm1_out_port: endpoint {
540 remote-endpoint = <&funnel_in_port1>;
546 compatible = "arm,coresight-etm3x", "arm,primecell";
547 reg = <0 0x2203c000 0 0x1000>;
550 clocks = <&oscclk6a>;
551 clock-names = "apb_pclk";
553 etm0_out_port: endpoint {
554 remote-endpoint = <&funnel_in_port2>;
560 compatible = "arm,coresight-etm3x", "arm,primecell";
561 reg = <0 0x2203d000 0 0x1000>;
564 clocks = <&oscclk6a>;
565 clock-names = "apb_pclk";
567 etm1_out_port: endpoint {
568 remote-endpoint = <&funnel_in_port4>;
574 compatible = "arm,coresight-etm3x", "arm,primecell";
575 reg = <0 0x2203e000 0 0x1000>;
578 clocks = <&oscclk6a>;
579 clock-names = "apb_pclk";
581 etm2_out_port: endpoint {
582 remote-endpoint = <&funnel_in_port5>;
588 compatible = "simple-bus";
590 #address-cells = <2>;
592 ranges = <0 0 0 0x08000000 0x04000000>,
593 <1 0 0 0x14000000 0x04000000>,
594 <2 0 0 0x18000000 0x04000000>,
595 <3 0 0 0x1c000000 0x04000000>,
596 <4 0 0 0x0c000000 0x04000000>,
597 <5 0 0 0x10000000 0x04000000>;
599 #interrupt-cells = <1>;
600 interrupt-map-mask = <0 0 63>;
601 interrupt-map = <0 0 0 &gic 0 0 4>,
611 <0 0 10 &gic 0 10 4>,
612 <0 0 11 &gic 0 11 4>,
613 <0 0 12 &gic 0 12 4>,
614 <0 0 13 &gic 0 13 4>,
615 <0 0 14 &gic 0 14 4>,
616 <0 0 15 &gic 0 15 4>,
617 <0 0 16 &gic 0 16 4>,
618 <0 0 17 &gic 0 17 4>,
619 <0 0 18 &gic 0 18 4>,
620 <0 0 19 &gic 0 19 4>,
621 <0 0 20 &gic 0 20 4>,
622 <0 0 21 &gic 0 21 4>,
623 <0 0 22 &gic 0 22 4>,
624 <0 0 23 &gic 0 23 4>,
625 <0 0 24 &gic 0 24 4>,
626 <0 0 25 &gic 0 25 4>,
627 <0 0 26 &gic 0 26 4>,
628 <0 0 27 &gic 0 27 4>,
629 <0 0 28 &gic 0 28 4>,
630 <0 0 29 &gic 0 29 4>,
631 <0 0 30 &gic 0 30 4>,
632 <0 0 31 &gic 0 31 4>,
633 <0 0 32 &gic 0 32 4>,
634 <0 0 33 &gic 0 33 4>,
635 <0 0 34 &gic 0 34 4>,
636 <0 0 35 &gic 0 35 4>,
637 <0 0 36 &gic 0 36 4>,
638 <0 0 37 &gic 0 37 4>,
639 <0 0 38 &gic 0 38 4>,
640 <0 0 39 &gic 0 39 4>,
641 <0 0 40 &gic 0 40 4>,
642 <0 0 41 &gic 0 41 4>,
643 <0 0 42 &gic 0 42 4>;
645 /include/ "vexpress-v2m-rs1.dtsi"
648 site2: hsb@40000000 {
649 compatible = "simple-bus";
650 #address-cells = <1>;
652 ranges = <0 0 0x40000000 0x3fef0000>;
653 #interrupt-cells = <1>;
654 interrupt-map-mask = <0 3>;
655 interrupt-map = <0 0 &gic 0 36 4>,