2 * Copyright (C) 2015, 2016 Zodiac Inflight Innovations
4 * Based on an original 'vf610-twr.dts' which is Copyright 2015,
5 * Freescale Semiconductor, Inc.
7 * This file is dual-licensed: you can use it either under the terms
8 * of the GPL or the X11 license, at your option. Note that this dual
9 * licensing only applies to this file, and not this project as a
12 * a) This file is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * version 2 as published by the Free Software Foundation.
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
46 #include "vf610-zii-dev.dtsi"
49 model = "ZII VF610 Development Board, Rev B";
50 compatible = "zii,vf610dev-b", "zii,vf610dev", "fsl,vf610";
53 compatible = "mdio-mux-gpio";
54 pinctrl-0 = <&pinctrl_mdio_mux>;
55 pinctrl-names = "default";
56 gpios = <&gpio0 8 GPIO_ACTIVE_HIGH
57 &gpio0 9 GPIO_ACTIVE_HIGH
58 &gpio0 24 GPIO_ACTIVE_HIGH
59 &gpio0 25 GPIO_ACTIVE_HIGH>;
60 mdio-parent-bus = <&mdio1>;
70 compatible = "marvell,mv88e6085";
71 pinctrl-0 = <&pinctrl_gpio_switch0>;
72 pinctrl-names = "default";
77 interrupt-parent = <&gpio0>;
78 interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
80 #interrupt-cells = <2>;
81 eeprom-length = <512>;
90 phy-handle = <&switch0phy0>;
96 phy-handle = <&switch0phy1>;
102 phy-handle = <&switch0phy2>;
105 switch0port5: port@5 {
108 phy-mode = "rgmii-txid";
109 link = <&switch1port6
129 #address-cells = <1>;
131 switch0phy0: switch0phy0@0 {
133 interrupt-parent = <&switch0>;
134 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
136 switch0phy1: switch1phy0@1 {
138 interrupt-parent = <&switch0>;
139 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
141 switch0phy2: switch1phy0@2 {
143 interrupt-parent = <&switch0>;
144 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
152 #address-cells = <1>;
156 compatible = "marvell,mv88e6085";
157 pinctrl-0 = <&pinctrl_gpio_switch1>;
158 pinctrl-names = "default";
159 #address-cells = <1>;
163 interrupt-parent = <&gpio0>;
164 interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
165 interrupt-controller;
166 #interrupt-cells = <2>;
167 eeprom-length = <512>;
170 #address-cells = <1>;
176 phy-handle = <&switch1phy0>;
182 phy-handle = <&switch1phy1>;
188 phy-handle = <&switch1phy2>;
191 switch1port5: port@5 {
194 link = <&switch2port9>;
195 phy-mode = "rgmii-txid";
203 switch1port6: port@6 {
206 phy-mode = "rgmii-txid";
207 link = <&switch0port5>;
215 #address-cells = <1>;
218 switch1phy0: switch1phy0@0 {
220 interrupt-parent = <&switch1>;
221 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
224 switch1phy1: switch1phy0@1 {
226 interrupt-parent = <&switch1>;
227 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
230 switch1phy2: switch1phy0@2 {
232 interrupt-parent = <&switch1>;
233 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
240 #address-cells = <1>;
245 compatible = "marvell,mv88e6085";
246 #address-cells = <1>;
252 #address-cells = <1>;
277 link-gpios = <&gpio6 2
289 link-gpios = <&gpio6 3
294 switch2port9: port@9 {
297 phy-mode = "rgmii-txid";
298 link = <&switch1port5
312 #address-cells = <1>;
318 compatible = "spi-gpio";
319 pinctrl-0 = <&pinctrl_gpio_spi0>;
320 pinctrl-names = "default";
321 #address-cells = <1>;
323 gpio-sck = <&gpio1 12 GPIO_ACTIVE_HIGH>;
324 gpio-mosi = <&gpio1 11 GPIO_ACTIVE_HIGH>;
325 gpio-miso = <&gpio1 10 GPIO_ACTIVE_HIGH>;
326 cs-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH
327 &gpio1 8 GPIO_ACTIVE_HIGH>;
328 num-chipselects = <2>;
331 compatible = "m25p128", "jedec,spi-nor";
332 #address-cells = <1>;
335 spi-max-frequency = <1000000>;
339 compatible = "atmel,at93c46d";
340 pinctrl-0 = <&pinctrl_gpio_e6185_eeprom_sel>;
341 pinctrl-names = "default";
342 #address-cells = <0>;
345 spi-max-frequency = <500000>;
348 select-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>;
354 clock-frequency = <100000>;
355 pinctrl-names = "default";
356 pinctrl-0 = <&pinctrl_i2c0>;
360 compatible = "nxp,pca9554";
368 compatible = "nxp,pca9554";
369 pinctrl-names = "default";
370 pinctrl-0 = <&pinctrl_pca9554_22>;
374 interrupt-parent = <&gpio2>;
375 interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
380 clock-frequency = <100000>;
381 pinctrl-names = "default";
382 pinctrl-0 = <&pinctrl_i2c2>;
386 compatible = "nxp,pca9548";
387 pinctrl-0 = <&pinctrl_i2c_mux_reset>;
388 pinctrl-names = "default";
389 #address-cells = <1>;
392 reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
395 #address-cells = <1>;
400 compatible = "atmel,24c02";
406 #address-cells = <1>;
411 compatible = "atmel,24c02";
417 #address-cells = <1>;
422 compatible = "atmel,24c02";
428 #address-cells = <1>;
433 compatible = "atmel,24c02";
439 #address-cells = <1>;
448 pinctrl_gpio_e6185_eeprom_sel: pinctrl-gpio-e6185-eeprom-spi0 {
450 VF610_PAD_PTE27__GPIO_132 0x33e2
454 pinctrl_gpio_spi0: pinctrl-gpio-spi0 {
456 VF610_PAD_PTB22__GPIO_44 0x33e2
457 VF610_PAD_PTB21__GPIO_43 0x33e2
458 VF610_PAD_PTB20__GPIO_42 0x33e1
459 VF610_PAD_PTB19__GPIO_41 0x33e2
460 VF610_PAD_PTB18__GPIO_40 0x33e2
464 pinctrl_mdio_mux: pinctrl-mdio-mux {
466 VF610_PAD_PTA18__GPIO_8 0x31c2
467 VF610_PAD_PTA19__GPIO_9 0x31c2
468 VF610_PAD_PTB2__GPIO_24 0x31c2
469 VF610_PAD_PTB3__GPIO_25 0x31c2
473 pinctrl_pca9554_22: pinctrl-pca95540-22 {
475 VF610_PAD_PTB28__GPIO_98 0x219d