2 * Copyright (C) 2015, 2016 Zodiac Inflight Innovations
4 * Based on an original 'vf610-twr.dts' which is Copyright 2015,
5 * Freescale Semiconductor, Inc.
7 * This file is dual-licensed: you can use it either under the terms
8 * of the GPL or the X11 license, at your option. Note that this dual
9 * licensing only applies to this file, and not this project as a
12 * a) This file is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * version 2 as published by the Free Software Foundation.
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
46 #include "vf610-zii-dev.dtsi"
49 model = "ZII VF610 Development Board, Rev B";
50 compatible = "zii,vf610dev-b", "zii,vf610dev", "fsl,vf610";
53 compatible = "mdio-mux-gpio";
54 pinctrl-0 = <&pinctrl_mdio_mux>;
55 pinctrl-names = "default";
56 gpios = <&gpio0 8 GPIO_ACTIVE_HIGH
57 &gpio0 9 GPIO_ACTIVE_HIGH
58 &gpio0 24 GPIO_ACTIVE_HIGH
59 &gpio0 25 GPIO_ACTIVE_HIGH>;
60 mdio-parent-bus = <&mdio1>;
70 compatible = "marvell,mv88e6085";
71 pinctrl-0 = <&pinctrl_gpio_switch0>;
72 pinctrl-names = "default";
77 interrupt-parent = <&gpio0>;
78 interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
80 #interrupt-cells = <2>;
81 eeprom-length = <512>;
90 phy-handle = <&switch0phy0>;
96 phy-handle = <&switch0phy1>;
102 phy-handle = <&switch0phy2>;
105 switch0port5: port@5 {
108 phy-mode = "rgmii-txid";
109 link = <&switch1port6
129 #address-cells = <1>;
131 switch0phy0: switch0phy0@0 {
133 interrupt-parent = <&switch0>;
134 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
136 switch0phy1: switch1phy0@1 {
138 interrupt-parent = <&switch0>;
139 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
141 switch0phy2: switch1phy0@2 {
143 interrupt-parent = <&switch0>;
144 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
152 #address-cells = <1>;
156 compatible = "marvell,mv88e6085";
157 pinctrl-0 = <&pinctrl_gpio_switch1>;
158 pinctrl-names = "default";
159 #address-cells = <1>;
163 interrupt-parent = <&gpio0>;
164 interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
165 interrupt-controller;
166 #interrupt-cells = <2>;
167 eeprom-length = <512>;
170 #address-cells = <1>;
176 phy-handle = <&switch1phy0>;
182 phy-handle = <&switch1phy1>;
188 phy-handle = <&switch1phy2>;
191 switch1port5: port@5 {
194 link = <&switch2port9>;
195 phy-mode = "rgmii-txid";
203 switch1port6: port@6 {
206 phy-mode = "rgmii-txid";
207 link = <&switch0port5>;
215 #address-cells = <1>;
218 switch1phy0: switch1phy0@0 {
220 interrupt-parent = <&switch1>;
221 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
224 switch1phy1: switch1phy0@1 {
226 interrupt-parent = <&switch1>;
227 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
230 switch1phy2: switch1phy0@2 {
232 interrupt-parent = <&switch1>;
233 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
240 #address-cells = <1>;
245 compatible = "marvell,mv88e6085";
246 #address-cells = <1>;
252 #address-cells = <1>;
258 phy-handle = <&switch2phy0>;
264 phy-handle = <&switch2phy1>;
270 phy-handle = <&switch2phy2>;
280 link-gpios = <&gpio6 2
292 link-gpios = <&gpio6 3
297 switch2port9: port@9 {
300 phy-mode = "rgmii-txid";
301 link = <&switch1port5
311 #address-cells = <1>;
329 #address-cells = <1>;
335 compatible = "spi-gpio";
336 pinctrl-0 = <&pinctrl_gpio_spi0>;
337 pinctrl-names = "default";
338 #address-cells = <1>;
340 gpio-sck = <&gpio1 12 GPIO_ACTIVE_HIGH>;
341 gpio-mosi = <&gpio1 11 GPIO_ACTIVE_HIGH>;
342 gpio-miso = <&gpio1 10 GPIO_ACTIVE_HIGH>;
343 cs-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH
344 &gpio1 8 GPIO_ACTIVE_HIGH>;
345 num-chipselects = <2>;
348 compatible = "m25p128", "jedec,spi-nor";
349 #address-cells = <1>;
352 spi-max-frequency = <1000000>;
356 compatible = "atmel,at93c46d";
357 pinctrl-0 = <&pinctrl_gpio_e6185_eeprom_sel>;
358 pinctrl-names = "default";
359 #address-cells = <0>;
362 spi-max-frequency = <500000>;
365 select-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>;
371 clock-frequency = <100000>;
372 pinctrl-names = "default";
373 pinctrl-0 = <&pinctrl_i2c0>;
377 compatible = "nxp,pca9554";
385 compatible = "nxp,pca9554";
386 pinctrl-names = "default";
387 pinctrl-0 = <&pinctrl_pca9554_22>;
391 interrupt-controller;
392 interrupt-parent = <&gpio3>;
393 interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
398 clock-frequency = <100000>;
399 pinctrl-names = "default";
400 pinctrl-0 = <&pinctrl_i2c2>;
404 compatible = "nxp,pca9548";
405 pinctrl-0 = <&pinctrl_i2c_mux_reset>;
406 pinctrl-names = "default";
407 #address-cells = <1>;
410 reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
413 #address-cells = <1>;
418 compatible = "atmel,24c02";
424 #address-cells = <1>;
429 compatible = "atmel,24c02";
435 #address-cells = <1>;
440 compatible = "atmel,24c02";
446 #address-cells = <1>;
451 compatible = "atmel,24c02";
457 #address-cells = <1>;
466 pinctrl_gpio_e6185_eeprom_sel: pinctrl-gpio-e6185-eeprom-spi0 {
468 VF610_PAD_PTE27__GPIO_132 0x33e2
472 pinctrl_gpio_spi0: pinctrl-gpio-spi0 {
474 VF610_PAD_PTB22__GPIO_44 0x33e2
475 VF610_PAD_PTB21__GPIO_43 0x33e2
476 VF610_PAD_PTB20__GPIO_42 0x33e1
477 VF610_PAD_PTB19__GPIO_41 0x33e2
478 VF610_PAD_PTB18__GPIO_40 0x33e2
482 pinctrl_mdio_mux: pinctrl-mdio-mux {
484 VF610_PAD_PTA18__GPIO_8 0x31c2
485 VF610_PAD_PTA19__GPIO_9 0x31c2
486 VF610_PAD_PTB2__GPIO_24 0x31c2
487 VF610_PAD_PTB3__GPIO_25 0x31c2
491 pinctrl_pca9554_22: pinctrl-pca95540-22 {
493 VF610_PAD_PTB28__GPIO_98 0x219d