sys/gnu/dts/arm/vf610-zii-dev-rev-b.dts

   1 /*
   2  * Copyright (C) 2015, 2016 Zodiac Inflight Innovations
   3  *
   4  * Based on an original 'vf610-twr.dts' which is Copyright 2015,
   5  * Freescale Semiconductor, Inc.
   6  *
   7  * This file is dual-licensed: you can use it either under the terms
   8  * of the GPL or the X11 license, at your option. Note that this dual
   9  * licensing only applies to this file, and not this project as a
  10  * whole.
  11  *
  12  *  a) This file is free software; you can redistribute it and/or
  13  *     modify it under the terms of the GNU General Public License
  14  *     version 2 as published by the Free Software Foundation.
  15  *
  16  *     This file is distributed in the hope that it will be useful
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 /dts-v1/;
  46 #include "vf610.dtsi"
  47
  48 / {
  49         model = "ZII VF610 Development Board, Rev B";
  50         compatible = "zii,vf610dev-b", "zii,vf610dev", "fsl,vf610";
  51
  52         chosen {
  53                 stdout-path = "serial0:115200n8";
  54         };
  55
  56         memory {
  57                 reg = <0x80000000 0x20000000>;
  58         };
  59
  60         gpio-leds {
  61                 compatible = "gpio-leds";
  62                 pinctrl-0 = <&pinctrl_leds_debug>;
  63                 pinctrl-names = "default";
  64
  65                 debug {
  66                         label = "zii:green:debug1";
  67                         gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
  68                         linux,default-trigger = "heartbeat";
  69                 };
  70         };
  71
  72         mdio-mux {
  73                 compatible = "mdio-mux-gpio";
  74                 pinctrl-0 = <&pinctrl_mdio_mux>;
  75                 pinctrl-names = "default";
  76                 gpios = <&gpio0 8  GPIO_ACTIVE_HIGH
  77                          &gpio0 9  GPIO_ACTIVE_HIGH
  78                          &gpio0 24 GPIO_ACTIVE_HIGH
  79                          &gpio0 25 GPIO_ACTIVE_HIGH>;
  80                 mdio-parent-bus = <&mdio1>;
  81                 #address-cells = <1>;
  82                 #size-cells = <0>;
  83
  84                 mdio_mux_1: mdio@1 {
  85                         reg = <1>;
  86                         #address-cells = <1>;
  87                         #size-cells = <0>;
  88
  89                         switch0: switch0@0 {
  90                                 compatible = "marvell,mv88e6085";
  91                                 pinctrl-0 = <&pinctrl_gpio_switch0>;
  92                                 pinctrl-names = "default";
  93                                 #address-cells = <1>;
  94                                 #size-cells = <0>;
  95                                 reg = <0>;
  96                                 dsa,member = <0 0>;
  97                                 interrupt-parent = <&gpio0>;
  98                                 interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
  99                                 interrupt-controller;
 100                                 #interrupt-cells = <2>;
 101
 102                                 ports {
 103                                         #address-cells = <1>;
 104                                         #size-cells = <0>;
 105                                         port@0 {
 106                                                 reg = <0>;
 107                                                 label = "lan0";
 108                                                 phy-handle = <&switch0phy0>;
 109                                         };
 110
 111                                         port@1 {
 112                                                 reg = <1>;
 113                                                 label = "lan1";
 114                                                 phy-handle = <&switch0phy1>;
 115                                         };
 116
 117                                         port@2 {
 118                                                 reg = <2>;
 119                                                 label = "lan2";
 120                                                 phy-handle = <&switch0phy2>;
 121                                         };
 122
 123                                         switch0port5: port@5 {
 124                                                 reg = <5>;
 125                                                 label = "dsa";
 126                                                 phy-mode = "rgmii-txid";
 127                                                 link = <&switch1port6
 128                                                         &switch2port9>;
 129                                                 fixed-link {
 130                                                         speed = <1000>;
 131                                                         full-duplex;
 132                                                 };
 133                                         };
 134
 135                                         port@6 {
 136                                                 reg = <6>;
 137                                                 label = "cpu";
 138                                                 ethernet = <&fec1>;
 139                                                 fixed-link {
 140                                                         speed = <100>;
 141                                                         full-duplex;
 142                                                 };
 143                                         };
 144                                 };
 145                                 mdio {
 146                                         #address-cells = <1>;
 147                                         #size-cells = <0>;
 148                                         switch0phy0: switch0phy0@0 {
 149                                                 reg = <0>;
 150                                                 interrupt-parent = <&switch0>;
 151                                                 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
 152                                         };
 153                                         switch0phy1: switch1phy0@1 {
 154                                                 reg = <1>;
 155                                                 interrupt-parent = <&switch0>;
 156                                                 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
 157                                         };
 158                                         switch0phy2: switch1phy0@2 {
 159                                                 reg = <2>;
 160                                                 interrupt-parent = <&switch0>;
 161                                                 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
 162                                         };
 163                                 };
 164                         };
 165                 };
 166
 167                 mdio_mux_2: mdio@2 {
 168                         reg = <2>;
 169                         #address-cells = <1>;
 170                         #size-cells = <0>;
 171
 172                         switch1: switch1@0 {
 173                                 compatible = "marvell,mv88e6085";
 174                                 pinctrl-0 = <&pinctrl_gpio_switch1>;
 175                                 pinctrl-names = "default";
 176                                 #address-cells = <1>;
 177                                 #size-cells = <0>;
 178                                 reg = <0>;
 179                                 dsa,member = <0 1>;
 180                                 interrupt-parent = <&gpio0>;
 181                                 interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
 182                                 interrupt-controller;
 183                                 #interrupt-cells = <2>;
 184
 185                                 ports {
 186                                         #address-cells = <1>;
 187                                         #size-cells = <0>;
 188                                         port@0 {
 189                                                 reg = <0>;
 190                                                 label = "lan3";
 191                                                 phy-handle = <&switch1phy0>;
 192                                         };
 193
 194                                         port@1 {
 195                                                 reg = <1>;
 196                                                 label = "lan4";
 197                                                 phy-handle = <&switch1phy1>;
 198                                         };
 199
 200                                         port@2 {
 201                                                 reg = <2>;
 202                                                 label = "lan5";
 203                                                 phy-handle = <&switch1phy2>;
 204                                         };
 205
 206                                         switch1port5: port@5 {
 207                                                 reg = <5>;
 208                                                 label = "dsa";
 209                                                 link = <&switch2port9>;
 210                                                 phy-mode = "rgmii-txid";
 211                                                 fixed-link {
 212                                                         speed = <1000>;
 213                                                         full-duplex;
 214                                                 };
 215                                         };
 216
 217                                         switch1port6: port@6 {
 218                                                 reg = <6>;
 219                                                 label = "dsa";
 220                                                 phy-mode = "rgmii-txid";
 221                                                 link = <&switch0port5>;
 222                                                 fixed-link {
 223                                                         speed = <1000>;
 224                                                         full-duplex;
 225                                                 };
 226                                         };
 227                                 };
 228                                 mdio {
 229                                         #address-cells = <1>;
 230                                         #size-cells = <0>;
 231                                         switch1phy0: switch1phy0@0 {
 232                                                 reg = <0>;
 233                                                 interrupt-parent = <&switch1>;
 234                                                 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
 235                                         };
 236                                         switch1phy1: switch1phy0@1 {
 237                                                 reg = <1>;
 238                                                 interrupt-parent = <&switch1>;
 239                                                 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
 240                                         };
 241                                         switch1phy2: switch1phy0@2 {
 242                                                 reg = <2>;
 243                                                 interrupt-parent = <&switch1>;
 244                                                 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
 245                                         };
 246                                 };
 247                         };
 248                 };
 249
 250                 mdio_mux_4: mdio@4 {
 251                         #address-cells = <1>;
 252                         #size-cells = <0>;
 253                         reg = <4>;
 254
 255                         switch2: switch2@0 {
 256                                 compatible = "marvell,mv88e6085";
 257                                 #address-cells = <1>;
 258                                 #size-cells = <0>;
 259                                 reg = <0>;
 260                                 dsa,member = <0 2>;
 261
 262                                 ports {
 263                                         #address-cells = <1>;
 264                                         #size-cells = <0>;
 265                                         port@0 {
 266                                                 reg = <0>;
 267                                                 label = "lan6";
 268                                         };
 269
 270                                         port@1 {
 271                                                 reg = <1>;
 272                                                 label = "lan7";
 273                                         };
 274
 275                                         port@2 {
 276                                                 reg = <2>;
 277                                                 label = "lan8";
 278                                         };
 279
 280                                         port@3 {
 281                                                 reg = <3>;
 282                                                 label = "optical3";
 283                                                 fixed-link {
 284                                                         speed = <1000>;
 285                                                         full-duplex;
 286                                                         link-gpios = <&gpio6 2
 287                                                               GPIO_ACTIVE_HIGH>;
 288                                                 };
 289                                         };
 290
 291                                         port@4 {
 292                                                 reg = <4>;
 293                                                 label = "optical4";
 294                                                 fixed-link {
 295                                                         speed = <1000>;
 296                                                         full-duplex;
 297                                                         link-gpios = <&gpio6 3
 298                                                               GPIO_ACTIVE_HIGH>;
 299                                                 };
 300                                         };
 301
 302                                         switch2port9: port@9 {
 303                                                 reg = <9>;
 304                                                 label = "dsa";
 305                                                 phy-mode = "rgmii-txid";
 306                                                 link = <&switch1port5
 307                                                         &switch0port5>;
 308                                                 fixed-link {
 309                                                         speed = <1000>;
 310                                                         full-duplex;
 311                                                 };
 312                                         };
 313                                 };
 314                         };
 315                 };
 316
 317                 mdio_mux_8: mdio@8 {
 318                         reg = <8>;
 319                         #address-cells = <1>;
 320                         #size-cells = <0>;
 321                 };
 322         };
 323
 324         reg_vcc_3v3_mcu: regulator-vcc-3v3-mcu {
 325                 compatible = "regulator-fixed";
 326                 regulator-name = "vcc_3v3_mcu";
 327                 regulator-min-microvolt = <3300000>;
 328                 regulator-max-microvolt = <3300000>;
 329         };
 330
 331         usb0_vbus: regulator-usb0-vbus {
 332                 compatible = "regulator-fixed";
 333                 pinctrl-0 = <&pinctrl_usb_vbus>;
 334                 regulator-name = "usb_vbus";
 335                 regulator-min-microvolt = <5000000>;
 336                 regulator-max-microvolt = <5000000>;
 337                 enable-active-high;
 338                 regulator-always-on;
 339                 regulator-boot-on;
 340                 gpio = <&gpio0 6 0>;
 341         };
 342
 343         spi0 {
 344                 compatible = "spi-gpio";
 345                 pinctrl-0 = <&pinctrl_gpio_spi0>;
 346                 pinctrl-names = "default";
 347                 #address-cells = <1>;
 348                 #size-cells = <0>;
 349                 gpio-sck  = <&gpio1 12 GPIO_ACTIVE_HIGH>;
 350                 gpio-mosi = <&gpio1 11 GPIO_ACTIVE_HIGH>;
 351                 gpio-miso = <&gpio1 10 GPIO_ACTIVE_HIGH>;
 352                 cs-gpios  = <&gpio1  9 GPIO_ACTIVE_HIGH
 353                              &gpio1  8 GPIO_ACTIVE_HIGH>;
 354                 num-chipselects = <2>;
 355
 356                 m25p128@0 {
 357                         compatible = "m25p128", "jedec,spi-nor";
 358                         #address-cells = <1>;
 359                         #size-cells = <1>;
 360                         reg = <0>;
 361                         spi-max-frequency = <1000000>;
 362                 };
 363
 364                 at93c46d@1 {
 365                         compatible = "atmel,at93c46d";
 366                         pinctrl-0 = <&pinctrl_gpio_e6185_eeprom_sel>;
 367                         pinctrl-names = "default";
 368                         #address-cells = <0>;
 369                         #size-cells = <0>;
 370                         reg = <1>;
 371                         spi-max-frequency = <500000>;
 372                         spi-cs-high;
 373                         data-size = <16>;
 374                         select-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>;
 375                 };
 376         };
 377 };
 378
 379 &adc0 {
 380         pinctrl-names = "default";
 381         pinctrl-0 = <&pinctrl_adc0_ad5>;
 382         vref-supply = <&reg_vcc_3v3_mcu>;
 383         status = "okay";
 384 };
 385
 386 &edma0 {
 387         status = "okay";
 388 };
 389
 390 &esdhc1 {
 391         pinctrl-names = "default";
 392         pinctrl-0 = <&pinctrl_esdhc1>;
 393         bus-width = <4>;
 394         status = "okay";
 395 };
 396
 397 &fec0 {
 398         phy-mode = "rmii";
 399         pinctrl-names = "default";
 400         pinctrl-0 = <&pinctrl_fec0>;
 401         status = "okay";
 402 };
 403
 404 &fec1 {
 405         phy-mode = "rmii";
 406         pinctrl-names = "default";
 407         pinctrl-0 = <&pinctrl_fec1>;
 408         status = "okay";
 409
 410         fixed-link {
 411                    speed = <100>;
 412                    full-duplex;
 413         };
 414
 415         mdio1: mdio {
 416                 #address-cells = <1>;
 417                 #size-cells = <0>;
 418                 status = "okay";
 419         };
 420 };
 421
 422 &i2c0 {
 423         clock-frequency = <100000>;
 424         pinctrl-names = "default";
 425         pinctrl-0 = <&pinctrl_i2c0>;
 426         status = "okay";
 427
 428         gpio5: pca9554@20 {
 429                 compatible = "nxp,pca9554";
 430                 reg = <0x20>;
 431                 gpio-controller;
 432                 #gpio-cells = <2>;
 433
 434         };
 435
 436         gpio6: pca9554@22 {
 437                 compatible = "nxp,pca9554";
 438                 pinctrl-names = "default";
 439                 pinctrl-0 = <&pinctrl_pca9554_22>;
 440                 reg = <0x22>;
 441                 gpio-controller;
 442                 #gpio-cells = <2>;
 443                 interrupt-parent = <&gpio2>;
 444                 interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
 445         };
 446
 447         lm75@48 {
 448                 compatible = "national,lm75";
 449                 reg = <0x48>;
 450         };
 451
 452         at24c04@50 {
 453                 compatible = "atmel,24c04";
 454                 reg = <0x50>;
 455         };
 456
 457         at24c04@52 {
 458                 compatible = "atmel,24c04";
 459                 reg = <0x52>;
 460         };
 461
 462         ds1682@6b {
 463                 compatible = "dallas,ds1682";
 464                 reg = <0x6b>;
 465         };
 466 };
 467
 468 &i2c1 {
 469         clock-frequency = <100000>;
 470         pinctrl-names = "default";
 471         pinctrl-0 = <&pinctrl_i2c1>;
 472         status = "okay";
 473 };
 474
 475 &i2c2 {
 476         clock-frequency = <100000>;
 477         pinctrl-names = "default";
 478         pinctrl-0 = <&pinctrl_i2c2>;
 479         status = "okay";
 480
 481         tca9548@70 {
 482                 compatible = "nxp,pca9548";
 483                 pinctrl-0 = <&pinctrl_i2c_mux_reset>;
 484                 pinctrl-names = "default";
 485                 #address-cells = <1>;
 486                 #size-cells = <0>;
 487                 reg = <0x70>;
 488                 reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
 489
 490                 i2c@0 {
 491                         #address-cells = <1>;
 492                         #size-cells = <0>;
 493                         reg = <0>;
 494
 495                         sfp1: at24c04@50 {
 496                                 compatible = "atmel,24c02";
 497                                 reg = <0x50>;
 498                         };
 499                 };
 500
 501                 i2c@1 {
 502                         #address-cells = <1>;
 503                         #size-cells = <0>;
 504                         reg = <1>;
 505
 506                         sfp2: at24c04@50 {
 507                                 compatible = "atmel,24c02";
 508                                 reg = <0x50>;
 509                         };
 510                 };
 511
 512                 i2c@2 {
 513                         #address-cells = <1>;
 514                         #size-cells = <0>;
 515                         reg = <2>;
 516
 517                         sfp3: at24c04@50 {
 518                                 compatible = "atmel,24c02";
 519                                 reg = <0x50>;
 520                         };
 521                 };
 522
 523                 i2c@3 {
 524                         #address-cells = <1>;
 525                         #size-cells = <0>;
 526                         reg = <3>;
 527
 528                         sfp4: at24c04@50 {
 529                                 compatible = "atmel,24c02";
 530                                 reg = <0x50>;
 531                         };
 532                 };
 533
 534                 i2c@4 {
 535                         #address-cells = <1>;
 536                         #size-cells = <0>;
 537                         reg = <4>;
 538                 };
 539         };
 540 };
 541
 542 &uart0 {
 543         pinctrl-names = "default";
 544         pinctrl-0 = <&pinctrl_uart0>;
 545         status = "okay";
 546 };
 547
 548 &uart1 {
 549         pinctrl-names = "default";
 550         pinctrl-0 = <&pinctrl_uart1>;
 551         status = "okay";
 552 };
 553
 554 &uart2 {
 555         pinctrl-names = "default";
 556         pinctrl-0 = <&pinctrl_uart2>;
 557         status = "okay";
 558 };
 559
 560 &usbdev0 {
 561         disable-over-current;
 562         vbus-supply = <&usb0_vbus>;
 563         dr_mode = "host";
 564         status = "okay";
 565 };
 566
 567 &usbh1 {
 568         disable-over-current;
 569         status = "okay";
 570 };
 571
 572 &usbmisc0 {
 573         status = "okay";
 574 };
 575
 576 &usbmisc1 {
 577         status = "okay";
 578 };
 579
 580 &usbphy0 {
 581         status = "okay";
 582 };
 583
 584 &usbphy1 {
 585         status = "okay";
 586 };
 587
 588 &iomuxc {
 589         pinctrl_adc0_ad5: adc0ad5grp {
 590                 fsl,pins = <
 591                         VF610_PAD_PTC30__ADC0_SE5       0x00a1
 592                 >;
 593         };
 594
 595         pinctrl_dspi0: dspi0grp {
 596                 fsl,pins = <
 597                         VF610_PAD_PTB18__DSPI0_CS1      0x1182
 598                         VF610_PAD_PTB19__DSPI0_CS0      0x1182
 599                         VF610_PAD_PTB20__DSPI0_SIN      0x1181
 600                         VF610_PAD_PTB21__DSPI0_SOUT     0x1182
 601                         VF610_PAD_PTB22__DSPI0_SCK      0x1182
 602                 >;
 603         };
 604
 605         pinctrl_dspi2: dspi2grp {
 606                 fsl,pins = <
 607                         VF610_PAD_PTD31__DSPI2_CS1      0x1182
 608                         VF610_PAD_PTD30__DSPI2_CS0      0x1182
 609                         VF610_PAD_PTD29__DSPI2_SIN      0x1181
 610                         VF610_PAD_PTD28__DSPI2_SOUT     0x1182
 611                         VF610_PAD_PTD27__DSPI2_SCK      0x1182
 612                 >;
 613         };
 614
 615         pinctrl_esdhc1: esdhc1grp {
 616                 fsl,pins = <
 617                         VF610_PAD_PTA24__ESDHC1_CLK     0x31ef
 618                         VF610_PAD_PTA25__ESDHC1_CMD     0x31ef
 619                         VF610_PAD_PTA26__ESDHC1_DAT0    0x31ef
 620                         VF610_PAD_PTA27__ESDHC1_DAT1    0x31ef
 621                         VF610_PAD_PTA28__ESDHC1_DATA2   0x31ef
 622                         VF610_PAD_PTA29__ESDHC1_DAT3    0x31ef
 623                         VF610_PAD_PTA7__GPIO_134        0x219d
 624                 >;
 625         };
 626
 627         pinctrl_fec0: fec0grp {
 628                 fsl,pins = <
 629                         VF610_PAD_PTC0__ENET_RMII0_MDC  0x30d2
 630                         VF610_PAD_PTC1__ENET_RMII0_MDIO 0x30d3
 631                         VF610_PAD_PTC2__ENET_RMII0_CRS  0x30d1
 632                         VF610_PAD_PTC3__ENET_RMII0_RXD1 0x30d1
 633                         VF610_PAD_PTC4__ENET_RMII0_RXD0 0x30d1
 634                         VF610_PAD_PTC5__ENET_RMII0_RXER 0x30d1
 635                         VF610_PAD_PTC6__ENET_RMII0_TXD1 0x30d2
 636                         VF610_PAD_PTC7__ENET_RMII0_TXD0 0x30d2
 637                         VF610_PAD_PTC8__ENET_RMII0_TXEN 0x30d2
 638                 >;
 639         };
 640
 641         pinctrl_fec1: fec1grp {
 642                 fsl,pins = <
 643                         VF610_PAD_PTA6__RMII_CLKIN              0x30d1
 644                         VF610_PAD_PTC9__ENET_RMII1_MDC          0x30d2
 645                         VF610_PAD_PTC10__ENET_RMII1_MDIO        0x30d3
 646                         VF610_PAD_PTC11__ENET_RMII1_CRS         0x30d1
 647                         VF610_PAD_PTC12__ENET_RMII1_RXD1        0x30d1
 648                         VF610_PAD_PTC13__ENET_RMII1_RXD0        0x30d1
 649                         VF610_PAD_PTC14__ENET_RMII1_RXER        0x30d1
 650                         VF610_PAD_PTC15__ENET_RMII1_TXD1        0x30d2
 651                         VF610_PAD_PTC16__ENET_RMII1_TXD0        0x30d2
 652                         VF610_PAD_PTC17__ENET_RMII1_TXEN        0x30d2
 653                 >;
 654         };
 655
 656         pinctrl_gpio_e6185_eeprom_sel: pinctrl-gpio-e6185-eeprom-spi0 {
 657                 fsl,pins = <
 658                         VF610_PAD_PTE27__GPIO_132       0x33e2
 659                 >;
 660         };
 661
 662         pinctrl_gpio_spi0: pinctrl-gpio-spi0 {
 663                 fsl,pins = <
 664                         VF610_PAD_PTB22__GPIO_44        0x33e2
 665                         VF610_PAD_PTB21__GPIO_43        0x33e2
 666                         VF610_PAD_PTB20__GPIO_42        0x33e1
 667                         VF610_PAD_PTB19__GPIO_41        0x33e2
 668                         VF610_PAD_PTB18__GPIO_40        0x33e2
 669                 >;
 670         };
 671
 672         pinctrl_gpio_switch0: pinctrl-gpio-switch0 {
 673                 fsl,pins = <
 674                         VF610_PAD_PTB5__GPIO_27         0x219d
 675                 >;
 676         };
 677
 678         pinctrl_gpio_switch1: pinctrl-gpio-switch1 {
 679                 fsl,pins = <
 680                         VF610_PAD_PTB4__GPIO_26         0x219d
 681                 >;
 682         };
 683
 684         pinctrl_i2c_mux_reset: pinctrl-i2c-mux-reset {
 685                 fsl,pins = <
 686                          VF610_PAD_PTE14__GPIO_119      0x31c2
 687                          >;
 688         };
 689
 690         pinctrl_i2c0: i2c0grp {
 691                 fsl,pins = <
 692                         VF610_PAD_PTB14__I2C0_SCL       0x37ff
 693                         VF610_PAD_PTB15__I2C0_SDA       0x37ff
 694                 >;
 695         };
 696
 697         pinctrl_i2c1: i2c1grp {
 698                 fsl,pins = <
 699                         VF610_PAD_PTB16__I2C1_SCL       0x37ff
 700                         VF610_PAD_PTB17__I2C1_SDA       0x37ff
 701                 >;
 702         };
 703
 704         pinctrl_i2c2: i2c2grp {
 705                 fsl,pins = <
 706                         VF610_PAD_PTA22__I2C2_SCL       0x37ff
 707                         VF610_PAD_PTA23__I2C2_SDA       0x37ff
 708                 >;
 709         };
 710
 711         pinctrl_leds_debug: pinctrl-leds-debug {
 712                 fsl,pins = <
 713                          VF610_PAD_PTD20__GPIO_74       0x31c2
 714                          >;
 715         };
 716
 717         pinctrl_mdio_mux: pinctrl-mdio-mux {
 718                 fsl,pins = <
 719                         VF610_PAD_PTA18__GPIO_8         0x31c2
 720                         VF610_PAD_PTA19__GPIO_9         0x31c2
 721                         VF610_PAD_PTB2__GPIO_24         0x31c2
 722                         VF610_PAD_PTB3__GPIO_25         0x31c2
 723                 >;
 724         };
 725
 726         pinctrl_pca9554_22: pinctrl-pca95540-22 {
 727                 fsl,pins = <
 728                         VF610_PAD_PTB28__GPIO_98        0x219d
 729                 >;
 730         };
 731
 732         pinctrl_pwm0: pwm0grp {
 733                 fsl,pins = <
 734                         VF610_PAD_PTB0__FTM0_CH0        0x1582
 735                         VF610_PAD_PTB1__FTM0_CH1        0x1582
 736                         VF610_PAD_PTB2__FTM0_CH2        0x1582
 737                         VF610_PAD_PTB3__FTM0_CH3        0x1582
 738                 >;
 739         };
 740
 741         pinctrl_qspi0: qspi0grp {
 742                 fsl,pins = <
 743                         VF610_PAD_PTD7__QSPI0_B_QSCK    0x31c3
 744                         VF610_PAD_PTD8__QSPI0_B_CS0     0x31ff
 745                         VF610_PAD_PTD9__QSPI0_B_DATA3   0x31c3
 746                         VF610_PAD_PTD10__QSPI0_B_DATA2  0x31c3
 747                         VF610_PAD_PTD11__QSPI0_B_DATA1  0x31c3
 748                         VF610_PAD_PTD12__QSPI0_B_DATA0  0x31c3
 749                 >;
 750         };
 751
 752         pinctrl_uart0: uart0grp {
 753                 fsl,pins = <
 754                         VF610_PAD_PTB10__UART0_TX       0x21a2
 755                         VF610_PAD_PTB11__UART0_RX       0x21a1
 756                 >;
 757         };
 758
 759         pinctrl_uart1: uart1grp {
 760                 fsl,pins = <
 761                         VF610_PAD_PTB23__UART1_TX       0x21a2
 762                         VF610_PAD_PTB24__UART1_RX       0x21a1
 763                 >;
 764         };
 765
 766         pinctrl_uart2: uart2grp {
 767                 fsl,pins = <
 768                         VF610_PAD_PTD0__UART2_TX        0x21a2
 769                         VF610_PAD_PTD1__UART2_RX        0x21a1
 770                 >;
 771         };
 772
 773         pinctrl_usb_vbus: pinctrl-usb-vbus {
 774                 fsl,pins = <
 775                         VF610_PAD_PTA16__GPIO_6 0x31c2
 776                 >;
 777         };
 778
 779         pinctrl_usb0_host: usb0-host-grp {
 780                 fsl,pins = <
 781                         VF610_PAD_PTD6__GPIO_85         0x0062
 782                 >;
 783         };
 784 };