2 * Copyright (C) 2016 ARM Ltd.
3 * based on the Allwinner H3 dtsi:
4 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
45 #include <dt-bindings/clock/sun50i-a64-ccu.h>
46 #include <dt-bindings/clock/sun8i-de2.h>
47 #include <dt-bindings/clock/sun8i-r-ccu.h>
48 #include <dt-bindings/interrupt-controller/arm-gic.h>
49 #include <dt-bindings/reset/sun50i-a64-ccu.h>
50 #include <dt-bindings/reset/sun8i-de2.h>
51 #include <dt-bindings/reset/sun8i-r-ccu.h>
54 interrupt-parent = <&gic>;
63 simplefb_lcd: framebuffer-lcd {
64 compatible = "allwinner,simple-framebuffer",
66 allwinner,pipeline = "mixer0-lcd0";
67 clocks = <&ccu CLK_TCON0>,
68 <&display_clocks CLK_MIXER0>;
72 simplefb_hdmi: framebuffer-hdmi {
73 compatible = "allwinner,simple-framebuffer",
75 allwinner,pipeline = "mixer1-lcd1-hdmi";
76 clocks = <&display_clocks CLK_MIXER1>,
77 <&ccu CLK_TCON1>, <&ccu CLK_HDMI>;
87 compatible = "arm,cortex-a53", "arm,armv8";
90 enable-method = "psci";
91 next-level-cache = <&L2>;
95 compatible = "arm,cortex-a53", "arm,armv8";
98 enable-method = "psci";
99 next-level-cache = <&L2>;
103 compatible = "arm,cortex-a53", "arm,armv8";
106 enable-method = "psci";
107 next-level-cache = <&L2>;
111 compatible = "arm,cortex-a53", "arm,armv8";
114 enable-method = "psci";
115 next-level-cache = <&L2>;
119 compatible = "cache";
125 compatible = "allwinner,sun50i-a64-display-engine";
126 allwinner,pipelines = <&mixer0>,
133 compatible = "fixed-clock";
134 clock-frequency = <24000000>;
135 clock-output-names = "osc24M";
140 compatible = "fixed-clock";
141 clock-frequency = <32768>;
142 clock-output-names = "osc32k";
145 iosc: internal-osc-clk {
147 compatible = "fixed-clock";
148 clock-frequency = <16000000>;
149 clock-accuracy = <300000000>;
150 clock-output-names = "iosc";
154 compatible = "arm,psci-0.2";
159 compatible = "simple-audio-card";
160 simple-audio-card,name = "On-board SPDIF";
162 simple-audio-card,cpu {
163 sound-dai = <&spdif>;
166 simple-audio-card,codec {
167 sound-dai = <&spdif_out>;
171 spdif_out: spdif-out {
172 #sound-dai-cells = <0>;
173 compatible = "linux,spdif-dit";
177 compatible = "arm,armv8-timer";
178 interrupts = <GIC_PPI 13
179 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
181 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
183 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
185 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
189 compatible = "simple-bus";
190 #address-cells = <1>;
195 compatible = "allwinner,sun50i-a64-de2";
196 reg = <0x1000000 0x400000>;
197 allwinner,sram = <&de2_sram 1>;
198 #address-cells = <1>;
200 ranges = <0 0x1000000 0x400000>;
202 display_clocks: clock@0 {
203 compatible = "allwinner,sun50i-a64-de2-clk";
204 reg = <0x0 0x100000>;
205 clocks = <&ccu CLK_DE>,
209 resets = <&ccu RST_BUS_DE>;
214 mixer0: mixer@100000 {
215 compatible = "allwinner,sun50i-a64-de2-mixer-0";
216 reg = <0x100000 0x100000>;
217 clocks = <&display_clocks CLK_BUS_MIXER0>,
218 <&display_clocks CLK_MIXER0>;
221 resets = <&display_clocks RST_MIXER0>;
224 #address-cells = <1>;
230 mixer0_out_tcon0: endpoint {
231 remote-endpoint = <&tcon0_in_mixer0>;
237 mixer1: mixer@200000 {
238 compatible = "allwinner,sun50i-a64-de2-mixer-1";
239 reg = <0x200000 0x100000>;
240 clocks = <&display_clocks CLK_BUS_MIXER1>,
241 <&display_clocks CLK_MIXER1>;
244 resets = <&display_clocks RST_MIXER1>;
247 #address-cells = <1>;
253 mixer1_out_tcon1: endpoint {
254 remote-endpoint = <&tcon1_in_mixer1>;
261 syscon: syscon@1c00000 {
262 compatible = "allwinner,sun50i-a64-system-control";
263 reg = <0x01c00000 0x1000>;
264 #address-cells = <1>;
269 compatible = "mmio-sram";
270 reg = <0x00018000 0x28000>;
271 #address-cells = <1>;
273 ranges = <0 0x00018000 0x28000>;
275 de2_sram: sram-section@0 {
276 compatible = "allwinner,sun50i-a64-sram-c";
277 reg = <0x0000 0x28000>;
282 dma: dma-controller@1c02000 {
283 compatible = "allwinner,sun50i-a64-dma";
284 reg = <0x01c02000 0x1000>;
285 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
286 clocks = <&ccu CLK_BUS_DMA>;
289 resets = <&ccu RST_BUS_DMA>;
293 tcon0: lcd-controller@1c0c000 {
294 compatible = "allwinner,sun50i-a64-tcon-lcd",
295 "allwinner,sun8i-a83t-tcon-lcd";
296 reg = <0x01c0c000 0x1000>;
297 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
298 clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
299 clock-names = "ahb", "tcon-ch0";
300 clock-output-names = "tcon-pixel-clock";
301 resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>;
302 reset-names = "lcd", "lvds";
305 #address-cells = <1>;
309 #address-cells = <1>;
313 tcon0_in_mixer0: endpoint@0 {
315 remote-endpoint = <&mixer0_out_tcon0>;
320 #address-cells = <1>;
327 tcon1: lcd-controller@1c0d000 {
328 compatible = "allwinner,sun50i-a64-tcon-tv",
329 "allwinner,sun8i-a83t-tcon-tv";
330 reg = <0x01c0d000 0x1000>;
331 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
332 clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>;
333 clock-names = "ahb", "tcon-ch1";
334 resets = <&ccu RST_BUS_TCON1>;
338 #address-cells = <1>;
344 tcon1_in_mixer1: endpoint {
345 remote-endpoint = <&mixer1_out_tcon1>;
350 #address-cells = <1>;
354 tcon1_out_hdmi: endpoint@1 {
356 remote-endpoint = <&hdmi_in_tcon1>;
363 compatible = "allwinner,sun50i-a64-mmc";
364 reg = <0x01c0f000 0x1000>;
365 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
366 clock-names = "ahb", "mmc";
367 resets = <&ccu RST_BUS_MMC0>;
369 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
370 max-frequency = <150000000>;
372 #address-cells = <1>;
377 compatible = "allwinner,sun50i-a64-mmc";
378 reg = <0x01c10000 0x1000>;
379 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
380 clock-names = "ahb", "mmc";
381 resets = <&ccu RST_BUS_MMC1>;
383 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
384 max-frequency = <150000000>;
386 #address-cells = <1>;
391 compatible = "allwinner,sun50i-a64-emmc";
392 reg = <0x01c11000 0x1000>;
393 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
394 clock-names = "ahb", "mmc";
395 resets = <&ccu RST_BUS_MMC2>;
397 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
398 max-frequency = <200000000>;
400 #address-cells = <1>;
404 sid: eeprom@1c14000 {
405 compatible = "allwinner,sun50i-a64-sid";
406 reg = <0x1c14000 0x400>;
409 usb_otg: usb@1c19000 {
410 compatible = "allwinner,sun8i-a33-musb";
411 reg = <0x01c19000 0x0400>;
412 clocks = <&ccu CLK_BUS_OTG>;
413 resets = <&ccu RST_BUS_OTG>;
414 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
415 interrupt-names = "mc";
418 extcon = <&usbphy 0>;
422 usbphy: phy@1c19400 {
423 compatible = "allwinner,sun50i-a64-usb-phy";
424 reg = <0x01c19400 0x14>,
427 reg-names = "phy_ctrl",
430 clocks = <&ccu CLK_USB_PHY0>,
432 clock-names = "usb0_phy",
434 resets = <&ccu RST_USB_PHY0>,
436 reset-names = "usb0_reset",
443 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
444 reg = <0x01c1a000 0x100>;
445 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
446 clocks = <&ccu CLK_BUS_OHCI0>,
447 <&ccu CLK_BUS_EHCI0>,
448 <&ccu CLK_USB_OHCI0>;
449 resets = <&ccu RST_BUS_OHCI0>,
450 <&ccu RST_BUS_EHCI0>;
455 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
456 reg = <0x01c1a400 0x100>;
457 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
458 clocks = <&ccu CLK_BUS_OHCI0>,
459 <&ccu CLK_USB_OHCI0>;
460 resets = <&ccu RST_BUS_OHCI0>;
465 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
466 reg = <0x01c1b000 0x100>;
467 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
468 clocks = <&ccu CLK_BUS_OHCI1>,
469 <&ccu CLK_BUS_EHCI1>,
470 <&ccu CLK_USB_OHCI1>;
471 resets = <&ccu RST_BUS_OHCI1>,
472 <&ccu RST_BUS_EHCI1>;
479 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
480 reg = <0x01c1b400 0x100>;
481 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
482 clocks = <&ccu CLK_BUS_OHCI1>,
483 <&ccu CLK_USB_OHCI1>;
484 resets = <&ccu RST_BUS_OHCI1>;
491 compatible = "allwinner,sun50i-a64-ccu";
492 reg = <0x01c20000 0x400>;
493 clocks = <&osc24M>, <&osc32k>;
494 clock-names = "hosc", "losc";
499 pio: pinctrl@1c20800 {
500 compatible = "allwinner,sun50i-a64-pinctrl";
501 reg = <0x01c20800 0x400>;
502 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
503 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
504 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
508 interrupt-controller;
509 #interrupt-cells = <3>;
511 i2c0_pins: i2c0_pins {
516 i2c1_pins: i2c1_pins {
521 mmc0_pins: mmc0-pins {
522 pins = "PF0", "PF1", "PF2", "PF3",
525 drive-strength = <30>;
529 mmc1_pins: mmc1-pins {
530 pins = "PG0", "PG1", "PG2", "PG3",
533 drive-strength = <30>;
537 mmc2_pins: mmc2-pins {
538 pins = "PC5", "PC6", "PC8", "PC9",
539 "PC10","PC11", "PC12", "PC13",
540 "PC14", "PC15", "PC16";
542 drive-strength = <30>;
546 mmc2_ds_pin: mmc2-ds-pin {
549 drive-strength = <30>;
558 rmii_pins: rmii_pins {
559 pins = "PD10", "PD11", "PD13", "PD14", "PD17",
560 "PD18", "PD19", "PD20", "PD22", "PD23";
562 drive-strength = <40>;
565 rgmii_pins: rgmii_pins {
566 pins = "PD8", "PD9", "PD10", "PD11", "PD12",
567 "PD13", "PD15", "PD16", "PD17", "PD18",
568 "PD19", "PD20", "PD21", "PD22", "PD23";
570 drive-strength = <40>;
573 spdif_tx_pin: spdif {
579 pins = "PC0", "PC1", "PC2", "PC3";
584 pins = "PD0", "PD1", "PD2", "PD3";
588 uart0_pb_pins: uart0-pb-pins {
593 uart1_pins: uart1_pins {
598 uart1_rts_cts_pins: uart1_rts_cts_pins {
603 uart2_pins: uart2-pins {
608 uart3_pins: uart3-pins {
613 uart4_pins: uart4-pins {
618 uart4_rts_cts_pins: uart4-rts-cts-pins {
624 spdif: spdif@1c21000 {
625 #sound-dai-cells = <0>;
626 compatible = "allwinner,sun50i-a64-spdif",
627 "allwinner,sun8i-h3-spdif";
628 reg = <0x01c21000 0x400>;
629 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
630 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
631 resets = <&ccu RST_BUS_SPDIF>;
632 clock-names = "apb", "spdif";
635 pinctrl-names = "default";
636 pinctrl-0 = <&spdif_tx_pin>;
641 #sound-dai-cells = <0>;
642 compatible = "allwinner,sun50i-a64-i2s",
643 "allwinner,sun8i-h3-i2s";
644 reg = <0x01c22000 0x400>;
645 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
646 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
647 clock-names = "apb", "mod";
648 resets = <&ccu RST_BUS_I2S0>;
649 dma-names = "rx", "tx";
650 dmas = <&dma 3>, <&dma 3>;
655 #sound-dai-cells = <0>;
656 compatible = "allwinner,sun50i-a64-i2s",
657 "allwinner,sun8i-h3-i2s";
658 reg = <0x01c22400 0x400>;
659 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
660 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
661 clock-names = "apb", "mod";
662 resets = <&ccu RST_BUS_I2S1>;
663 dma-names = "rx", "tx";
664 dmas = <&dma 4>, <&dma 4>;
668 uart0: serial@1c28000 {
669 compatible = "snps,dw-apb-uart";
670 reg = <0x01c28000 0x400>;
671 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
674 clocks = <&ccu CLK_BUS_UART0>;
675 resets = <&ccu RST_BUS_UART0>;
679 uart1: serial@1c28400 {
680 compatible = "snps,dw-apb-uart";
681 reg = <0x01c28400 0x400>;
682 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
685 clocks = <&ccu CLK_BUS_UART1>;
686 resets = <&ccu RST_BUS_UART1>;
690 uart2: serial@1c28800 {
691 compatible = "snps,dw-apb-uart";
692 reg = <0x01c28800 0x400>;
693 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
696 clocks = <&ccu CLK_BUS_UART2>;
697 resets = <&ccu RST_BUS_UART2>;
701 uart3: serial@1c28c00 {
702 compatible = "snps,dw-apb-uart";
703 reg = <0x01c28c00 0x400>;
704 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
707 clocks = <&ccu CLK_BUS_UART3>;
708 resets = <&ccu RST_BUS_UART3>;
712 uart4: serial@1c29000 {
713 compatible = "snps,dw-apb-uart";
714 reg = <0x01c29000 0x400>;
715 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
718 clocks = <&ccu CLK_BUS_UART4>;
719 resets = <&ccu RST_BUS_UART4>;
724 compatible = "allwinner,sun6i-a31-i2c";
725 reg = <0x01c2ac00 0x400>;
726 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
727 clocks = <&ccu CLK_BUS_I2C0>;
728 resets = <&ccu RST_BUS_I2C0>;
730 #address-cells = <1>;
735 compatible = "allwinner,sun6i-a31-i2c";
736 reg = <0x01c2b000 0x400>;
737 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
738 clocks = <&ccu CLK_BUS_I2C1>;
739 resets = <&ccu RST_BUS_I2C1>;
741 #address-cells = <1>;
746 compatible = "allwinner,sun6i-a31-i2c";
747 reg = <0x01c2b400 0x400>;
748 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
749 clocks = <&ccu CLK_BUS_I2C2>;
750 resets = <&ccu RST_BUS_I2C2>;
752 #address-cells = <1>;
758 compatible = "allwinner,sun8i-h3-spi";
759 reg = <0x01c68000 0x1000>;
760 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
761 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
762 clock-names = "ahb", "mod";
763 dmas = <&dma 23>, <&dma 23>;
764 dma-names = "rx", "tx";
765 pinctrl-names = "default";
766 pinctrl-0 = <&spi0_pins>;
767 resets = <&ccu RST_BUS_SPI0>;
770 #address-cells = <1>;
775 compatible = "allwinner,sun8i-h3-spi";
776 reg = <0x01c69000 0x1000>;
777 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
778 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
779 clock-names = "ahb", "mod";
780 dmas = <&dma 24>, <&dma 24>;
781 dma-names = "rx", "tx";
782 pinctrl-names = "default";
783 pinctrl-0 = <&spi1_pins>;
784 resets = <&ccu RST_BUS_SPI1>;
787 #address-cells = <1>;
791 emac: ethernet@1c30000 {
792 compatible = "allwinner,sun50i-a64-emac";
794 reg = <0x01c30000 0x10000>;
795 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
796 interrupt-names = "macirq";
797 resets = <&ccu RST_BUS_EMAC>;
798 reset-names = "stmmaceth";
799 clocks = <&ccu CLK_BUS_EMAC>;
800 clock-names = "stmmaceth";
804 compatible = "snps,dwmac-mdio";
805 #address-cells = <1>;
810 gic: interrupt-controller@1c81000 {
811 compatible = "arm,gic-400";
812 reg = <0x01c81000 0x1000>,
816 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
817 interrupt-controller;
818 #interrupt-cells = <3>;
822 compatible = "allwinner,sun50i-a64-pwm",
823 "allwinner,sun5i-a13-pwm";
824 reg = <0x01c21400 0x400>;
826 pinctrl-names = "default";
827 pinctrl-0 = <&pwm_pin>;
833 compatible = "allwinner,sun50i-a64-dw-hdmi",
834 "allwinner,sun8i-a83t-dw-hdmi";
835 reg = <0x01ee0000 0x10000>;
837 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
838 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
840 clock-names = "iahb", "isfr", "tmds";
841 resets = <&ccu RST_BUS_HDMI1>;
842 reset-names = "ctrl";
844 phy-names = "hdmi-phy";
848 #address-cells = <1>;
854 hdmi_in_tcon1: endpoint {
855 remote-endpoint = <&tcon1_out_hdmi>;
865 hdmi_phy: hdmi-phy@1ef0000 {
866 compatible = "allwinner,sun50i-a64-hdmi-phy";
867 reg = <0x01ef0000 0x10000>;
868 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
870 clock-names = "bus", "mod", "pll-0";
871 resets = <&ccu RST_BUS_HDMI0>;
877 compatible = "allwinner,sun6i-a31-rtc";
878 reg = <0x01f00000 0x54>;
879 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
880 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
881 clock-output-names = "rtc-osc32k", "rtc-osc32k-out";
886 r_intc: interrupt-controller@1f00c00 {
887 compatible = "allwinner,sun50i-a64-r-intc",
888 "allwinner,sun6i-a31-r-intc";
889 interrupt-controller;
890 #interrupt-cells = <2>;
891 reg = <0x01f00c00 0x400>;
892 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
895 r_ccu: clock@1f01400 {
896 compatible = "allwinner,sun50i-a64-r-ccu";
897 reg = <0x01f01400 0x100>;
898 clocks = <&osc24M>, <&osc32k>, <&iosc>,
900 clock-names = "hosc", "losc", "iosc", "pll-periph";
906 compatible = "allwinner,sun50i-a64-i2c",
907 "allwinner,sun6i-a31-i2c";
908 reg = <0x01f02400 0x400>;
909 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
910 clocks = <&r_ccu CLK_APB0_I2C>;
911 resets = <&r_ccu RST_APB0_I2C>;
913 #address-cells = <1>;
918 compatible = "allwinner,sun50i-a64-pwm",
919 "allwinner,sun5i-a13-pwm";
920 reg = <0x01f03800 0x400>;
922 pinctrl-names = "default";
923 pinctrl-0 = <&r_pwm_pin>;
928 r_pio: pinctrl@1f02c00 {
929 compatible = "allwinner,sun50i-a64-r-pinctrl";
930 reg = <0x01f02c00 0x400>;
931 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
932 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
933 clock-names = "apb", "hosc", "losc";
936 interrupt-controller;
937 #interrupt-cells = <3>;
939 r_i2c_pl89_pins: r-i2c-pl89-pins {
956 compatible = "allwinner,sun8i-a23-rsb";
957 reg = <0x01f03400 0x400>;
958 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
960 clock-frequency = <3000000>;
962 pinctrl-names = "default";
963 pinctrl-0 = <&r_rsb_pins>;
965 #address-cells = <1>;
969 wdt0: watchdog@1c20ca0 {
970 compatible = "allwinner,sun50i-a64-wdt",
971 "allwinner,sun6i-a31-wdt";
972 reg = <0x01c20ca0 0x20>;
973 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;