sys/gnu/dts/arm64/allwinner/sun50i-h6.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ or MIT)
   2 /*
   3  * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
   4  */
   5
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/clock/sun50i-h6-ccu.h>
   8 #include <dt-bindings/clock/sun50i-h6-r-ccu.h>
   9 #include <dt-bindings/clock/sun8i-de2.h>
  10 #include <dt-bindings/clock/sun8i-tcon-top.h>
  11 #include <dt-bindings/reset/sun50i-h6-ccu.h>
  12 #include <dt-bindings/reset/sun50i-h6-r-ccu.h>
  13 #include <dt-bindings/reset/sun8i-de2.h>
  14
  15 / {
  16         interrupt-parent = <&gic>;
  17         #address-cells = <1>;
  18         #size-cells = <1>;
  19
  20         cpus {
  21                 #address-cells = <1>;
  22                 #size-cells = <0>;
  23
  24                 cpu0: cpu@0 {
  25                         compatible = "arm,cortex-a53";
  26                         device_type = "cpu";
  27                         reg = <0>;
  28                         enable-method = "psci";
  29                 };
  30
  31                 cpu1: cpu@1 {
  32                         compatible = "arm,cortex-a53";
  33                         device_type = "cpu";
  34                         reg = <1>;
  35                         enable-method = "psci";
  36                 };
  37
  38                 cpu2: cpu@2 {
  39                         compatible = "arm,cortex-a53";
  40                         device_type = "cpu";
  41                         reg = <2>;
  42                         enable-method = "psci";
  43                 };
  44
  45                 cpu3: cpu@3 {
  46                         compatible = "arm,cortex-a53";
  47                         device_type = "cpu";
  48                         reg = <3>;
  49                         enable-method = "psci";
  50                 };
  51         };
  52
  53         de: display-engine {
  54                 compatible = "allwinner,sun50i-h6-display-engine";
  55                 allwinner,pipelines = <&mixer0>;
  56                 status = "disabled";
  57         };
  58
  59         osc24M: osc24M_clk {
  60                 #clock-cells = <0>;
  61                 compatible = "fixed-clock";
  62                 clock-frequency = <24000000>;
  63                 clock-output-names = "osc24M";
  64         };
  65
  66         ext_osc32k: ext_osc32k_clk {
  67                 #clock-cells = <0>;
  68                 compatible = "fixed-clock";
  69                 clock-frequency = <32768>;
  70                 clock-output-names = "ext_osc32k";
  71         };
  72
  73         psci {
  74                 compatible = "arm,psci-0.2";
  75                 method = "smc";
  76         };
  77
  78         timer {
  79                 compatible = "arm,armv8-timer";
  80                 interrupts = <GIC_PPI 13
  81                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  82                              <GIC_PPI 14
  83                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  84                              <GIC_PPI 11
  85                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  86                              <GIC_PPI 10
  87                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  88         };
  89
  90         soc {
  91                 compatible = "simple-bus";
  92                 #address-cells = <1>;
  93                 #size-cells = <1>;
  94                 ranges;
  95
  96                 bus@1000000 {
  97                         compatible = "allwinner,sun50i-h6-de3",
  98                                      "allwinner,sun50i-a64-de2";
  99                         reg = <0x1000000 0x400000>;
 100                         allwinner,sram = <&de2_sram 1>;
 101                         #address-cells = <1>;
 102                         #size-cells = <1>;
 103                         ranges = <0 0x1000000 0x400000>;
 104
 105                         display_clocks: clock@0 {
 106                                 compatible = "allwinner,sun50i-h6-de3-clk";
 107                                 reg = <0x0 0x10000>;
 108                                 clocks = <&ccu CLK_DE>,
 109                                          <&ccu CLK_BUS_DE>;
 110                                 clock-names = "mod",
 111                                               "bus";
 112                                 resets = <&ccu RST_BUS_DE>;
 113                                 #clock-cells = <1>;
 114                                 #reset-cells = <1>;
 115                         };
 116
 117                         mixer0: mixer@100000 {
 118                                 compatible = "allwinner,sun50i-h6-de3-mixer-0";
 119                                 reg = <0x100000 0x100000>;
 120                                 clocks = <&display_clocks CLK_BUS_MIXER0>,
 121                                          <&display_clocks CLK_MIXER0>;
 122                                 clock-names = "bus",
 123                                               "mod";
 124                                 resets = <&display_clocks RST_MIXER0>;
 125
 126                                 ports {
 127                                         #address-cells = <1>;
 128                                         #size-cells = <0>;
 129
 130                                         mixer0_out: port@1 {
 131                                                 reg = <1>;
 132
 133                                                 mixer0_out_tcon_top_mixer0: endpoint {
 134                                                         remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
 135                                                 };
 136                                         };
 137                                 };
 138                         };
 139                 };
 140
 141                 video-codec@1c0e000 {
 142                         compatible = "allwinner,sun50i-h6-video-engine";
 143                         reg = <0x01c0e000 0x2000>;
 144                         clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
 145                                  <&ccu CLK_MBUS_VE>;
 146                         clock-names = "ahb", "mod", "ram";
 147                         resets = <&ccu RST_BUS_VE>;
 148                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 149                         allwinner,sram = <&ve_sram 1>;
 150                 };
 151
 152                 syscon: syscon@3000000 {
 153                         compatible = "allwinner,sun50i-h6-system-control",
 154                                      "allwinner,sun50i-a64-system-control";
 155                         reg = <0x03000000 0x1000>;
 156                         #address-cells = <1>;
 157                         #size-cells = <1>;
 158                         ranges;
 159
 160                         sram_c: sram@28000 {
 161                                 compatible = "mmio-sram";
 162                                 reg = <0x00028000 0x1e000>;
 163                                 #address-cells = <1>;
 164                                 #size-cells = <1>;
 165                                 ranges = <0 0x00028000 0x1e000>;
 166
 167                                 de2_sram: sram-section@0 {
 168                                         compatible = "allwinner,sun50i-h6-sram-c",
 169                                                      "allwinner,sun50i-a64-sram-c";
 170                                         reg = <0x0000 0x1e000>;
 171                                 };
 172                         };
 173
 174                         sram_c1: sram@1a00000 {
 175                                 compatible = "mmio-sram";
 176                                 reg = <0x01a00000 0x200000>;
 177                                 #address-cells = <1>;
 178                                 #size-cells = <1>;
 179                                 ranges = <0 0x01a00000 0x200000>;
 180
 181                                 ve_sram: sram-section@0 {
 182                                         compatible = "allwinner,sun50i-h6-sram-c1",
 183                                                      "allwinner,sun4i-a10-sram-c1";
 184                                         reg = <0x000000 0x200000>;
 185                                 };
 186                         };
 187                 };
 188
 189                 ccu: clock@3001000 {
 190                         compatible = "allwinner,sun50i-h6-ccu";
 191                         reg = <0x03001000 0x1000>;
 192                         clocks = <&osc24M>, <&rtc 0>, <&rtc 2>;
 193                         clock-names = "hosc", "losc", "iosc";
 194                         #clock-cells = <1>;
 195                         #reset-cells = <1>;
 196                 };
 197
 198                 dma: dma-controller@3002000 {
 199                         compatible = "allwinner,sun50i-h6-dma";
 200                         reg = <0x03002000 0x1000>;
 201                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 202                         clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>;
 203                         clock-names = "bus", "mbus";
 204                         dma-channels = <16>;
 205                         dma-requests = <46>;
 206                         resets = <&ccu RST_BUS_DMA>;
 207                         #dma-cells = <1>;
 208                 };
 209
 210                 sid: efuse@3006000 {
 211                         compatible = "allwinner,sun50i-h6-sid";
 212                         reg = <0x03006000 0x400>;
 213                 };
 214
 215                 watchdog: watchdog@30090a0 {
 216                         compatible = "allwinner,sun50i-h6-wdt",
 217                                      "allwinner,sun6i-a31-wdt";
 218                         reg = <0x030090a0 0x20>;
 219                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 220                         clocks = <&osc24M>;
 221                         /* Broken on some H6 boards */
 222                         status = "disabled";
 223                 };
 224
 225                 pio: pinctrl@300b000 {
 226                         compatible = "allwinner,sun50i-h6-pinctrl";
 227                         reg = <0x0300b000 0x400>;
 228                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
 229                                      <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
 230                                      <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 231                                      <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 232                         clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc 0>;
 233                         clock-names = "apb", "hosc", "losc";
 234                         gpio-controller;
 235                         #gpio-cells = <3>;
 236                         interrupt-controller;
 237                         #interrupt-cells = <3>;
 238
 239                         ext_rgmii_pins: rgmii-pins {
 240                                 pins = "PD0", "PD1", "PD2", "PD3", "PD4",
 241                                        "PD5", "PD7", "PD8", "PD9", "PD10",
 242                                        "PD11", "PD12", "PD13", "PD19", "PD20";
 243                                 function = "emac";
 244                                 drive-strength = <40>;
 245                         };
 246
 247                         hdmi_pins: hdmi-pins {
 248                                 pins = "PH8", "PH9", "PH10";
 249                                 function = "hdmi";
 250                         };
 251
 252                         i2c0_pins: i2c0-pins {
 253                                 pins = "PD25", "PD26";
 254                                 function = "i2c0";
 255                         };
 256
 257                         i2c1_pins: i2c1-pins {
 258                                 pins = "PH5", "PH6";
 259                                 function = "i2c1";
 260                         };
 261
 262                         i2c2_pins: i2c2-pins {
 263                                 pins = "PD23", "PD24";
 264                                 function = "i2c2";
 265                         };
 266
 267                         mmc0_pins: mmc0-pins {
 268                                 pins = "PF0", "PF1", "PF2", "PF3",
 269                                        "PF4", "PF5";
 270                                 function = "mmc0";
 271                                 drive-strength = <30>;
 272                                 bias-pull-up;
 273                         };
 274
 275                         /omit-if-no-ref/
 276                         mmc1_pins: mmc1-pins {
 277                                 pins = "PG0", "PG1", "PG2", "PG3",
 278                                        "PG4", "PG5";
 279                                 function = "mmc1";
 280                                 drive-strength = <30>;
 281                                 bias-pull-up;
 282                         };
 283
 284                         mmc2_pins: mmc2-pins {
 285                                 pins = "PC1", "PC4", "PC5", "PC6",
 286                                        "PC7", "PC8", "PC9", "PC10",
 287                                        "PC11", "PC12", "PC13", "PC14";
 288                                 function = "mmc2";
 289                                 drive-strength = <30>;
 290                                 bias-pull-up;
 291                         };
 292
 293                         spdif_tx_pin: spdif-tx-pin {
 294                                 pins = "PH7";
 295                                 function = "spdif";
 296                         };
 297
 298                         uart0_ph_pins: uart0-ph-pins {
 299                                 pins = "PH0", "PH1";
 300                                 function = "uart0";
 301                         };
 302                 };
 303
 304                 gic: interrupt-controller@3021000 {
 305                         compatible = "arm,gic-400";
 306                         reg = <0x03021000 0x1000>,
 307                               <0x03022000 0x2000>,
 308                               <0x03024000 0x2000>,
 309                               <0x03026000 0x2000>;
 310                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 311                         interrupt-controller;
 312                         #interrupt-cells = <3>;
 313                 };
 314
 315                 mmc0: mmc@4020000 {
 316                         compatible = "allwinner,sun50i-h6-mmc",
 317                                      "allwinner,sun50i-a64-mmc";
 318                         reg = <0x04020000 0x1000>;
 319                         clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
 320                         clock-names = "ahb", "mmc";
 321                         resets = <&ccu RST_BUS_MMC0>;
 322                         reset-names = "ahb";
 323                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 324                         pinctrl-names = "default";
 325                         pinctrl-0 = <&mmc0_pins>;
 326                         status = "disabled";
 327                         #address-cells = <1>;
 328                         #size-cells = <0>;
 329                 };
 330
 331                 mmc1: mmc@4021000 {
 332                         compatible = "allwinner,sun50i-h6-mmc",
 333                                      "allwinner,sun50i-a64-mmc";
 334                         reg = <0x04021000 0x1000>;
 335                         clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
 336                         clock-names = "ahb", "mmc";
 337                         resets = <&ccu RST_BUS_MMC1>;
 338                         reset-names = "ahb";
 339                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 340                         pinctrl-names = "default";
 341                         pinctrl-0 = <&mmc1_pins>;
 342                         status = "disabled";
 343                         #address-cells = <1>;
 344                         #size-cells = <0>;
 345                 };
 346
 347                 mmc2: mmc@4022000 {
 348                         compatible = "allwinner,sun50i-h6-emmc",
 349                                      "allwinner,sun50i-a64-emmc";
 350                         reg = <0x04022000 0x1000>;
 351                         clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
 352                         clock-names = "ahb", "mmc";
 353                         resets = <&ccu RST_BUS_MMC2>;
 354                         reset-names = "ahb";
 355                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 356                         pinctrl-names = "default";
 357                         pinctrl-0 = <&mmc2_pins>;
 358                         status = "disabled";
 359                         #address-cells = <1>;
 360                         #size-cells = <0>;
 361                 };
 362
 363                 uart0: serial@5000000 {
 364                         compatible = "snps,dw-apb-uart";
 365                         reg = <0x05000000 0x400>;
 366                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 367                         reg-shift = <2>;
 368                         reg-io-width = <4>;
 369                         clocks = <&ccu CLK_BUS_UART0>;
 370                         resets = <&ccu RST_BUS_UART0>;
 371                         status = "disabled";
 372                 };
 373
 374                 uart1: serial@5000400 {
 375                         compatible = "snps,dw-apb-uart";
 376                         reg = <0x05000400 0x400>;
 377                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 378                         reg-shift = <2>;
 379                         reg-io-width = <4>;
 380                         clocks = <&ccu CLK_BUS_UART1>;
 381                         resets = <&ccu RST_BUS_UART1>;
 382                         status = "disabled";
 383                 };
 384
 385                 uart2: serial@5000800 {
 386                         compatible = "snps,dw-apb-uart";
 387                         reg = <0x05000800 0x400>;
 388                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 389                         reg-shift = <2>;
 390                         reg-io-width = <4>;
 391                         clocks = <&ccu CLK_BUS_UART2>;
 392                         resets = <&ccu RST_BUS_UART2>;
 393                         status = "disabled";
 394                 };
 395
 396                 uart3: serial@5000c00 {
 397                         compatible = "snps,dw-apb-uart";
 398                         reg = <0x05000c00 0x400>;
 399                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 400                         reg-shift = <2>;
 401                         reg-io-width = <4>;
 402                         clocks = <&ccu CLK_BUS_UART3>;
 403                         resets = <&ccu RST_BUS_UART3>;
 404                         status = "disabled";
 405                 };
 406
 407                 i2c0: i2c@5002000 {
 408                         compatible = "allwinner,sun50i-h6-i2c",
 409                                      "allwinner,sun6i-a31-i2c";
 410                         reg = <0x05002000 0x400>;
 411                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 412                         clocks = <&ccu CLK_BUS_I2C0>;
 413                         resets = <&ccu RST_BUS_I2C0>;
 414                         pinctrl-names = "default";
 415                         pinctrl-0 = <&i2c0_pins>;
 416                         status = "disabled";
 417                         #address-cells = <1>;
 418                         #size-cells = <0>;
 419                 };
 420
 421                 i2c1: i2c@5002400 {
 422                         compatible = "allwinner,sun50i-h6-i2c",
 423                                      "allwinner,sun6i-a31-i2c";
 424                         reg = <0x05002400 0x400>;
 425                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 426                         clocks = <&ccu CLK_BUS_I2C1>;
 427                         resets = <&ccu RST_BUS_I2C1>;
 428                         pinctrl-names = "default";
 429                         pinctrl-0 = <&i2c1_pins>;
 430                         status = "disabled";
 431                         #address-cells = <1>;
 432                         #size-cells = <0>;
 433                 };
 434
 435                 i2c2: i2c@5002800 {
 436                         compatible = "allwinner,sun50i-h6-i2c",
 437                                      "allwinner,sun6i-a31-i2c";
 438                         reg = <0x05002800 0x400>;
 439                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 440                         clocks = <&ccu CLK_BUS_I2C2>;
 441                         resets = <&ccu RST_BUS_I2C2>;
 442                         pinctrl-names = "default";
 443                         pinctrl-0 = <&i2c2_pins>;
 444                         status = "disabled";
 445                         #address-cells = <1>;
 446                         #size-cells = <0>;
 447                 };
 448
 449                 emac: ethernet@5020000 {
 450                         compatible = "allwinner,sun50i-h6-emac",
 451                                      "allwinner,sun50i-a64-emac";
 452                         syscon = <&syscon>;
 453                         reg = <0x05020000 0x10000>;
 454                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 455                         interrupt-names = "macirq";
 456                         resets = <&ccu RST_BUS_EMAC>;
 457                         reset-names = "stmmaceth";
 458                         clocks = <&ccu CLK_BUS_EMAC>;
 459                         clock-names = "stmmaceth";
 460                         status = "disabled";
 461
 462                         mdio: mdio {
 463                                 compatible = "snps,dwmac-mdio";
 464                                 #address-cells = <1>;
 465                                 #size-cells = <0>;
 466                         };
 467                 };
 468
 469                 spdif: spdif@5093000 {
 470                         #sound-dai-cells = <0>;
 471                         compatible = "allwinner,sun50i-h6-spdif";
 472                         reg = <0x05093000 0x400>;
 473                         interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 474                         clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
 475                         clock-names = "apb", "spdif";
 476                         resets = <&ccu RST_BUS_SPDIF>;
 477                         dmas = <&dma 2>;
 478                         dma-names = "tx";
 479                         pinctrl-names = "default";
 480                         pinctrl-0 = <&spdif_tx_pin>;
 481                         status = "disabled";
 482                 };
 483
 484                 usb2otg: usb@5100000 {
 485                         compatible = "allwinner,sun50i-h6-musb",
 486                                      "allwinner,sun8i-a33-musb";
 487                         reg = <0x05100000 0x0400>;
 488                         clocks = <&ccu CLK_BUS_OTG>;
 489                         resets = <&ccu RST_BUS_OTG>;
 490                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 491                         interrupt-names = "mc";
 492                         phys = <&usb2phy 0>;
 493                         phy-names = "usb";
 494                         extcon = <&usb2phy 0>;
 495                         status = "disabled";
 496                 };
 497
 498                 usb2phy: phy@5100400 {
 499                         compatible = "allwinner,sun50i-h6-usb-phy";
 500                         reg = <0x05100400 0x24>,
 501                               <0x05101800 0x4>,
 502                               <0x05311800 0x4>;
 503                         reg-names = "phy_ctrl",
 504                                     "pmu0",
 505                                     "pmu3";
 506                         clocks = <&ccu CLK_USB_PHY0>,
 507                                  <&ccu CLK_USB_PHY3>;
 508                         clock-names = "usb0_phy",
 509                                       "usb3_phy";
 510                         resets = <&ccu RST_USB_PHY0>,
 511                                  <&ccu RST_USB_PHY3>;
 512                         reset-names = "usb0_reset",
 513                                       "usb3_reset";
 514                         status = "disabled";
 515                         #phy-cells = <1>;
 516                 };
 517
 518                 ehci0: usb@5101000 {
 519                         compatible = "allwinner,sun50i-h6-ehci", "generic-ehci";
 520                         reg = <0x05101000 0x100>;
 521                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 522                         clocks = <&ccu CLK_BUS_OHCI0>,
 523                                  <&ccu CLK_BUS_EHCI0>,
 524                                  <&ccu CLK_USB_OHCI0>;
 525                         resets = <&ccu RST_BUS_OHCI0>,
 526                                  <&ccu RST_BUS_EHCI0>;
 527                         status = "disabled";
 528                 };
 529
 530                 ohci0: usb@5101400 {
 531                         compatible = "allwinner,sun50i-h6-ohci", "generic-ohci";
 532                         reg = <0x05101400 0x100>;
 533                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 534                         clocks = <&ccu CLK_BUS_OHCI0>,
 535                                  <&ccu CLK_USB_OHCI0>;
 536                         resets = <&ccu RST_BUS_OHCI0>;
 537                         status = "disabled";
 538                 };
 539
 540                 ehci3: usb@5311000 {
 541                         compatible = "allwinner,sun50i-h6-ehci", "generic-ehci";
 542                         reg = <0x05311000 0x100>;
 543                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 544                         clocks = <&ccu CLK_BUS_OHCI3>,
 545                                  <&ccu CLK_BUS_EHCI3>,
 546                                  <&ccu CLK_USB_OHCI3>;
 547                         resets = <&ccu RST_BUS_OHCI3>,
 548                                  <&ccu RST_BUS_EHCI3>;
 549                         phys = <&usb2phy 3>;
 550                         phy-names = "usb";
 551                         status = "disabled";
 552                 };
 553
 554                 ohci3: usb@5311400 {
 555                         compatible = "allwinner,sun50i-h6-ohci", "generic-ohci";
 556                         reg = <0x05311400 0x100>;
 557                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 558                         clocks = <&ccu CLK_BUS_OHCI3>,
 559                                  <&ccu CLK_USB_OHCI3>;
 560                         resets = <&ccu RST_BUS_OHCI3>;
 561                         phys = <&usb2phy 3>;
 562                         phy-names = "usb";
 563                         status = "disabled";
 564                 };
 565
 566                 hdmi: hdmi@6000000 {
 567                         compatible = "allwinner,sun50i-h6-dw-hdmi";
 568                         reg = <0x06000000 0x10000>;
 569                         reg-io-width = <1>;
 570                         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 571                         clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>,
 572                                  <&ccu CLK_HDMI>, <&ccu CLK_HDMI_CEC>,
 573                                  <&ccu CLK_HDCP>, <&ccu CLK_BUS_HDCP>;
 574                         clock-names = "iahb", "isfr", "tmds", "cec", "hdcp",
 575                                       "hdcp-bus";
 576                         resets = <&ccu RST_BUS_HDMI_SUB>, <&ccu RST_BUS_HDCP>;
 577                         reset-names = "ctrl", "hdcp";
 578                         phys = <&hdmi_phy>;
 579                         phy-names = "phy";
 580                         pinctrl-names = "default";
 581                         pinctrl-0 = <&hdmi_pins>;
 582                         status = "disabled";
 583
 584                         ports {
 585                                 #address-cells = <1>;
 586                                 #size-cells = <0>;
 587
 588                                 hdmi_in: port@0 {
 589                                         reg = <0>;
 590
 591                                         hdmi_in_tcon_top: endpoint {
 592                                                 remote-endpoint = <&tcon_top_hdmi_out_hdmi>;
 593                                         };
 594                                 };
 595
 596                                 hdmi_out: port@1 {
 597                                         reg = <1>;
 598                                 };
 599                         };
 600                 };
 601
 602                 hdmi_phy: hdmi-phy@6010000 {
 603                         compatible = "allwinner,sun50i-h6-hdmi-phy";
 604                         reg = <0x06010000 0x10000>;
 605                         clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>;
 606                         clock-names = "bus", "mod";
 607                         resets = <&ccu RST_BUS_HDMI>;
 608                         reset-names = "phy";
 609                         #phy-cells = <0>;
 610                 };
 611
 612                 tcon_top: tcon-top@6510000 {
 613                         compatible = "allwinner,sun50i-h6-tcon-top";
 614                         reg = <0x06510000 0x1000>;
 615                         clocks = <&ccu CLK_BUS_TCON_TOP>,
 616                                  <&ccu CLK_TCON_TV0>;
 617                         clock-names = "bus",
 618                                       "tcon-tv0";
 619                         clock-output-names = "tcon-top-tv0";
 620                         resets = <&ccu RST_BUS_TCON_TOP>;
 621                         reset-names = "rst";
 622                         #clock-cells = <1>;
 623
 624                         ports {
 625                                 #address-cells = <1>;
 626                                 #size-cells = <0>;
 627
 628                                 tcon_top_mixer0_in: port@0 {
 629                                         #address-cells = <1>;
 630                                         #size-cells = <0>;
 631                                         reg = <0>;
 632
 633                                         tcon_top_mixer0_in_mixer0: endpoint@0 {
 634                                                 reg = <0>;
 635                                                 remote-endpoint = <&mixer0_out_tcon_top_mixer0>;
 636                                         };
 637                                 };
 638
 639                                 tcon_top_mixer0_out: port@1 {
 640                                         #address-cells = <1>;
 641                                         #size-cells = <0>;
 642                                         reg = <1>;
 643
 644                                         tcon_top_mixer0_out_tcon_tv: endpoint@2 {
 645                                                 reg = <2>;
 646                                                 remote-endpoint = <&tcon_tv_in_tcon_top_mixer0>;
 647                                         };
 648                                 };
 649
 650                                 tcon_top_hdmi_in: port@4 {
 651                                         #address-cells = <1>;
 652                                         #size-cells = <0>;
 653                                         reg = <4>;
 654
 655                                         tcon_top_hdmi_in_tcon_tv: endpoint@0 {
 656                                                 reg = <0>;
 657                                                 remote-endpoint = <&tcon_tv_out_tcon_top>;
 658                                         };
 659                                 };
 660
 661                                 tcon_top_hdmi_out: port@5 {
 662                                         reg = <5>;
 663
 664                                         tcon_top_hdmi_out_hdmi: endpoint {
 665                                                 remote-endpoint = <&hdmi_in_tcon_top>;
 666                                         };
 667                                 };
 668                         };
 669                 };
 670
 671                 tcon_tv: lcd-controller@6515000 {
 672                         compatible = "allwinner,sun50i-h6-tcon-tv",
 673                                      "allwinner,sun8i-r40-tcon-tv";
 674                         reg = <0x06515000 0x1000>;
 675                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 676                         clocks = <&ccu CLK_BUS_TCON_TV0>,
 677                                  <&tcon_top CLK_TCON_TOP_TV0>;
 678                         clock-names = "ahb",
 679                                       "tcon-ch1";
 680                         resets = <&ccu RST_BUS_TCON_TV0>;
 681                         reset-names = "lcd";
 682
 683                         ports {
 684                                 #address-cells = <1>;
 685                                 #size-cells = <0>;
 686
 687                                 tcon_tv_in: port@0 {
 688                                         reg = <0>;
 689
 690                                         tcon_tv_in_tcon_top_mixer0: endpoint {
 691                                                 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv>;
 692                                         };
 693                                 };
 694
 695                                 tcon_tv_out: port@1 {
 696                                         #address-cells = <1>;
 697                                         #size-cells = <0>;
 698                                         reg = <1>;
 699
 700                                         tcon_tv_out_tcon_top: endpoint@1 {
 701                                                 reg = <1>;
 702                                                 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv>;
 703                                         };
 704                                 };
 705                         };
 706                 };
 707
 708                 rtc: rtc@7000000 {
 709                         compatible = "allwinner,sun50i-h6-rtc";
 710                         reg = <0x07000000 0x400>;
 711                         interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
 712                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 713                         clock-output-names = "osc32k", "osc32k-out", "iosc";
 714                         clocks = <&ext_osc32k>;
 715                         #clock-cells = <1>;
 716                 };
 717
 718                 r_ccu: clock@7010000 {
 719                         compatible = "allwinner,sun50i-h6-r-ccu";
 720                         reg = <0x07010000 0x400>;
 721                         clocks = <&osc24M>, <&rtc 0>, <&rtc 2>,
 722                                  <&ccu CLK_PLL_PERIPH0>;
 723                         clock-names = "hosc", "losc", "iosc", "pll-periph";
 724                         #clock-cells = <1>;
 725                         #reset-cells = <1>;
 726                 };
 727
 728                 r_watchdog: watchdog@7020400 {
 729                         compatible = "allwinner,sun50i-h6-wdt",
 730                                      "allwinner,sun6i-a31-wdt";
 731                         reg = <0x07020400 0x20>;
 732                         interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 733                         clocks = <&osc24M>;
 734                 };
 735
 736                 r_intc: interrupt-controller@7021000 {
 737                         compatible = "allwinner,sun50i-h6-r-intc",
 738                                      "allwinner,sun6i-a31-r-intc";
 739                         interrupt-controller;
 740                         #interrupt-cells = <2>;
 741                         reg = <0x07021000 0x400>;
 742                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 743                 };
 744
 745                 r_pio: pinctrl@7022000 {
 746                         compatible = "allwinner,sun50i-h6-r-pinctrl";
 747                         reg = <0x07022000 0x400>;
 748                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 749                                      <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 750                         clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&rtc 0>;
 751                         clock-names = "apb", "hosc", "losc";
 752                         gpio-controller;
 753                         #gpio-cells = <3>;
 754                         interrupt-controller;
 755                         #interrupt-cells = <3>;
 756
 757                         r_i2c_pins: r-i2c-pins {
 758                                 pins = "PL0", "PL1";
 759                                 function = "s_i2c";
 760                         };
 761
 762                         r_ir_rx_pin: r-ir-rx-pin {
 763                                 pins = "PL9";
 764                                 function = "s_cir_rx";
 765                         };
 766                 };
 767
 768                 r_ir: ir@7040000 {
 769                                 compatible = "allwinner,sun50i-h6-ir",
 770                                              "allwinner,sun6i-a31-ir";
 771                                 reg = <0x07040000 0x400>;
 772                                 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
 773                                 clocks = <&r_ccu CLK_R_APB1_IR>,
 774                                          <&r_ccu CLK_IR>;
 775                                 clock-names = "apb", "ir";
 776                                 resets = <&r_ccu RST_R_APB1_IR>;
 777                                 pinctrl-names = "default";
 778                                 pinctrl-0 = <&r_ir_rx_pin>;
 779                                 status = "disabled";
 780                 };
 781
 782                 r_i2c: i2c@7081400 {
 783                         compatible = "allwinner,sun50i-h6-i2c",
 784                                      "allwinner,sun6i-a31-i2c";
 785                         reg = <0x07081400 0x400>;
 786                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 787                         clocks = <&r_ccu CLK_R_APB2_I2C>;
 788                         resets = <&r_ccu RST_R_APB2_I2C>;
 789                         pinctrl-names = "default";
 790                         pinctrl-0 = <&r_i2c_pins>;
 791                         status = "disabled";
 792                         #address-cells = <1>;
 793                         #size-cells = <0>;
 794                 };
 795         };
 796 };