1 // SPDX-License-Identifier: (GPL-2.0+ or MIT)
3 * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/sun50i-h6-ccu.h>
8 #include <dt-bindings/reset/sun50i-h6-ccu.h>
11 interrupt-parent = <&gic>;
20 compatible = "arm,cortex-a53", "arm,armv8";
23 enable-method = "psci";
27 compatible = "arm,cortex-a53", "arm,armv8";
30 enable-method = "psci";
34 compatible = "arm,cortex-a53", "arm,armv8";
37 enable-method = "psci";
41 compatible = "arm,cortex-a53", "arm,armv8";
44 enable-method = "psci";
48 iosc: internal-osc-clk {
50 compatible = "fixed-clock";
51 clock-frequency = <16000000>;
52 clock-accuracy = <300000000>;
53 clock-output-names = "iosc";
58 compatible = "fixed-clock";
59 clock-frequency = <24000000>;
60 clock-output-names = "osc24M";
65 compatible = "fixed-clock";
66 clock-frequency = <32768>;
67 clock-output-names = "osc32k";
71 compatible = "arm,psci-0.2";
76 compatible = "arm,armv8-timer";
77 interrupts = <GIC_PPI 13
78 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
80 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
82 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
84 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
88 compatible = "simple-bus";
94 compatible = "allwinner,sun50i-h6-ccu";
95 reg = <0x03001000 0x1000>;
96 clocks = <&osc24M>, <&osc32k>, <&iosc>;
97 clock-names = "hosc", "losc", "iosc";
102 gic: interrupt-controller@3021000 {
103 compatible = "arm,gic-400";
104 reg = <0x03021000 0x1000>,
108 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
109 interrupt-controller;
110 #interrupt-cells = <3>;
113 pio: pinctrl@300b000 {
114 compatible = "allwinner,sun50i-h6-pinctrl";
115 reg = <0x0300b000 0x400>;
116 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
117 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
118 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
119 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
120 clocks = <&ccu CLK_APB1>, <&osc24M>, <&osc32k>;
121 clock-names = "apb", "hosc", "losc";
124 interrupt-controller;
125 #interrupt-cells = <3>;
127 uart0_ph_pins: uart0-ph {
133 uart0: serial@5000000 {
134 compatible = "snps,dw-apb-uart";
135 reg = <0x05000000 0x400>;
136 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
139 clocks = <&ccu CLK_BUS_UART0>;
140 resets = <&ccu RST_BUS_UART0>;
144 uart1: serial@5000400 {
145 compatible = "snps,dw-apb-uart";
146 reg = <0x05000400 0x400>;
147 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
150 clocks = <&ccu CLK_BUS_UART1>;
151 resets = <&ccu RST_BUS_UART1>;
155 uart2: serial@5000800 {
156 compatible = "snps,dw-apb-uart";
157 reg = <0x05000800 0x400>;
158 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
161 clocks = <&ccu CLK_BUS_UART2>;
162 resets = <&ccu RST_BUS_UART2>;
166 uart3: serial@5000c00 {
167 compatible = "snps,dw-apb-uart";
168 reg = <0x05000c00 0x400>;
169 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
172 clocks = <&ccu CLK_BUS_UART3>;
173 resets = <&ccu RST_BUS_UART3>;
177 r_ccu: clock@7010000 {
178 compatible = "allwinner,sun50i-h6-r-ccu";
179 reg = <0x07010000 0x400>;
180 clocks = <&osc24M>, <&osc32k>, <&iosc>,
181 <&ccu CLK_PLL_PERIPH0>;
182 clock-names = "hosc", "losc", "iosc", "pll-periph";
187 r_intc: interrupt-controller@7021000 {
188 compatible = "allwinner,sun50i-h6-r-intc",
189 "allwinner,sun6i-a31-r-intc";
190 interrupt-controller;
191 #interrupt-cells = <2>;
192 reg = <0x07021000 0x400>;
193 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
196 r_pio: pinctrl@7022000 {
197 compatible = "allwinner,sun50i-h6-r-pinctrl";
198 reg = <0x07022000 0x400>;
199 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
200 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
201 clocks = <&r_ccu 2>, <&osc24M>, <&osc32k>;
202 clock-names = "apb", "hosc", "losc";
205 interrupt-controller;
206 #interrupt-cells = <3>;
215 compatible = "allwinner,sun6i-a31-i2c";
216 reg = <0x07081400 0x400>;
217 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
220 pinctrl-names = "default";
221 pinctrl-0 = <&r_i2c_pins>;
223 #address-cells = <1>;