sys/gnu/dts/arm64/amlogic/meson-axg.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
   4  */
   5
   6 #include <dt-bindings/clock/axg-aoclkc.h>
   7 #include <dt-bindings/clock/axg-audio-clkc.h>
   8 #include <dt-bindings/clock/axg-clkc.h>
   9 #include <dt-bindings/gpio/gpio.h>
  10 #include <dt-bindings/gpio/meson-axg-gpio.h>
  11 #include <dt-bindings/interrupt-controller/irq.h>
  12 #include <dt-bindings/interrupt-controller/arm-gic.h>
  13 #include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
  14 #include <dt-bindings/reset/amlogic,meson-axg-reset.h>
  15
  16 / {
  17         compatible = "amlogic,meson-axg";
  18
  19         interrupt-parent = <&gic>;
  20         #address-cells = <2>;
  21         #size-cells = <2>;
  22
  23         tdmif_a: audio-controller-0 {
  24                 compatible = "amlogic,axg-tdm-iface";
  25                 #sound-dai-cells = <0>;
  26                 sound-name-prefix = "TDM_A";
  27                 clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>,
  28                          <&clkc_audio AUD_CLKID_MST_A_SCLK>,
  29                          <&clkc_audio AUD_CLKID_MST_A_LRCLK>;
  30                 clock-names = "mclk", "sclk", "lrclk";
  31                 status = "disabled";
  32         };
  33
  34         tdmif_b: audio-controller-1 {
  35                 compatible = "amlogic,axg-tdm-iface";
  36                 #sound-dai-cells = <0>;
  37                 sound-name-prefix = "TDM_B";
  38                 clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>,
  39                          <&clkc_audio AUD_CLKID_MST_B_SCLK>,
  40                          <&clkc_audio AUD_CLKID_MST_B_LRCLK>;
  41                 clock-names = "mclk", "sclk", "lrclk";
  42                 status = "disabled";
  43         };
  44
  45         tdmif_c: audio-controller-2 {
  46                 compatible = "amlogic,axg-tdm-iface";
  47                 #sound-dai-cells = <0>;
  48                 sound-name-prefix = "TDM_C";
  49                 clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>,
  50                          <&clkc_audio AUD_CLKID_MST_C_SCLK>,
  51                          <&clkc_audio AUD_CLKID_MST_C_LRCLK>;
  52                 clock-names = "mclk", "sclk", "lrclk";
  53                 status = "disabled";
  54         };
  55
  56         arm-pmu {
  57                 compatible = "arm,cortex-a53-pmu";
  58                 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
  59                              <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
  60                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
  61                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
  62                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  63         };
  64
  65         cpus {
  66                 #address-cells = <0x2>;
  67                 #size-cells = <0x0>;
  68
  69                 cpu0: cpu@0 {
  70                         device_type = "cpu";
  71                         compatible = "arm,cortex-a53", "arm,armv8";
  72                         reg = <0x0 0x0>;
  73                         enable-method = "psci";
  74                         next-level-cache = <&l2>;
  75                         clocks = <&scpi_dvfs 0>;
  76                 };
  77
  78                 cpu1: cpu@1 {
  79                         device_type = "cpu";
  80                         compatible = "arm,cortex-a53", "arm,armv8";
  81                         reg = <0x0 0x1>;
  82                         enable-method = "psci";
  83                         next-level-cache = <&l2>;
  84                         clocks = <&scpi_dvfs 0>;
  85                 };
  86
  87                 cpu2: cpu@2 {
  88                         device_type = "cpu";
  89                         compatible = "arm,cortex-a53", "arm,armv8";
  90                         reg = <0x0 0x2>;
  91                         enable-method = "psci";
  92                         next-level-cache = <&l2>;
  93                         clocks = <&scpi_dvfs 0>;
  94                 };
  95
  96                 cpu3: cpu@3 {
  97                         device_type = "cpu";
  98                         compatible = "arm,cortex-a53", "arm,armv8";
  99                         reg = <0x0 0x3>;
 100                         enable-method = "psci";
 101                         next-level-cache = <&l2>;
 102                         clocks = <&scpi_dvfs 0>;
 103                 };
 104
 105                 l2: l2-cache0 {
 106                         compatible = "cache";
 107                 };
 108         };
 109
 110         sm: secure-monitor {
 111                 compatible = "amlogic,meson-gxbb-sm";
 112         };
 113
 114         psci {
 115                 compatible = "arm,psci-1.0";
 116                 method = "smc";
 117         };
 118
 119         reserved-memory {
 120                 #address-cells = <2>;
 121                 #size-cells = <2>;
 122                 ranges;
 123
 124                 /* 16 MiB reserved for Hardware ROM Firmware */
 125                 hwrom_reserved: hwrom@0 {
 126                         reg = <0x0 0x0 0x0 0x1000000>;
 127                         no-map;
 128                 };
 129
 130                 /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
 131                 secmon_reserved: secmon@5000000 {
 132                         reg = <0x0 0x05000000 0x0 0x300000>;
 133                         no-map;
 134                 };
 135         };
 136
 137         scpi {
 138                 compatible = "arm,scpi-pre-1.0";
 139                 mboxes = <&mailbox 1 &mailbox 2>;
 140                 shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
 141
 142                 scpi_clocks: clocks {
 143                         compatible = "arm,scpi-clocks";
 144
 145                         scpi_dvfs: clock-controller {
 146                                 compatible = "arm,scpi-dvfs-clocks";
 147                                 #clock-cells = <1>;
 148                                 clock-indices = <0>;
 149                                 clock-output-names = "vcpu";
 150                         };
 151                 };
 152
 153                 scpi_sensors: sensors {
 154                         compatible = "amlogic,meson-gxbb-scpi-sensors";
 155                         #thermal-sensor-cells = <1>;
 156                 };
 157         };
 158
 159         soc {
 160                 compatible = "simple-bus";
 161                 #address-cells = <2>;
 162                 #size-cells = <2>;
 163                 ranges;
 164
 165                 ethmac: ethernet@ff3f0000 {
 166                         compatible = "amlogic,meson-axg-dwmac", "snps,dwmac";
 167                         reg = <0x0 0xff3f0000 0x0 0x10000
 168                                0x0 0xff634540 0x0 0x8>;
 169                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 170                         interrupt-names = "macirq";
 171                         clocks = <&clkc CLKID_ETH>,
 172                                  <&clkc CLKID_FCLK_DIV2>,
 173                                  <&clkc CLKID_MPLL2>;
 174                         clock-names = "stmmaceth", "clkin0", "clkin1";
 175                         status = "disabled";
 176                 };
 177
 178                 pdm: audio-controller@ff632000 {
 179                         compatible = "amlogic,axg-pdm";
 180                         reg = <0x0 0xff632000 0x0 0x34>;
 181                         #sound-dai-cells = <0>;
 182                         sound-name-prefix = "PDM";
 183                         clocks = <&clkc_audio AUD_CLKID_PDM>,
 184                                  <&clkc_audio AUD_CLKID_PDM_DCLK>,
 185                                  <&clkc_audio AUD_CLKID_PDM_SYSCLK>;
 186                         clock-names = "pclk", "dclk", "sysclk";
 187                         status = "disabled";
 188                 };
 189
 190                 periphs: bus@ff634000 {
 191                         compatible = "simple-bus";
 192                         reg = <0x0 0xff634000 0x0 0x2000>;
 193                         #address-cells = <2>;
 194                         #size-cells = <2>;
 195                         ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>;
 196
 197                         hwrng: rng@18 {
 198                                 compatible = "amlogic,meson-rng";
 199                                 reg = <0x0 0x18 0x0 0x4>;
 200                                 clocks = <&clkc CLKID_RNG0>;
 201                                 clock-names = "core";
 202                         };
 203
 204                         pinctrl_periphs: pinctrl@480 {
 205                                 compatible = "amlogic,meson-axg-periphs-pinctrl";
 206                                 #address-cells = <2>;
 207                                 #size-cells = <2>;
 208                                 ranges;
 209
 210                                 gpio: bank@480 {
 211                                         reg = <0x0 0x00480 0x0 0x40>,
 212                                               <0x0 0x004e8 0x0 0x14>,
 213                                               <0x0 0x00520 0x0 0x14>,
 214                                               <0x0 0x00430 0x0 0x3c>;
 215                                         reg-names = "mux", "pull", "pull-enable", "gpio";
 216                                         gpio-controller;
 217                                         #gpio-cells = <2>;
 218                                         gpio-ranges = <&pinctrl_periphs 0 0 86>;
 219                                 };
 220
 221                                 i2c0_pins: i2c0 {
 222                                         mux {
 223                                                 groups = "i2c0_sck",
 224                                                          "i2c0_sda";
 225                                                 function = "i2c0";
 226                                                 bias-disable;
 227                                         };
 228                                 };
 229
 230                                 i2c1_x_pins: i2c1_x {
 231                                         mux {
 232                                                 groups = "i2c1_sck_x",
 233                                                          "i2c1_sda_x";
 234                                                 function = "i2c1";
 235                                                 bias-disable;
 236                                         };
 237                                 };
 238
 239                                 i2c1_z_pins: i2c1_z {
 240                                         mux {
 241                                                 groups = "i2c1_sck_z",
 242                                                          "i2c1_sda_z";
 243                                                 function = "i2c1";
 244                                                 bias-disable;
 245                                         };
 246                                 };
 247
 248                                 i2c2_a_pins: i2c2_a {
 249                                         mux {
 250                                                 groups = "i2c2_sck_a",
 251                                                          "i2c2_sda_a";
 252                                                 function = "i2c2";
 253                                                 bias-disable;
 254                                         };
 255                                 };
 256
 257                                 i2c2_x_pins: i2c2_x {
 258                                         mux {
 259                                                 groups = "i2c2_sck_x",
 260                                                          "i2c2_sda_x";
 261                                                 function = "i2c2";
 262                                                 bias-disable;
 263                                         };
 264                                 };
 265
 266                                 i2c3_a6_pins: i2c3_a6 {
 267                                         mux {
 268                                                 groups = "i2c3_sda_a6",
 269                                                          "i2c3_sck_a7";
 270                                                 function = "i2c3";
 271                                                 bias-disable;
 272                                         };
 273                                 };
 274
 275                                 i2c3_a12_pins: i2c3_a12 {
 276                                         mux {
 277                                                 groups = "i2c3_sda_a12",
 278                                                          "i2c3_sck_a13";
 279                                                 function = "i2c3";
 280                                                 bias-disable;
 281                                         };
 282                                 };
 283
 284                                 i2c3_a19_pins: i2c3_a19 {
 285                                         mux {
 286                                                 groups = "i2c3_sda_a19",
 287                                                          "i2c3_sck_a20";
 288                                                 function = "i2c3";
 289                                                 bias-disable;
 290                                         };
 291                                 };
 292
 293                                 emmc_pins: emmc {
 294                                         mux {
 295                                                 groups = "emmc_nand_d0",
 296                                                          "emmc_nand_d1",
 297                                                          "emmc_nand_d2",
 298                                                          "emmc_nand_d3",
 299                                                          "emmc_nand_d4",
 300                                                          "emmc_nand_d5",
 301                                                          "emmc_nand_d6",
 302                                                          "emmc_nand_d7",
 303                                                          "emmc_clk",
 304                                                          "emmc_cmd",
 305                                                          "emmc_ds";
 306                                                 function = "emmc";
 307                                                 bias-disable;
 308                                         };
 309                                 };
 310
 311                                 emmc_clk_gate_pins: emmc_clk_gate {
 312                                         mux {
 313                                                 groups = "BOOT_8";
 314                                                 function = "gpio_periphs";
 315                                                 bias-pull-down;
 316                                         };
 317                                 };
 318
 319                                 eth_rgmii_x_pins: eth-x-rgmii {
 320                                         mux {
 321                                                 groups = "eth_mdio_x",
 322                                                          "eth_mdc_x",
 323                                                          "eth_rgmii_rx_clk_x",
 324                                                          "eth_rx_dv_x",
 325                                                          "eth_rxd0_x",
 326                                                          "eth_rxd1_x",
 327                                                          "eth_rxd2_rgmii",
 328                                                          "eth_rxd3_rgmii",
 329                                                          "eth_rgmii_tx_clk",
 330                                                          "eth_txen_x",
 331                                                          "eth_txd0_x",
 332                                                          "eth_txd1_x",
 333                                                          "eth_txd2_rgmii",
 334                                                          "eth_txd3_rgmii";
 335                                                 function = "eth";
 336                                                 bias-disable;
 337                                         };
 338                                 };
 339
 340                                 eth_rgmii_y_pins: eth-y-rgmii {
 341                                         mux {
 342                                                 groups = "eth_mdio_y",
 343                                                          "eth_mdc_y",
 344                                                          "eth_rgmii_rx_clk_y",
 345                                                          "eth_rx_dv_y",
 346                                                          "eth_rxd0_y",
 347                                                          "eth_rxd1_y",
 348                                                          "eth_rxd2_rgmii",
 349                                                          "eth_rxd3_rgmii",
 350                                                          "eth_rgmii_tx_clk",
 351                                                          "eth_txen_y",
 352                                                          "eth_txd0_y",
 353                                                          "eth_txd1_y",
 354                                                          "eth_txd2_rgmii",
 355                                                          "eth_txd3_rgmii";
 356                                                 function = "eth";
 357                                                 bias-disable;
 358                                         };
 359                                 };
 360
 361                                 eth_rmii_x_pins: eth-x-rmii {
 362                                         mux {
 363                                                 groups = "eth_mdio_x",
 364                                                          "eth_mdc_x",
 365                                                          "eth_rgmii_rx_clk_x",
 366                                                          "eth_rx_dv_x",
 367                                                          "eth_rxd0_x",
 368                                                          "eth_rxd1_x",
 369                                                          "eth_txen_x",
 370                                                          "eth_txd0_x",
 371                                                          "eth_txd1_x";
 372                                                 function = "eth";
 373                                                 bias-disable;
 374                                         };
 375                                 };
 376
 377                                 eth_rmii_y_pins: eth-y-rmii {
 378                                         mux {
 379                                                 groups = "eth_mdio_y",
 380                                                          "eth_mdc_y",
 381                                                          "eth_rgmii_rx_clk_y",
 382                                                          "eth_rx_dv_y",
 383                                                          "eth_rxd0_y",
 384                                                          "eth_rxd1_y",
 385                                                          "eth_txen_y",
 386                                                          "eth_txd0_y",
 387                                                          "eth_txd1_y";
 388                                                 function = "eth";
 389                                                 bias-disable;
 390                                         };
 391                                 };
 392
 393                                 mclk_b_pins: mclk_b {
 394                                         mux {
 395                                                 groups = "mclk_b";
 396                                                 function = "mclk_b";
 397                                                 bias-disable;
 398                                         };
 399                                 };
 400
 401                                 mclk_c_pins: mclk_c {
 402                                         mux {
 403                                                 groups = "mclk_c";
 404                                                 function = "mclk_c";
 405                                                 bias-disable;
 406                                         };
 407                                 };
 408
 409                                 pdm_dclk_a14_pins: pdm_dclk_a14 {
 410                                         mux {
 411                                                 groups = "pdm_dclk_a14";
 412                                                 function = "pdm";
 413                                                 bias-disable;
 414                                         };
 415                                 };
 416
 417                                 pdm_dclk_a19_pins: pdm_dclk_a19 {
 418                                         mux {
 419                                                 groups = "pdm_dclk_a19";
 420                                                 function = "pdm";
 421                                                 bias-disable;
 422                                         };
 423                                 };
 424
 425                                 pdm_din0_pins: pdm_din0 {
 426                                         mux {
 427                                                 groups = "pdm_din0";
 428                                                 function = "pdm";
 429                                                 bias-disable;
 430                                         };
 431                                 };
 432
 433                                 pdm_din1_pins: pdm_din1 {
 434                                         mux {
 435                                                 groups = "pdm_din1";
 436                                                 function = "pdm";
 437                                                 bias-disable;
 438                                         };
 439                                 };
 440
 441                                 pdm_din2_pins: pdm_din2 {
 442                                         mux {
 443                                                 groups = "pdm_din2";
 444                                                 function = "pdm";
 445                                                 bias-disable;
 446                                         };
 447                                 };
 448
 449                                 pdm_din3_pins: pdm_din3 {
 450                                         mux {
 451                                                 groups = "pdm_din3";
 452                                                 function = "pdm";
 453                                                 bias-disable;
 454                                         };
 455                                 };
 456
 457                                 pwm_a_a_pins: pwm_a_a {
 458                                         mux {
 459                                                 groups = "pwm_a_a";
 460                                                 function = "pwm_a";
 461                                                 bias-disable;
 462                                         };
 463                                 };
 464
 465                                 pwm_a_x18_pins: pwm_a_x18 {
 466                                         mux {
 467                                                 groups = "pwm_a_x18";
 468                                                 function = "pwm_a";
 469                                                 bias-disable;
 470                                         };
 471                                 };
 472
 473                                 pwm_a_x20_pins: pwm_a_x20 {
 474                                         mux {
 475                                                 groups = "pwm_a_x20";
 476                                                 function = "pwm_a";
 477                                                 bias-disable;
 478                                         };
 479                                 };
 480
 481                                 pwm_a_z_pins: pwm_a_z {
 482                                         mux {
 483                                                 groups = "pwm_a_z";
 484                                                 function = "pwm_a";
 485                                                 bias-disable;
 486                                         };
 487                                 };
 488
 489                                 pwm_b_a_pins: pwm_b_a {
 490                                         mux {
 491                                                 groups = "pwm_b_a";
 492                                                 function = "pwm_b";
 493                                                 bias-disable;
 494                                         };
 495                                 };
 496
 497                                 pwm_b_x_pins: pwm_b_x {
 498                                         mux {
 499                                                 groups = "pwm_b_x";
 500                                                 function = "pwm_b";
 501                                                 bias-disable;
 502                                         };
 503                                 };
 504
 505                                 pwm_b_z_pins: pwm_b_z {
 506                                         mux {
 507                                                 groups = "pwm_b_z";
 508                                                 function = "pwm_b";
 509                                                 bias-disable;
 510                                         };
 511                                 };
 512
 513                                 pwm_c_a_pins: pwm_c_a {
 514                                         mux {
 515                                                 groups = "pwm_c_a";
 516                                                 function = "pwm_c";
 517                                                 bias-disable;
 518                                         };
 519                                 };
 520
 521                                 pwm_c_x10_pins: pwm_c_x10 {
 522                                         mux {
 523                                                 groups = "pwm_c_x10";
 524                                                 function = "pwm_c";
 525                                                 bias-disable;
 526                                         };
 527                                 };
 528
 529                                 pwm_c_x17_pins: pwm_c_x17 {
 530                                         mux {
 531                                                 groups = "pwm_c_x17";
 532                                                 function = "pwm_c";
 533                                                 bias-disable;
 534                                         };
 535                                 };
 536
 537                                 pwm_d_x11_pins: pwm_d_x11 {
 538                                         mux {
 539                                                 groups = "pwm_d_x11";
 540                                                 function = "pwm_d";
 541                                                 bias-disable;
 542                                         };
 543                                 };
 544
 545                                 pwm_d_x16_pins: pwm_d_x16 {
 546                                         mux {
 547                                                 groups = "pwm_d_x16";
 548                                                 function = "pwm_d";
 549                                                 bias-disable;
 550                                         };
 551                                 };
 552
 553                                 sdio_pins: sdio {
 554                                         mux {
 555                                                 groups = "sdio_d0",
 556                                                          "sdio_d1",
 557                                                          "sdio_d2",
 558                                                          "sdio_d3",
 559                                                          "sdio_cmd",
 560                                                          "sdio_clk";
 561                                                 function = "sdio";
 562                                                 bias-disable;
 563                                         };
 564                                 };
 565
 566                                 sdio_clk_gate_pins: sdio_clk_gate {
 567                                         mux {
 568                                                 groups = "GPIOX_4";
 569                                                 function = "gpio_periphs";
 570                                                 bias-pull-down;
 571                                         };
 572                                 };
 573
 574                                 spdif_in_z_pins: spdif_in_z {
 575                                         mux {
 576                                                 groups = "spdif_in_z";
 577                                                 function = "spdif_in";
 578                                                 bias-disable;
 579                                         };
 580                                 };
 581
 582                                 spdif_in_a1_pins: spdif_in_a1 {
 583                                         mux {
 584                                                 groups = "spdif_in_a1";
 585                                                 function = "spdif_in";
 586                                                 bias-disable;
 587                                         };
 588                                 };
 589
 590                                 spdif_in_a7_pins: spdif_in_a7 {
 591                                         mux {
 592                                                 groups = "spdif_in_a7";
 593                                                 function = "spdif_in";
 594                                                 bias-disable;
 595                                         };
 596                                 };
 597
 598                                 spdif_in_a19_pins: spdif_in_a19 {
 599                                         mux {
 600                                                 groups = "spdif_in_a19";
 601                                                 function = "spdif_in";
 602                                                 bias-disable;
 603                                         };
 604                                 };
 605
 606                                 spdif_in_a20_pins: spdif_in_a20 {
 607                                         mux {
 608                                                 groups = "spdif_in_a20";
 609                                                 function = "spdif_in";
 610                                                 bias-disable;
 611                                         };
 612                                 };
 613
 614                                 spdif_out_a1_pins: spdif_out_a1 {
 615                                         mux {
 616                                                 groups = "spdif_out_a1";
 617                                                 function = "spdif_out";
 618                                                 bias-disable;
 619                                         };
 620                                 };
 621
 622                                 spdif_out_a11_pins: spdif_out_a11 {
 623                                         mux {
 624                                                 groups = "spdif_out_a11";
 625                                                 function = "spdif_out";
 626                                                 bias-disable;
 627                                         };
 628                                 };
 629
 630                                 spdif_out_a19_pins: spdif_out_a19 {
 631                                         mux {
 632                                                 groups = "spdif_out_a19";
 633                                                 function = "spdif_out";
 634                                                 bias-disable;
 635                                         };
 636                                 };
 637
 638                                 spdif_out_a20_pins: spdif_out_a20 {
 639                                         mux {
 640                                                 groups = "spdif_out_a20";
 641                                                 function = "spdif_out";
 642                                                 bias-disable;
 643                                         };
 644                                 };
 645
 646                                 spdif_out_z_pins: spdif_out_z {
 647                                         mux {
 648                                                 groups = "spdif_out_z";
 649                                                 function = "spdif_out";
 650                                                 bias-disable;
 651                                         };
 652                                 };
 653
 654                                 spi0_pins: spi0 {
 655                                         mux {
 656                                                 groups = "spi0_miso",
 657                                                          "spi0_mosi",
 658                                                          "spi0_clk";
 659                                                 function = "spi0";
 660                                                 bias-disable;
 661                                         };
 662                                 };
 663
 664                                 spi0_ss0_pins: spi0_ss0 {
 665                                         mux {
 666                                                 groups = "spi0_ss0";
 667                                                 function = "spi0";
 668                                                 bias-disable;
 669                                         };
 670                                 };
 671
 672                                 spi0_ss1_pins: spi0_ss1 {
 673                                         mux {
 674                                                 groups = "spi0_ss1";
 675                                                 function = "spi0";
 676                                                 bias-disable;
 677                                         };
 678                                 };
 679
 680                                 spi0_ss2_pins: spi0_ss2 {
 681                                         mux {
 682                                                 groups = "spi0_ss2";
 683                                                 function = "spi0";
 684                                                 bias-disable;
 685                                         };
 686                                 };
 687
 688                                 spi1_a_pins: spi1_a {
 689                                         mux {
 690                                                 groups = "spi1_miso_a",
 691                                                          "spi1_mosi_a",
 692                                                          "spi1_clk_a";
 693                                                 function = "spi1";
 694                                                 bias-disable;
 695                                         };
 696                                 };
 697
 698                                 spi1_ss0_a_pins: spi1_ss0_a {
 699                                         mux {
 700                                                 groups = "spi1_ss0_a";
 701                                                 function = "spi1";
 702                                                 bias-disable;
 703                                         };
 704                                 };
 705
 706                                 spi1_ss1_pins: spi1_ss1 {
 707                                         mux {
 708                                                 groups = "spi1_ss1";
 709                                                 function = "spi1";
 710                                                 bias-disable;
 711                                         };
 712                                 };
 713
 714                                 spi1_x_pins: spi1_x {
 715                                         mux {
 716                                                 groups = "spi1_miso_x",
 717                                                          "spi1_mosi_x",
 718                                                          "spi1_clk_x";
 719                                                 function = "spi1";
 720                                                 bias-disable;
 721                                         };
 722                                 };
 723
 724                                 spi1_ss0_x_pins: spi1_ss0_x {
 725                                         mux {
 726                                                 groups = "spi1_ss0_x";
 727                                                 function = "spi1";
 728                                                 bias-disable;
 729                                         };
 730                                 };
 731
 732                                 tdma_din0_pins: tdma_din0 {
 733                                         mux {
 734                                                 groups = "tdma_din0";
 735                                                 function = "tdma";
 736                                                 bias-disable;
 737                                         };
 738                                 };
 739
 740                                 tdma_dout0_x14_pins: tdma_dout0_x14 {
 741                                         mux {
 742                                                 groups = "tdma_dout0_x14";
 743                                                 function = "tdma";
 744                                                 bias-disable;
 745                                         };
 746                                 };
 747
 748                                 tdma_dout0_x15_pins: tdma_dout0_x15 {
 749                                         mux {
 750                                                 groups = "tdma_dout0_x15";
 751                                                 function = "tdma";
 752                                                 bias-disable;
 753                                         };
 754                                 };
 755
 756                                 tdma_dout1_pins: tdma_dout1 {
 757                                         mux {
 758                                                 groups = "tdma_dout1";
 759                                                 function = "tdma";
 760                                                 bias-disable;
 761                                         };
 762                                 };
 763
 764                                 tdma_din1_pins: tdma_din1 {
 765                                         mux {
 766                                                 groups = "tdma_din1";
 767                                                 function = "tdma";
 768                                                 bias-disable;
 769                                         };
 770                                 };
 771
 772                                 tdma_fs_pins: tdma_fs {
 773                                         mux {
 774                                                 groups = "tdma_fs";
 775                                                 function = "tdma";
 776                                                 bias-disable;
 777                                         };
 778                                 };
 779
 780                                 tdma_fs_slv_pins: tdma_fs_slv {
 781                                         mux {
 782                                                 groups = "tdma_fs_slv";
 783                                                 function = "tdma";
 784                                                 bias-disable;
 785                                         };
 786                                 };
 787
 788                                 tdma_sclk_pins: tdma_sclk {
 789                                         mux {
 790                                                 groups = "tdma_sclk";
 791                                                 function = "tdma";
 792                                                 bias-disable;
 793                                         };
 794                                 };
 795
 796                                 tdma_sclk_slv_pins: tdma_sclk_slv {
 797                                         mux {
 798                                                 groups = "tdma_sclk_slv";
 799                                                 function = "tdma";
 800                                                 bias-disable;
 801                                         };
 802                                 };
 803
 804                                 tdmb_din0_pins: tdmb_din0 {
 805                                         mux {
 806                                                 groups = "tdmb_din0";
 807                                                 function = "tdmb";
 808                                                 bias-disable;
 809                                         };
 810                                 };
 811
 812                                 tdmb_din1_pins: tdmb_din1 {
 813                                         mux {
 814                                                 groups = "tdmb_din1";
 815                                                 function = "tdmb";
 816                                                 bias-disable;
 817                                         };
 818                                 };
 819
 820                                 tdmb_din2_pins: tdmb_din2 {
 821                                         mux {
 822                                                 groups = "tdmb_din2";
 823                                                 function = "tdmb";
 824                                                 bias-disable;
 825                                         };
 826                                 };
 827
 828                                 tdmb_din3_pins: tdmb_din3 {
 829                                         mux {
 830                                                 groups = "tdmb_din3";
 831                                                 function = "tdmb";
 832                                                 bias-disable;
 833                                         };
 834                                 };
 835
 836                                 tdmb_dout0_pins: tdmb_dout0 {
 837                                         mux {
 838                                                 groups = "tdmb_dout0";
 839                                                 function = "tdmb";
 840                                                 bias-disable;
 841                                         };
 842                                 };
 843
 844                                 tdmb_dout1_pins: tdmb_dout1 {
 845                                         mux {
 846                                                 groups = "tdmb_dout1";
 847                                                 function = "tdmb";
 848                                                 bias-disable;
 849                                         };
 850                                 };
 851
 852                                 tdmb_dout2_pins: tdmb_dout2 {
 853                                         mux {
 854                                                 groups = "tdmb_dout2";
 855                                                 function = "tdmb";
 856                                                 bias-disable;
 857                                         };
 858                                 };
 859
 860                                 tdmb_dout3_pins: tdmb_dout3 {
 861                                         mux {
 862                                                 groups = "tdmb_dout3";
 863                                                 function = "tdmb";
 864                                                 bias-disable;
 865                                         };
 866                                 };
 867
 868                                 tdmb_fs_pins: tdmb_fs {
 869                                         mux {
 870                                                 groups = "tdmb_fs";
 871                                                 function = "tdmb";
 872                                                 bias-disable;
 873                                         };
 874                                 };
 875
 876                                 tdmb_fs_slv_pins: tdmb_fs_slv {
 877                                         mux {
 878                                                 groups = "tdmb_fs_slv";
 879                                                 function = "tdmb";
 880                                                 bias-disable;
 881                                         };
 882                                 };
 883
 884                                 tdmb_sclk_pins: tdmb_sclk {
 885                                         mux {
 886                                                 groups = "tdmb_sclk";
 887                                                 function = "tdmb";
 888                                                 bias-disable;
 889                                         };
 890                                 };
 891
 892                                 tdmb_sclk_slv_pins: tdmb_sclk_slv {
 893                                         mux {
 894                                                 groups = "tdmb_sclk_slv";
 895                                                 function = "tdmb";
 896                                                 bias-disable;
 897                                         };
 898                                 };
 899
 900                                 tdmc_fs_pins: tdmc_fs {
 901                                         mux {
 902                                                 groups = "tdmc_fs";
 903                                                 function = "tdmc";
 904                                                 bias-disable;
 905                                         };
 906                                 };
 907
 908                                 tdmc_fs_slv_pins: tdmc_fs_slv {
 909                                         mux {
 910                                                 groups = "tdmc_fs_slv";
 911                                                 function = "tdmc";
 912                                                 bias-disable;
 913                                         };
 914                                 };
 915
 916                                 tdmc_sclk_pins: tdmc_sclk {
 917                                         mux {
 918                                                 groups = "tdmc_sclk";
 919                                                 function = "tdmc";
 920                                                 bias-disable;
 921                                         };
 922                                 };
 923
 924                                 tdmc_sclk_slv_pins: tdmc_sclk_slv {
 925                                         mux {
 926                                                 groups = "tdmc_sclk_slv";
 927                                                 function = "tdmc";
 928                                                 bias-disable;
 929                                         };
 930                                 };
 931
 932                                 tdmc_din0_pins: tdmc_din0 {
 933                                         mux {
 934                                                 groups = "tdmc_din0";
 935                                                 function = "tdmc";
 936                                                 bias-disable;
 937                                         };
 938                                 };
 939
 940                                 tdmc_din1_pins: tdmc_din1 {
 941                                         mux {
 942                                                 groups = "tdmc_din1";
 943                                                 function = "tdmc";
 944                                                 bias-disable;
 945                                         };
 946                                 };
 947
 948                                 tdmc_din2_pins: tdmc_din2 {
 949                                         mux {
 950                                                 groups = "tdmc_din2";
 951                                                 function = "tdmc";
 952                                                 bias-disable;
 953                                         };
 954                                 };
 955
 956                                 tdmc_din3_pins: tdmc_din3 {
 957                                         mux {
 958                                                 groups = "tdmc_din3";
 959                                                 function = "tdmc";
 960                                                 bias-disable;
 961                                         };
 962                                 };
 963
 964                                 tdmc_dout0_pins: tdmc_dout0 {
 965                                         mux {
 966                                                 groups = "tdmc_dout0";
 967                                                 function = "tdmc";
 968                                                 bias-disable;
 969                                         };
 970                                 };
 971
 972                                 tdmc_dout1_pins: tdmc_dout1 {
 973                                         mux {
 974                                                 groups = "tdmc_dout1";
 975                                                 function = "tdmc";
 976                                                 bias-disable;
 977                                         };
 978                                 };
 979
 980                                 tdmc_dout2_pins: tdmc_dout2 {
 981                                         mux {
 982                                                 groups = "tdmc_dout2";
 983                                                 function = "tdmc";
 984                                                 bias-disable;
 985                                         };
 986                                 };
 987
 988                                 tdmc_dout3_pins: tdmc_dout3 {
 989                                         mux {
 990                                                 groups = "tdmc_dout3";
 991                                                 function = "tdmc";
 992                                                 bias-disable;
 993                                         };
 994                                 };
 995
 996                                 uart_a_pins: uart_a {
 997                                         mux {
 998                                                 groups = "uart_tx_a",
 999                                                          "uart_rx_a";
1000                                                 function = "uart_a";
1001                                                 bias-disable;
1002                                         };
1003                                 };
1004
1005                                 uart_a_cts_rts_pins: uart_a_cts_rts {
1006                                         mux {
1007                                                 groups = "uart_cts_a",
1008                                                          "uart_rts_a";
1009                                                 function = "uart_a";
1010                                                 bias-disable;
1011                                         };
1012                                 };
1013
1014                                 uart_b_x_pins: uart_b_x {
1015                                         mux {
1016                                                 groups = "uart_tx_b_x",
1017                                                          "uart_rx_b_x";
1018                                                 function = "uart_b";
1019                                                 bias-disable;
1020                                         };
1021                                 };
1022
1023                                 uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
1024                                         mux {
1025                                                 groups = "uart_cts_b_x",
1026                                                          "uart_rts_b_x";
1027                                                 function = "uart_b";
1028                                                 bias-disable;
1029                                         };
1030                                 };
1031
1032                                 uart_b_z_pins: uart_b_z {
1033                                         mux {
1034                                                 groups = "uart_tx_b_z",
1035                                                          "uart_rx_b_z";
1036                                                 function = "uart_b";
1037                                                 bias-disable;
1038                                         };
1039                                 };
1040
1041                                 uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
1042                                         mux {
1043                                                 groups = "uart_cts_b_z",
1044                                                          "uart_rts_b_z";
1045                                                 function = "uart_b";
1046                                                 bias-disable;
1047                                         };
1048                                 };
1049
1050                                 uart_ao_b_z_pins: uart_ao_b_z {
1051                                         mux {
1052                                                 groups = "uart_ao_tx_b_z",
1053                                                          "uart_ao_rx_b_z";
1054                                                 function = "uart_ao_b_z";
1055                                                 bias-disable;
1056                                         };
1057                                 };
1058
1059                                 uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts {
1060                                         mux {
1061                                                 groups = "uart_ao_cts_b_z",
1062                                                          "uart_ao_rts_b_z";
1063                                                 function = "uart_ao_b_z";
1064                                                 bias-disable;
1065                                         };
1066                                 };
1067                         };
1068                 };
1069
1070                 hiubus: bus@ff63c000 {
1071                         compatible = "simple-bus";
1072                         reg = <0x0 0xff63c000 0x0 0x1c00>;
1073                         #address-cells = <2>;
1074                         #size-cells = <2>;
1075                         ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
1076
1077                         sysctrl: system-controller@0 {
1078                                 compatible = "amlogic,meson-axg-hhi-sysctrl",
1079                                              "simple-mfd", "syscon";
1080                                 reg = <0 0 0 0x400>;
1081
1082                                 clkc: clock-controller {
1083                                         compatible = "amlogic,axg-clkc";
1084                                         #clock-cells = <1>;
1085                                         clocks = <&xtal>;
1086                                         clock-names = "xtal";
1087                                 };
1088                         };
1089                 };
1090
1091                 mailbox: mailbox@ff63c404 {
1092                         compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
1093                         reg = <0 0xff63c404 0 0x4c>;
1094                         interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
1095                                      <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
1096                                      <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
1097                         #mbox-cells = <1>;
1098                 };
1099
1100                 audio: bus@ff642000 {
1101                         compatible = "simple-bus";
1102                         reg = <0x0 0xff642000 0x0 0x2000>;
1103                         #address-cells = <2>;
1104                         #size-cells = <2>;
1105                         ranges = <0x0 0x0 0x0 0xff642000 0x0 0x2000>;
1106
1107                         clkc_audio: clock-controller@0 {
1108                                 compatible = "amlogic,axg-audio-clkc";
1109                                 reg = <0x0 0x0 0x0 0xb4>;
1110                                 #clock-cells = <1>;
1111
1112                                 clocks = <&clkc CLKID_AUDIO>,
1113                                          <&clkc CLKID_MPLL0>,
1114                                          <&clkc CLKID_MPLL1>,
1115                                          <&clkc CLKID_MPLL2>,
1116                                          <&clkc CLKID_MPLL3>,
1117                                          <&clkc CLKID_HIFI_PLL>,
1118                                          <&clkc CLKID_FCLK_DIV3>,
1119                                          <&clkc CLKID_FCLK_DIV4>,
1120                                          <&clkc CLKID_GP0_PLL>;
1121                                 clock-names = "pclk",
1122                                               "mst_in0",
1123                                               "mst_in1",
1124                                               "mst_in2",
1125                                               "mst_in3",
1126                                               "mst_in4",
1127                                               "mst_in5",
1128                                               "mst_in6",
1129                                               "mst_in7";
1130
1131                                 resets = <&reset RESET_AUDIO>;
1132                         };
1133
1134                         toddr_a: audio-controller@100 {
1135                                 compatible = "amlogic,axg-toddr";
1136                                 reg = <0x0 0x100 0x0 0x1c>;
1137                                 #sound-dai-cells = <0>;
1138                                 sound-name-prefix = "TODDR_A";
1139                                 interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>;
1140                                 clocks = <&clkc_audio AUD_CLKID_TODDR_A>;
1141                                 resets = <&arb AXG_ARB_TODDR_A>;
1142                                 status = "disabled";
1143                         };
1144
1145                         toddr_b: audio-controller@140 {
1146                                 compatible = "amlogic,axg-toddr";
1147                                 reg = <0x0 0x140 0x0 0x1c>;
1148                                 #sound-dai-cells = <0>;
1149                                 sound-name-prefix = "TODDR_B";
1150                                 interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
1151                                 clocks = <&clkc_audio AUD_CLKID_TODDR_B>;
1152                                 resets = <&arb AXG_ARB_TODDR_B>;
1153                                 status = "disabled";
1154                         };
1155
1156                         toddr_c: audio-controller@180 {
1157                                 compatible = "amlogic,axg-toddr";
1158                                 reg = <0x0 0x180 0x0 0x1c>;
1159                                 #sound-dai-cells = <0>;
1160                                 sound-name-prefix = "TODDR_C";
1161                                 interrupts = <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>;
1162                                 clocks = <&clkc_audio AUD_CLKID_TODDR_C>;
1163                                 resets = <&arb AXG_ARB_TODDR_C>;
1164                                 status = "disabled";
1165                         };
1166
1167                         frddr_a: audio-controller@1c0 {
1168                                 compatible = "amlogic,axg-frddr";
1169                                 reg = <0x0 0x1c0 0x0 0x1c>;
1170                                 #sound-dai-cells = <0>;
1171                                 sound-name-prefix = "FRDDR_A";
1172                                 interrupts = <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>;
1173                                 clocks = <&clkc_audio AUD_CLKID_FRDDR_A>;
1174                                 resets = <&arb AXG_ARB_FRDDR_A>;
1175                                 status = "disabled";
1176                         };
1177
1178                         frddr_b: audio-controller@200 {
1179                                 compatible = "amlogic,axg-frddr";
1180                                 reg = <0x0 0x200 0x0 0x1c>;
1181                                 #sound-dai-cells = <0>;
1182                                 sound-name-prefix = "FRDDR_B";
1183                                 interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>;
1184                                 clocks = <&clkc_audio AUD_CLKID_FRDDR_B>;
1185                                 resets = <&arb AXG_ARB_FRDDR_B>;
1186                                 status = "disabled";
1187                         };
1188
1189                         frddr_c: audio-controller@240 {
1190                                 compatible = "amlogic,axg-frddr";
1191                                 reg = <0x0 0x240 0x0 0x1c>;
1192                                 #sound-dai-cells = <0>;
1193                                 sound-name-prefix = "FRDDR_C";
1194                                 interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
1195                                 clocks = <&clkc_audio AUD_CLKID_FRDDR_C>;
1196                                 resets = <&arb AXG_ARB_FRDDR_C>;
1197                                 status = "disabled";
1198                         };
1199
1200                         arb: reset-controller@280 {
1201                                 compatible = "amlogic,meson-axg-audio-arb";
1202                                 reg = <0x0 0x280 0x0 0x4>;
1203                                 #reset-cells = <1>;
1204                                 clocks = <&clkc_audio AUD_CLKID_DDR_ARB>;
1205                         };
1206
1207                         tdmin_a: audio-controller@300 {
1208                                 compatible = "amlogic,axg-tdmin";
1209                                 reg = <0x0 0x300 0x0 0x40>;
1210                                 sound-name-prefix = "TDMIN_A";
1211                                 clocks = <&clkc_audio AUD_CLKID_TDMIN_A>,
1212                                          <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>,
1213                                          <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>,
1214                                          <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>,
1215                                          <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>;
1216                                 clock-names = "pclk", "sclk", "sclk_sel",
1217                                               "lrclk", "lrclk_sel";
1218                                 status = "disabled";
1219                         };
1220
1221                         tdmin_b: audio-controller@340 {
1222                                 compatible = "amlogic,axg-tdmin";
1223                                 reg = <0x0 0x340 0x0 0x40>;
1224                                 sound-name-prefix = "TDMIN_B";
1225                                 clocks = <&clkc_audio AUD_CLKID_TDMIN_B>,
1226                                          <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>,
1227                                          <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>,
1228                                          <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>,
1229                                          <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>;
1230                                 clock-names = "pclk", "sclk", "sclk_sel",
1231                                               "lrclk", "lrclk_sel";
1232                                 status = "disabled";
1233                         };
1234
1235                         tdmin_c: audio-controller@380 {
1236                                 compatible = "amlogic,axg-tdmin";
1237                                 reg = <0x0 0x380 0x0 0x40>;
1238                                 sound-name-prefix = "TDMIN_C";
1239                                 clocks = <&clkc_audio AUD_CLKID_TDMIN_C>,
1240                                          <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>,
1241                                          <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>,
1242                                          <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>,
1243                                          <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>;
1244                                 clock-names = "pclk", "sclk", "sclk_sel",
1245                                               "lrclk", "lrclk_sel";
1246                                 status = "disabled";
1247                         };
1248
1249                         tdmin_lb: audio-controller@3c0 {
1250                                 compatible = "amlogic,axg-tdmin";
1251                                 reg = <0x0 0x3c0 0x0 0x40>;
1252                                 sound-name-prefix = "TDMIN_LB";
1253                                 clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>,
1254                                          <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>,
1255                                          <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>,
1256                                          <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>,
1257                                          <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>;
1258                                 clock-names = "pclk", "sclk", "sclk_sel",
1259                                               "lrclk", "lrclk_sel";
1260                                 status = "disabled";
1261                         };
1262
1263                         spdifout: audio-controller@480 {
1264                                 compatible = "amlogic,axg-spdifout";
1265                                 reg = <0x0 0x480 0x0 0x50>;
1266                                 #sound-dai-cells = <0>;
1267                                 sound-name-prefix = "SPDIFOUT";
1268                                 clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>,
1269                                          <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>;
1270                                 clock-names = "pclk", "mclk";
1271                                 status = "disabled";
1272                         };
1273
1274                         tdmout_a: audio-controller@500 {
1275                                 compatible = "amlogic,axg-tdmout";
1276                                 reg = <0x0 0x500 0x0 0x40>;
1277                                 sound-name-prefix = "TDMOUT_A";
1278                                 clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>,
1279                                          <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>,
1280                                          <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>,
1281                                          <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>,
1282                                          <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>;
1283                                 clock-names = "pclk", "sclk", "sclk_sel",
1284                                               "lrclk", "lrclk_sel";
1285                                 status = "disabled";
1286                         };
1287
1288                         tdmout_b: audio-controller@540 {
1289                                 compatible = "amlogic,axg-tdmout";
1290                                 reg = <0x0 0x540 0x0 0x40>;
1291                                 sound-name-prefix = "TDMOUT_B";
1292                                 clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>,
1293                                          <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>,
1294                                          <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>,
1295                                          <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>,
1296                                          <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>;
1297                                 clock-names = "pclk", "sclk", "sclk_sel",
1298                                               "lrclk", "lrclk_sel";
1299                                 status = "disabled";
1300                         };
1301
1302                         tdmout_c: audio-controller@580 {
1303                                 compatible = "amlogic,axg-tdmout";
1304                                 reg = <0x0 0x580 0x0 0x40>;
1305                                 sound-name-prefix = "TDMOUT_C";
1306                                 clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>,
1307                                          <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>,
1308                                          <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>,
1309                                          <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>,
1310                                          <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>;
1311                                 clock-names = "pclk", "sclk", "sclk_sel",
1312                                               "lrclk", "lrclk_sel";
1313                                 status = "disabled";
1314                         };
1315                 };
1316
1317                 aobus: bus@ff800000 {
1318                         compatible = "simple-bus";
1319                         reg = <0x0 0xff800000 0x0 0x100000>;
1320                         #address-cells = <2>;
1321                         #size-cells = <2>;
1322                         ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
1323
1324                         sysctrl_AO: sys-ctrl@0 {
1325                                 compatible = "amlogic,meson-axg-ao-sysctrl", "simple-mfd", "syscon";
1326                                 reg =  <0x0 0x0 0x0 0x100>;
1327
1328                                 clkc_AO: clock-controller {
1329                                         compatible = "amlogic,meson-axg-aoclkc";
1330                                         #clock-cells = <1>;
1331                                         #reset-cells = <1>;
1332                                         clocks = <&xtal>, <&clkc CLKID_CLK81>;
1333                                         clock-names = "xtal", "mpeg-clk";
1334                                 };
1335                         };
1336
1337                         pinctrl_aobus: pinctrl@14 {
1338                                 compatible = "amlogic,meson-axg-aobus-pinctrl";
1339                                 #address-cells = <2>;
1340                                 #size-cells = <2>;
1341                                 ranges;
1342
1343                                 gpio_ao: bank@14 {
1344                                         reg = <0x0 0x00014 0x0 0x8>,
1345                                               <0x0 0x0002c 0x0 0x4>,
1346                                               <0x0 0x00024 0x0 0x8>;
1347                                         reg-names = "mux", "pull", "gpio";
1348                                         gpio-controller;
1349                                         #gpio-cells = <2>;
1350                                         gpio-ranges = <&pinctrl_aobus 0 0 15>;
1351                                 };
1352
1353                                 i2c_ao_sck_4_pins: i2c_ao_sck_4 {
1354                                         mux {
1355                                                 groups = "i2c_ao_sck_4";
1356                                                 function = "i2c_ao";
1357                                                 bias-disable;
1358                                         };
1359                                 };
1360
1361                                 i2c_ao_sck_8_pins: i2c_ao_sck_8 {
1362                                         mux {
1363                                                 groups = "i2c_ao_sck_8";
1364                                                 function = "i2c_ao";
1365                                                 bias-disable;
1366                                         };
1367                                 };
1368
1369                                 i2c_ao_sck_10_pins: i2c_ao_sck_10 {
1370                                         mux {
1371                                                 groups = "i2c_ao_sck_10";
1372                                                 function = "i2c_ao";
1373                                                 bias-disable;
1374                                         };
1375                                 };
1376
1377                                 i2c_ao_sda_5_pins: i2c_ao_sda_5 {
1378                                         mux {
1379                                                 groups = "i2c_ao_sda_5";
1380                                                 function = "i2c_ao";
1381                                                 bias-disable;
1382                                         };
1383                                 };
1384
1385                                 i2c_ao_sda_9_pins: i2c_ao_sda_9 {
1386                                         mux {
1387                                                 groups = "i2c_ao_sda_9";
1388                                                 function = "i2c_ao";
1389                                                 bias-disable;
1390                                         };
1391                                 };
1392
1393                                 i2c_ao_sda_11_pins: i2c_ao_sda_11 {
1394                                         mux {
1395                                                 groups = "i2c_ao_sda_11";
1396                                                 function = "i2c_ao";
1397                                                 bias-disable;
1398                                         };
1399                                 };
1400
1401                                 remote_input_ao_pins: remote_input_ao {
1402                                         mux {
1403                                                 groups = "remote_input_ao";
1404                                                 function = "remote_input_ao";
1405                                                 bias-disable;
1406                                         };
1407                                 };
1408
1409                                 uart_ao_a_pins: uart_ao_a {
1410                                         mux {
1411                                                 groups = "uart_ao_tx_a",
1412                                                          "uart_ao_rx_a";
1413                                                 function = "uart_ao_a";
1414                                                 bias-disable;
1415                                         };
1416                                 };
1417
1418                                 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
1419                                         mux {
1420                                                 groups = "uart_ao_cts_a",
1421                                                          "uart_ao_rts_a";
1422                                                 function = "uart_ao_a";
1423                                                 bias-disable;
1424                                         };
1425                                 };
1426
1427                                 uart_ao_b_pins: uart_ao_b {
1428                                         mux {
1429                                                 groups = "uart_ao_tx_b",
1430                                                          "uart_ao_rx_b";
1431                                                 function = "uart_ao_b";
1432                                                 bias-disable;
1433                                         };
1434                                 };
1435
1436                                 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
1437                                         mux {
1438                                                 groups = "uart_ao_cts_b",
1439                                                          "uart_ao_rts_b";
1440                                                 function = "uart_ao_b";
1441                                                 bias-disable;
1442                                         };
1443                                 };
1444                         };
1445
1446                         sec_AO: ao-secure@140 {
1447                                 compatible = "amlogic,meson-gx-ao-secure", "syscon";
1448                                 reg = <0x0 0x140 0x0 0x140>;
1449                                 amlogic,has-chip-id;
1450                         };
1451
1452                         pwm_AO_cd: pwm@2000 {
1453                                 compatible = "amlogic,meson-axg-ao-pwm";
1454                                 reg = <0x0 0x02000  0x0 0x20>;
1455                                 #pwm-cells = <3>;
1456                                 status = "disabled";
1457                         };
1458
1459                         uart_AO: serial@3000 {
1460                                 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1461                                 reg = <0x0 0x3000 0x0 0x18>;
1462                                 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
1463                                 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
1464                                 clock-names = "xtal", "pclk", "baud";
1465                                 status = "disabled";
1466                         };
1467
1468                         uart_AO_B: serial@4000 {
1469                                 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1470                                 reg = <0x0 0x4000 0x0 0x18>;
1471                                 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
1472                                 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
1473                                 clock-names = "xtal", "pclk", "baud";
1474                                 status = "disabled";
1475                         };
1476
1477                         i2c_AO: i2c@5000 {
1478                                 compatible = "amlogic,meson-axg-i2c";
1479                                 reg = <0x0 0x05000 0x0 0x20>;
1480                                 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
1481                                 clocks = <&clkc CLKID_AO_I2C>;
1482                                 #address-cells = <1>;
1483                                 #size-cells = <0>;
1484                                 status = "disabled";
1485                         };
1486
1487                         pwm_AO_ab: pwm@7000 {
1488                                 compatible = "amlogic,meson-axg-ao-pwm";
1489                                 reg = <0x0 0x07000 0x0 0x20>;
1490                                 #pwm-cells = <3>;
1491                                 status = "disabled";
1492                         };
1493
1494                         ir: ir@8000 {
1495                                 compatible = "amlogic,meson-gxbb-ir";
1496                                 reg = <0x0 0x8000 0x0 0x20>;
1497                                 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
1498                                 status = "disabled";
1499                         };
1500
1501                         saradc: adc@9000 {
1502                                 compatible = "amlogic,meson-axg-saradc",
1503                                         "amlogic,meson-saradc";
1504                                 reg = <0x0 0x9000 0x0 0x38>;
1505                                 #io-channel-cells = <1>;
1506                                 interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
1507                                 clocks = <&xtal>,
1508                                          <&clkc_AO CLKID_AO_SAR_ADC>,
1509                                          <&clkc_AO CLKID_AO_SAR_ADC_CLK>,
1510                                          <&clkc_AO CLKID_AO_SAR_ADC_SEL>;
1511                                 clock-names = "clkin", "core", "adc_clk", "adc_sel";
1512                                 status = "disabled";
1513                         };
1514                 };
1515
1516                 gic: interrupt-controller@ffc01000 {
1517                         compatible = "arm,gic-400";
1518                         reg = <0x0 0xffc01000 0 0x1000>,
1519                               <0x0 0xffc02000 0 0x2000>,
1520                               <0x0 0xffc04000 0 0x2000>,
1521                               <0x0 0xffc06000 0 0x2000>;
1522                         interrupt-controller;
1523                         interrupts = <GIC_PPI 9
1524                                 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1525                         #interrupt-cells = <3>;
1526                         #address-cells = <0>;
1527                 };
1528
1529                 cbus: bus@ffd00000 {
1530                         compatible = "simple-bus";
1531                         reg = <0x0 0xffd00000 0x0 0x25000>;
1532                         #address-cells = <2>;
1533                         #size-cells = <2>;
1534                         ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>;
1535
1536                         reset: reset-controller@1004 {
1537                                 compatible = "amlogic,meson-axg-reset";
1538                                 reg = <0x0 0x01004 0x0 0x9c>;
1539                                 #reset-cells = <1>;
1540                         };
1541
1542                         gpio_intc: interrupt-controller@f080 {
1543                                 compatible = "amlogic,meson-axg-gpio-intc",
1544                                              "amlogic,meson-gpio-intc";
1545                                 reg = <0x0 0xf080 0x0 0x10>;
1546                                 interrupt-controller;
1547                                 #interrupt-cells = <2>;
1548                                 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
1549                         };
1550
1551                         watchdog@f0d0 {
1552                                 compatible = "amlogic,meson-gxbb-wdt";
1553                                 reg = <0x0 0xf0d0 0x0 0x10>;
1554                                 clocks = <&xtal>;
1555                         };
1556
1557                         pwm_ab: pwm@1b000 {
1558                                 compatible = "amlogic,meson-axg-ee-pwm";
1559                                 reg = <0x0 0x1b000 0x0 0x20>;
1560                                 #pwm-cells = <3>;
1561                                 status = "disabled";
1562                         };
1563
1564                         pwm_cd: pwm@1a000 {
1565                                 compatible = "amlogic,meson-axg-ee-pwm";
1566                                 reg = <0x0 0x1a000 0x0 0x20>;
1567                                 #pwm-cells = <3>;
1568                                 status = "disabled";
1569                         };
1570
1571                         spicc0: spi@13000 {
1572                                 compatible = "amlogic,meson-axg-spicc";
1573                                 reg = <0x0 0x13000 0x0 0x3c>;
1574                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1575                                 clocks = <&clkc CLKID_SPICC0>;
1576                                 clock-names = "core";
1577                                 #address-cells = <1>;
1578                                 #size-cells = <0>;
1579                                 status = "disabled";
1580                         };
1581
1582                         spicc1: spi@15000 {
1583                                 compatible = "amlogic,meson-axg-spicc";
1584                                 reg = <0x0 0x15000 0x0 0x3c>;
1585                                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1586                                 clocks = <&clkc CLKID_SPICC1>;
1587                                 clock-names = "core";
1588                                 #address-cells = <1>;
1589                                 #size-cells = <0>;
1590                                 status = "disabled";
1591                         };
1592
1593                         i2c3: i2c@1c000 {
1594                                 compatible = "amlogic,meson-axg-i2c";
1595                                 reg = <0x0 0x1c000 0x0 0x20>;
1596                                 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
1597                                 clocks = <&clkc CLKID_I2C>;
1598                                 #address-cells = <1>;
1599                                 #size-cells = <0>;
1600                                 status = "disabled";
1601                         };
1602
1603                         i2c2: i2c@1d000 {
1604                                 compatible = "amlogic,meson-axg-i2c";
1605                                 reg = <0x0 0x1d000 0x0 0x20>;
1606                                 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
1607                                 clocks = <&clkc CLKID_I2C>;
1608                                 #address-cells = <1>;
1609                                 #size-cells = <0>;
1610                                 status = "disabled";
1611                         };
1612
1613                         i2c1: i2c@1e000 {
1614                                 compatible = "amlogic,meson-axg-i2c";
1615                                 reg = <0x0 0x1e000 0x0 0x20>;
1616                                 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
1617                                 clocks = <&clkc CLKID_I2C>;
1618                                 #address-cells = <1>;
1619                                 #size-cells = <0>;
1620                                 status = "disabled";
1621                         };
1622
1623                         i2c0: i2c@1f000 {
1624                                 compatible = "amlogic,meson-axg-i2c";
1625                                 reg = <0x0 0x1f000 0x0 0x20>;
1626                                 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
1627                                 clocks = <&clkc CLKID_I2C>;
1628                                 #address-cells = <1>;
1629                                 #size-cells = <0>;
1630                                 status = "disabled";
1631                         };
1632
1633                         uart_B: serial@23000 {
1634                                 compatible = "amlogic,meson-gx-uart";
1635                                 reg = <0x0 0x23000 0x0 0x18>;
1636                                 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
1637                                 status = "disabled";
1638                                 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
1639                                 clock-names = "xtal", "pclk", "baud";
1640                         };
1641
1642                         uart_A: serial@24000 {
1643                                 compatible = "amlogic,meson-gx-uart";
1644                                 reg = <0x0 0x24000 0x0 0x18>;
1645                                 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
1646                                 status = "disabled";
1647                                 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
1648                                 clock-names = "xtal", "pclk", "baud";
1649                         };
1650                 };
1651
1652                 apb: bus@ffe00000 {
1653                         compatible = "simple-bus";
1654                         reg = <0x0 0xffe00000 0x0 0x200000>;
1655                         #address-cells = <2>;
1656                         #size-cells = <2>;
1657                         ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>;
1658
1659                         sd_emmc_b: sd@5000 {
1660                                 compatible = "amlogic,meson-axg-mmc";
1661                                 reg = <0x0 0x5000 0x0 0x800>;
1662                                 interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
1663                                 status = "disabled";
1664                                 clocks = <&clkc CLKID_SD_EMMC_B>,
1665                                         <&clkc CLKID_SD_EMMC_B_CLK0>,
1666                                         <&clkc CLKID_FCLK_DIV2>;
1667                                 clock-names = "core", "clkin0", "clkin1";
1668                                 resets = <&reset RESET_SD_EMMC_B>;
1669                         };
1670
1671                         sd_emmc_c: mmc@7000 {
1672                                 compatible = "amlogic,meson-axg-mmc";
1673                                 reg = <0x0 0x7000 0x0 0x800>;
1674                                 interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>;
1675                                 status = "disabled";
1676                                 clocks = <&clkc CLKID_SD_EMMC_C>,
1677                                         <&clkc CLKID_SD_EMMC_C_CLK0>,
1678                                         <&clkc CLKID_FCLK_DIV2>;
1679                                 clock-names = "core", "clkin0", "clkin1";
1680                                 resets = <&reset RESET_SD_EMMC_C>;
1681                         };
1682                 };
1683
1684                 sram: sram@fffc0000 {
1685                         compatible = "amlogic,meson-axg-sram", "mmio-sram";
1686                         reg = <0x0 0xfffc0000 0x0 0x20000>;
1687                         #address-cells = <1>;
1688                         #size-cells = <1>;
1689                         ranges = <0 0x0 0xfffc0000 0x20000>;
1690
1691                         cpu_scp_lpri: scp-shmem@13000 {
1692                                 compatible = "amlogic,meson-axg-scp-shmem";
1693                                 reg = <0x13000 0x400>;
1694                         };
1695
1696                         cpu_scp_hpri: scp-shmem@13400 {
1697                                 compatible = "amlogic,meson-axg-scp-shmem";
1698                                 reg = <0x13400 0x400>;
1699                         };
1700                 };
1701         };
1702
1703         timer {
1704                 compatible = "arm,armv8-timer";
1705                 interrupts = <GIC_PPI 13
1706                         (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1707                              <GIC_PPI 14
1708                         (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1709                              <GIC_PPI 11
1710                         (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1711                              <GIC_PPI 10
1712                         (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
1713         };
1714
1715         xtal: xtal-clk {
1716                 compatible = "fixed-clock";
1717                 clock-frequency = <24000000>;
1718                 clock-output-names = "xtal";
1719                 #clock-cells = <0>;
1720         };
1721 };