sys/gnu/dts/arm64/amlogic/meson-gxl.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2016 Endless Computers, Inc.
   4  * Author: Carlo Caione <carlo@endlessm.com>
   5  */
   6
   7 #include "meson-gx.dtsi"
   8 #include <dt-bindings/clock/gxbb-clkc.h>
   9 #include <dt-bindings/clock/gxbb-aoclkc.h>
  10 #include <dt-bindings/gpio/meson-gxl-gpio.h>
  11 #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
  12
  13 / {
  14         compatible = "amlogic,meson-gxl";
  15
  16         soc {
  17                 usb0: usb@c9000000 {
  18                         status = "disabled";
  19                         compatible = "amlogic,meson-gxl-dwc3";
  20                         #address-cells = <2>;
  21                         #size-cells = <2>;
  22                         ranges;
  23
  24                         clocks = <&clkc CLKID_USB>;
  25                         clock-names = "usb_general";
  26                         resets = <&reset RESET_USB_OTG>;
  27                         reset-names = "usb_otg";
  28
  29                         dwc3: dwc3@c9000000 {
  30                                 compatible = "snps,dwc3";
  31                                 reg = <0x0 0xc9000000 0x0 0x100000>;
  32                                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
  33                                 dr_mode = "host";
  34                                 maximum-speed = "high-speed";
  35                                 snps,dis_u2_susphy_quirk;
  36                                 phys = <&usb3_phy>, <&usb2_phy0>, <&usb2_phy1>;
  37                         };
  38                 };
  39         };
  40 };
  41
  42 &apb {
  43         usb2_phy0: phy@78000 {
  44                 compatible = "amlogic,meson-gxl-usb2-phy";
  45                 #phy-cells = <0>;
  46                 reg = <0x0 0x78000 0x0 0x20>;
  47                 clocks = <&clkc CLKID_USB>;
  48                 clock-names = "phy";
  49                 resets = <&reset RESET_USB_OTG>;
  50                 reset-names = "phy";
  51                 status = "okay";
  52         };
  53
  54         usb2_phy1: phy@78020 {
  55                 compatible = "amlogic,meson-gxl-usb2-phy";
  56                 #phy-cells = <0>;
  57                 reg = <0x0 0x78020 0x0 0x20>;
  58                 clocks = <&clkc CLKID_USB>;
  59                 clock-names = "phy";
  60                 resets = <&reset RESET_USB_OTG>;
  61                 reset-names = "phy";
  62                 status = "okay";
  63         };
  64
  65         usb3_phy: phy@78080 {
  66                 compatible = "amlogic,meson-gxl-usb3-phy";
  67                 #phy-cells = <0>;
  68                 reg = <0x0 0x78080 0x0 0x20>;
  69                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
  70                 clocks = <&clkc CLKID_USB>, <&clkc_AO CLKID_AO_CEC_32K>;
  71                 clock-names = "phy", "peripheral";
  72                 resets = <&reset RESET_USB_OTG>, <&reset RESET_USB_OTG>;
  73                 reset-names = "phy", "peripheral";
  74                 status = "okay";
  75         };
  76 };
  77
  78 &efuse {
  79         clocks = <&clkc CLKID_EFUSE>;
  80 };
  81
  82 &ethmac {
  83         clocks = <&clkc CLKID_ETH>,
  84                  <&clkc CLKID_FCLK_DIV2>,
  85                  <&clkc CLKID_MPLL2>;
  86         clock-names = "stmmaceth", "clkin0", "clkin1";
  87
  88         mdio0: mdio {
  89                 #address-cells = <1>;
  90                 #size-cells = <0>;
  91                 compatible = "snps,dwmac-mdio";
  92         };
  93 };
  94
  95 &aobus {
  96         pinctrl_aobus: pinctrl@14 {
  97                 compatible = "amlogic,meson-gxl-aobus-pinctrl";
  98                 #address-cells = <2>;
  99                 #size-cells = <2>;
 100                 ranges;
 101
 102                 gpio_ao: bank@14 {
 103                         reg = <0x0 0x00014 0x0 0x8>,
 104                               <0x0 0x0002c 0x0 0x4>,
 105                               <0x0 0x00024 0x0 0x8>;
 106                         reg-names = "mux", "pull", "gpio";
 107                         gpio-controller;
 108                         #gpio-cells = <2>;
 109                         gpio-ranges = <&pinctrl_aobus 0 0 14>;
 110                 };
 111
 112                 uart_ao_a_pins: uart_ao_a {
 113                         mux {
 114                                 groups = "uart_tx_ao_a", "uart_rx_ao_a";
 115                                 function = "uart_ao";
 116                                 bias-disable;
 117                         };
 118                 };
 119
 120                 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
 121                         mux {
 122                                 groups = "uart_cts_ao_a",
 123                                        "uart_rts_ao_a";
 124                                 function = "uart_ao";
 125                                 bias-disable;
 126                         };
 127                 };
 128
 129                 uart_ao_b_pins: uart_ao_b {
 130                         mux {
 131                                 groups = "uart_tx_ao_b", "uart_rx_ao_b";
 132                                 function = "uart_ao_b";
 133                                 bias-disable;
 134                         };
 135                 };
 136
 137                 uart_ao_b_0_1_pins: uart_ao_b_0_1 {
 138                         mux {
 139                                 groups = "uart_tx_ao_b_0", "uart_rx_ao_b_1";
 140                                 function = "uart_ao_b";
 141                                 bias-disable;
 142                         };
 143                 };
 144
 145                 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
 146                         mux {
 147                                 groups = "uart_cts_ao_b",
 148                                        "uart_rts_ao_b";
 149                                 function = "uart_ao_b";
 150                                 bias-disable;
 151                         };
 152                 };
 153
 154                 remote_input_ao_pins: remote_input_ao {
 155                         mux {
 156                                 groups = "remote_input_ao";
 157                                 function = "remote_input_ao";
 158                                 bias-disable;
 159                         };
 160                 };
 161
 162                 i2c_ao_pins: i2c_ao {
 163                         mux {
 164                                 groups = "i2c_sck_ao",
 165                                        "i2c_sda_ao";
 166                                 function = "i2c_ao";
 167                                 bias-disable;
 168                         };
 169                 };
 170
 171                 pwm_ao_a_3_pins: pwm_ao_a_3 {
 172                         mux {
 173                                 groups = "pwm_ao_a_3";
 174                                 function = "pwm_ao_a";
 175                                 bias-disable;
 176                         };
 177                 };
 178
 179                 pwm_ao_a_8_pins: pwm_ao_a_8 {
 180                         mux {
 181                                 groups = "pwm_ao_a_8";
 182                                 function = "pwm_ao_a";
 183                                 bias-disable;
 184                         };
 185                 };
 186
 187                 pwm_ao_b_pins: pwm_ao_b {
 188                         mux {
 189                                 groups = "pwm_ao_b";
 190                                 function = "pwm_ao_b";
 191                                 bias-disable;
 192                         };
 193                 };
 194
 195                 pwm_ao_b_6_pins: pwm_ao_b_6 {
 196                         mux {
 197                                 groups = "pwm_ao_b_6";
 198                                 function = "pwm_ao_b";
 199                                 bias-disable;
 200                         };
 201                 };
 202
 203                 i2s_out_ch23_ao_pins: i2s_out_ch23_ao {
 204                         mux {
 205                                 groups = "i2s_out_ch23_ao";
 206                                 function = "i2s_out_ao";
 207                                 bias-disable;
 208                         };
 209                 };
 210
 211                 i2s_out_ch45_ao_pins: i2s_out_ch45_ao {
 212                         mux {
 213                                 groups = "i2s_out_ch45_ao";
 214                                 function = "i2s_out_ao";
 215                                 bias-disable;
 216                         };
 217                 };
 218
 219                 spdif_out_ao_6_pins: spdif_out_ao_6 {
 220                         mux {
 221                                 groups = "spdif_out_ao_6";
 222                                 function = "spdif_out_ao";
 223                                 bias-disable;
 224                         };
 225                 };
 226
 227                 spdif_out_ao_9_pins: spdif_out_ao_9 {
 228                         mux {
 229                                 groups = "spdif_out_ao_9";
 230                                 function = "spdif_out_ao";
 231                                 bias-disable;
 232                         };
 233                 };
 234
 235                 ao_cec_pins: ao_cec {
 236                         mux {
 237                                 groups = "ao_cec";
 238                                 function = "cec_ao";
 239                                 bias-disable;
 240                         };
 241                 };
 242
 243                 ee_cec_pins: ee_cec {
 244                         mux {
 245                                 groups = "ee_cec";
 246                                 function = "cec_ao";
 247                                 bias-disable;
 248                         };
 249                 };
 250         };
 251 };
 252
 253 &cec_AO {
 254         clocks = <&clkc_AO CLKID_AO_CEC_32K>;
 255         clock-names = "core";
 256 };
 257
 258 &clkc_AO {
 259         compatible = "amlogic,meson-gxl-aoclkc", "amlogic,meson-gx-aoclkc";
 260         clocks = <&xtal>, <&clkc CLKID_CLK81>;
 261         clock-names = "xtal", "mpeg-clk";
 262 };
 263
 264 &gpio_intc {
 265         compatible = "amlogic,meson-gpio-intc",
 266                      "amlogic,meson-gxl-gpio-intc";
 267         status = "okay";
 268 };
 269
 270 &hdmi_tx {
 271         compatible = "amlogic,meson-gxl-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
 272         resets = <&reset RESET_HDMITX_CAPB3>,
 273                  <&reset RESET_HDMI_SYSTEM_RESET>,
 274                  <&reset RESET_HDMI_TX>;
 275         reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
 276         clocks = <&clkc CLKID_HDMI_PCLK>,
 277                  <&clkc CLKID_CLK81>,
 278                  <&clkc CLKID_GCLK_VENCI_INT0>;
 279         clock-names = "isfr", "iahb", "venci";
 280 };
 281
 282 &sysctrl {
 283         clkc: clock-controller {
 284                 compatible = "amlogic,gxl-clkc";
 285                 #clock-cells = <1>;
 286                 clocks = <&xtal>;
 287                 clock-names = "xtal";
 288         };
 289 };
 290
 291 &i2c_A {
 292         clocks = <&clkc CLKID_I2C>;
 293 };
 294
 295 &i2c_AO {
 296         clocks = <&clkc CLKID_AO_I2C>;
 297 };
 298
 299 &i2c_B {
 300         clocks = <&clkc CLKID_I2C>;
 301 };
 302
 303 &i2c_C {
 304         clocks = <&clkc CLKID_I2C>;
 305 };
 306
 307 &periphs {
 308         pinctrl_periphs: pinctrl@4b0 {
 309                 compatible = "amlogic,meson-gxl-periphs-pinctrl";
 310                 #address-cells = <2>;
 311                 #size-cells = <2>;
 312                 ranges;
 313
 314                 gpio: bank@4b0 {
 315                         reg = <0x0 0x004b0 0x0 0x28>,
 316                               <0x0 0x004e8 0x0 0x14>,
 317                               <0x0 0x00520 0x0 0x14>,
 318                               <0x0 0x00430 0x0 0x40>;
 319                         reg-names = "mux", "pull", "pull-enable", "gpio";
 320                         gpio-controller;
 321                         #gpio-cells = <2>;
 322                         gpio-ranges = <&pinctrl_periphs 0 0 100>;
 323                 };
 324
 325                 emmc_pins: emmc {
 326                         mux-0 {
 327                                 groups = "emmc_nand_d07",
 328                                        "emmc_cmd";
 329                                 function = "emmc";
 330                                 bias-pull-up;
 331                         };
 332
 333                         mux-1 {
 334                                 groups = "emmc_clk";
 335                                 function = "emmc";
 336                                 bias-disable;
 337                         };
 338                 };
 339
 340                 emmc_ds_pins: emmc-ds {
 341                         mux {
 342                                 groups = "emmc_ds";
 343                                 function = "emmc";
 344                                 bias-pull-down;
 345                         };
 346                 };
 347
 348                 emmc_clk_gate_pins: emmc_clk_gate {
 349                         mux {
 350                                 groups = "BOOT_8";
 351                                 function = "gpio_periphs";
 352                                 bias-pull-down;
 353                         };
 354                 };
 355
 356                 nor_pins: nor {
 357                         mux {
 358                                 groups = "nor_d",
 359                                        "nor_q",
 360                                        "nor_c",
 361                                        "nor_cs";
 362                                 function = "nor";
 363                                 bias-disable;
 364                         };
 365                 };
 366
 367                 spi_pins: spi-pins {
 368                         mux {
 369                                 groups = "spi_miso",
 370                                         "spi_mosi",
 371                                         "spi_sclk";
 372                                 function = "spi";
 373                                 bias-disable;
 374                         };
 375                 };
 376
 377                 spi_ss0_pins: spi-ss0 {
 378                         mux {
 379                                 groups = "spi_ss0";
 380                                 function = "spi";
 381                                 bias-disable;
 382                         };
 383                 };
 384
 385                 sdcard_pins: sdcard {
 386                         mux-0 {
 387                                 groups = "sdcard_d0",
 388                                        "sdcard_d1",
 389                                        "sdcard_d2",
 390                                        "sdcard_d3",
 391                                        "sdcard_cmd";
 392                                 function = "sdcard";
 393                                 bias-pull-up;
 394                         };
 395
 396                         mux-1 {
 397                                 groups = "sdcard_clk";
 398                                 function = "sdcard";
 399                                 bias-disable;
 400                         };
 401                 };
 402
 403                 sdcard_clk_gate_pins: sdcard_clk_gate {
 404                         mux {
 405                                 groups = "CARD_2";
 406                                 function = "gpio_periphs";
 407                                 bias-pull-down;
 408                         };
 409                 };
 410
 411                 sdio_pins: sdio {
 412                         mux-0 {
 413                                 groups = "sdio_d0",
 414                                        "sdio_d1",
 415                                        "sdio_d2",
 416                                        "sdio_d3",
 417                                        "sdio_cmd";
 418                                 function = "sdio";
 419                                 bias-pull-up;
 420                         };
 421
 422                         mux-1 {
 423                                 groups = "sdio_clk";
 424                                 function = "sdio";
 425                                 bias-disable;
 426                         };
 427                 };
 428
 429                 sdio_clk_gate_pins: sdio_clk_gate {
 430                         mux {
 431                                 groups = "GPIOX_4";
 432                                 function = "gpio_periphs";
 433                                 bias-pull-down;
 434                         };
 435                 };
 436
 437                 sdio_irq_pins: sdio_irq {
 438                         mux {
 439                                 groups = "sdio_irq";
 440                                 function = "sdio";
 441                                 bias-disable;
 442                         };
 443                 };
 444
 445                 uart_a_pins: uart_a {
 446                         mux {
 447                                 groups = "uart_tx_a",
 448                                        "uart_rx_a";
 449                                 function = "uart_a";
 450                                 bias-disable;
 451                         };
 452                 };
 453
 454                 uart_a_cts_rts_pins: uart_a_cts_rts {
 455                         mux {
 456                                 groups = "uart_cts_a",
 457                                        "uart_rts_a";
 458                                 function = "uart_a";
 459                                 bias-disable;
 460                         };
 461                 };
 462
 463                 uart_b_pins: uart_b {
 464                         mux {
 465                                 groups = "uart_tx_b",
 466                                        "uart_rx_b";
 467                                 function = "uart_b";
 468                                 bias-disable;
 469                         };
 470                 };
 471
 472                 uart_b_cts_rts_pins: uart_b_cts_rts {
 473                         mux {
 474                                 groups = "uart_cts_b",
 475                                        "uart_rts_b";
 476                                 function = "uart_b";
 477                                 bias-disable;
 478                         };
 479                 };
 480
 481                 uart_c_pins: uart_c {
 482                         mux {
 483                                 groups = "uart_tx_c",
 484                                        "uart_rx_c";
 485                                 function = "uart_c";
 486                                 bias-disable;
 487                         };
 488                 };
 489
 490                 uart_c_cts_rts_pins: uart_c_cts_rts {
 491                         mux {
 492                                 groups = "uart_cts_c",
 493                                        "uart_rts_c";
 494                                 function = "uart_c";
 495                                 bias-disable;
 496                         };
 497                 };
 498
 499                 i2c_a_pins: i2c_a {
 500                         mux {
 501                                 groups = "i2c_sck_a",
 502                                      "i2c_sda_a";
 503                                 function = "i2c_a";
 504                                 bias-disable;
 505                         };
 506                 };
 507
 508                 i2c_b_pins: i2c_b {
 509                         mux {
 510                                 groups = "i2c_sck_b",
 511                                       "i2c_sda_b";
 512                                 function = "i2c_b";
 513                                 bias-disable;
 514                         };
 515                 };
 516
 517                 i2c_c_pins: i2c_c {
 518                         mux {
 519                                 groups = "i2c_sck_c",
 520                                       "i2c_sda_c";
 521                                 function = "i2c_c";
 522                                 bias-disable;
 523                         };
 524                 };
 525
 526                 eth_pins: eth_c {
 527                         mux {
 528                                 groups = "eth_mdio",
 529                                        "eth_mdc",
 530                                        "eth_clk_rx_clk",
 531                                        "eth_rx_dv",
 532                                        "eth_rxd0",
 533                                        "eth_rxd1",
 534                                        "eth_rxd2",
 535                                        "eth_rxd3",
 536                                        "eth_rgmii_tx_clk",
 537                                        "eth_tx_en",
 538                                        "eth_txd0",
 539                                        "eth_txd1",
 540                                        "eth_txd2",
 541                                        "eth_txd3";
 542                                 function = "eth";
 543                                 bias-disable;
 544                         };
 545                 };
 546
 547                 eth_link_led_pins: eth_link_led {
 548                         mux {
 549                                 groups = "eth_link_led";
 550                                 function = "eth_led";
 551                                 bias-disable;
 552                         };
 553                 };
 554
 555                 eth_act_led_pins: eth_act_led {
 556                         mux {
 557                                 groups = "eth_act_led";
 558                                 function = "eth_led";
 559                         };
 560                 };
 561
 562                 pwm_a_pins: pwm_a {
 563                         mux {
 564                                 groups = "pwm_a";
 565                                 function = "pwm_a";
 566                                 bias-disable;
 567                         };
 568                 };
 569
 570                 pwm_b_pins: pwm_b {
 571                         mux {
 572                                 groups = "pwm_b";
 573                                 function = "pwm_b";
 574                                 bias-disable;
 575                         };
 576                 };
 577
 578                 pwm_c_pins: pwm_c {
 579                         mux {
 580                                 groups = "pwm_c";
 581                                 function = "pwm_c";
 582                                 bias-disable;
 583                         };
 584                 };
 585
 586                 pwm_d_pins: pwm_d {
 587                         mux {
 588                                 groups = "pwm_d";
 589                                 function = "pwm_d";
 590                                 bias-disable;
 591                         };
 592                 };
 593
 594                 pwm_e_pins: pwm_e {
 595                         mux {
 596                                 groups = "pwm_e";
 597                                 function = "pwm_e";
 598                                 bias-disable;
 599                         };
 600                 };
 601
 602                 pwm_f_clk_pins: pwm_f_clk {
 603                         mux {
 604                                 groups = "pwm_f_clk";
 605                                 function = "pwm_f";
 606                                 bias-disable;
 607                         };
 608                 };
 609
 610                 pwm_f_x_pins: pwm_f_x {
 611                         mux {
 612                                 groups = "pwm_f_x";
 613                                 function = "pwm_f";
 614                                 bias-disable;
 615                         };
 616                 };
 617
 618                 hdmi_hpd_pins: hdmi_hpd {
 619                         mux {
 620                                 groups = "hdmi_hpd";
 621                                 function = "hdmi_hpd";
 622                                 bias-disable;
 623                         };
 624                 };
 625
 626                 hdmi_i2c_pins: hdmi_i2c {
 627                         mux {
 628                                 groups = "hdmi_sda", "hdmi_scl";
 629                                 function = "hdmi_i2c";
 630                                 bias-disable;
 631                         };
 632                 };
 633
 634                 i2s_am_clk_pins: i2s_am_clk {
 635                         mux {
 636                                 groups = "i2s_am_clk";
 637                                 function = "i2s_out";
 638                                 bias-disable;
 639                         };
 640                 };
 641
 642                 i2s_out_ao_clk_pins: i2s_out_ao_clk {
 643                         mux {
 644                                 groups = "i2s_out_ao_clk";
 645                                 function = "i2s_out";
 646                                 bias-disable;
 647                         };
 648                 };
 649
 650                 i2s_out_lr_clk_pins: i2s_out_lr_clk {
 651                         mux {
 652                                 groups = "i2s_out_lr_clk";
 653                                 function = "i2s_out";
 654                                 bias-disable;
 655                         };
 656                 };
 657
 658                 i2s_out_ch01_pins: i2s_out_ch01 {
 659                         mux {
 660                                 groups = "i2s_out_ch01";
 661                                 function = "i2s_out";
 662                                 bias-disable;
 663                         };
 664                 };
 665                 i2sout_ch23_z_pins: i2sout_ch23_z {
 666                         mux {
 667                                 groups = "i2sout_ch23_z";
 668                                 function = "i2s_out";
 669                                 bias-disable;
 670                         };
 671                 };
 672
 673                 i2sout_ch45_z_pins: i2sout_ch45_z {
 674                         mux {
 675                                 groups = "i2sout_ch45_z";
 676                                 function = "i2s_out";
 677                                 bias-disable;
 678                         };
 679                 };
 680
 681                 i2sout_ch67_z_pins: i2sout_ch67_z {
 682                         mux {
 683                                 groups = "i2sout_ch67_z";
 684                                 function = "i2s_out";
 685                                 bias-disable;
 686                         };
 687                 };
 688
 689                 spdif_out_h_pins: spdif_out_ao_h {
 690                         mux {
 691                                 groups = "spdif_out_h";
 692                                 function = "spdif_out";
 693                                 bias-disable;
 694                         };
 695                 };
 696         };
 697
 698         eth-phy-mux {
 699                 compatible = "mdio-mux-mmioreg", "mdio-mux";
 700                 #address-cells = <1>;
 701                 #size-cells = <0>;
 702                 reg = <0x0 0x55c 0x0 0x4>;
 703                 mux-mask = <0xffffffff>;
 704                 mdio-parent-bus = <&mdio0>;
 705
 706                 internal_mdio: mdio@e40908ff {
 707                         reg = <0xe40908ff>;
 708                         #address-cells = <1>;
 709                         #size-cells = <0>;
 710
 711                         internal_phy: ethernet-phy@8 {
 712                                 compatible = "ethernet-phy-id0181.4400";
 713                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 714                                 reg = <8>;
 715                                 max-speed = <100>;
 716                         };
 717                 };
 718
 719                 external_mdio: mdio@2009087f {
 720                         reg = <0x2009087f>;
 721                         #address-cells = <1>;
 722                         #size-cells = <0>;
 723                 };
 724         };
 725 };
 726
 727 &pwrc_vpu {
 728         resets = <&reset RESET_VIU>,
 729                  <&reset RESET_VENC>,
 730                  <&reset RESET_VCBUS>,
 731                  <&reset RESET_BT656>,
 732                  <&reset RESET_DVIN_RESET>,
 733                  <&reset RESET_RDMA>,
 734                  <&reset RESET_VENCI>,
 735                  <&reset RESET_VENCP>,
 736                  <&reset RESET_VDAC>,
 737                  <&reset RESET_VDI6>,
 738                  <&reset RESET_VENCL>,
 739                  <&reset RESET_VID_LOCK>;
 740         clocks = <&clkc CLKID_VPU>,
 741                  <&clkc CLKID_VAPB>;
 742         clock-names = "vpu", "vapb";
 743         /*
 744          * VPU clocking is provided by two identical clock paths
 745          * VPU_0 and VPU_1 muxed to a single clock by a glitch
 746          * free mux to safely change frequency while running.
 747          * Same for VAPB but with a final gate after the glitch free mux.
 748          */
 749         assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
 750                           <&clkc CLKID_VPU_0>,
 751                           <&clkc CLKID_VPU>, /* Glitch free mux */
 752                           <&clkc CLKID_VAPB_0_SEL>,
 753                           <&clkc CLKID_VAPB_0>,
 754                           <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
 755         assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
 756                                  <0>, /* Do Nothing */
 757                                  <&clkc CLKID_VPU_0>,
 758                                  <&clkc CLKID_FCLK_DIV4>,
 759                                  <0>, /* Do Nothing */
 760                                  <&clkc CLKID_VAPB_0>;
 761         assigned-clock-rates = <0>, /* Do Nothing */
 762                                <666666666>,
 763                                <0>, /* Do Nothing */
 764                                <0>, /* Do Nothing */
 765                                <250000000>,
 766                                <0>; /* Do Nothing */
 767 };
 768
 769 &saradc {
 770         compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
 771         clocks = <&xtal>,
 772                  <&clkc CLKID_SAR_ADC>,
 773                  <&clkc CLKID_SAR_ADC_CLK>,
 774                  <&clkc CLKID_SAR_ADC_SEL>;
 775         clock-names = "clkin", "core", "adc_clk", "adc_sel";
 776 };
 777
 778 &sd_emmc_a {
 779         clocks = <&clkc CLKID_SD_EMMC_A>,
 780                  <&clkc CLKID_SD_EMMC_A_CLK0>,
 781                  <&clkc CLKID_FCLK_DIV2>;
 782         clock-names = "core", "clkin0", "clkin1";
 783         resets = <&reset RESET_SD_EMMC_A>;
 784 };
 785
 786 &sd_emmc_b {
 787         clocks = <&clkc CLKID_SD_EMMC_B>,
 788                  <&clkc CLKID_SD_EMMC_B_CLK0>,
 789                  <&clkc CLKID_FCLK_DIV2>;
 790         clock-names = "core", "clkin0", "clkin1";
 791         resets = <&reset RESET_SD_EMMC_B>;
 792 };
 793
 794 &sd_emmc_c {
 795         clocks = <&clkc CLKID_SD_EMMC_C>,
 796                  <&clkc CLKID_SD_EMMC_C_CLK0>,
 797                  <&clkc CLKID_FCLK_DIV2>;
 798         clock-names = "core", "clkin0", "clkin1";
 799         resets = <&reset RESET_SD_EMMC_C>;
 800 };
 801
 802 &simplefb_hdmi {
 803         clocks = <&clkc CLKID_HDMI_PCLK>,
 804                  <&clkc CLKID_CLK81>,
 805                  <&clkc CLKID_GCLK_VENCI_INT0>;
 806 };
 807
 808 &spicc {
 809         clocks = <&clkc CLKID_SPICC>;
 810         clock-names = "core";
 811         resets = <&reset RESET_PERIPHS_SPICC>;
 812         num-cs = <1>;
 813 };
 814
 815 &spifc {
 816         clocks = <&clkc CLKID_SPI>;
 817 };
 818
 819 &uart_A {
 820         clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
 821         clock-names = "xtal", "pclk", "baud";
 822 };
 823
 824 &uart_AO {
 825         clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
 826         clock-names = "xtal", "pclk", "baud";
 827 };
 828
 829 &uart_AO_B {
 830         clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
 831         clock-names = "xtal", "pclk", "baud";
 832 };
 833
 834 &uart_B {
 835         clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
 836         clock-names = "xtal", "pclk", "baud";
 837 };
 838
 839 &uart_C {
 840         clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
 841         clock-names = "xtal", "pclk", "baud";
 842 };
 843
 844 &vpu {
 845         compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu";
 846         power-domains = <&pwrc_vpu>;
 847 };
 848
 849 &vdec {
 850         compatible = "amlogic,gxl-vdec", "amlogic,gx-vdec";
 851         clocks = <&clkc CLKID_DOS_PARSER>,
 852                  <&clkc CLKID_DOS>,
 853                  <&clkc CLKID_VDEC_1>,
 854                  <&clkc CLKID_VDEC_HEVC>;
 855         clock-names = "dos_parser", "dos", "vdec_1", "vdec_hevc";
 856         resets = <&reset RESET_PARSER>;
 857         reset-names = "esparser";
 858 };