1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2019 Linaro Ltd.
4 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 compatible = "bitmain,bm1880";
11 interrupt-parent = <&gic>;
21 compatible = "arm,cortex-a53";
23 enable-method = "psci";
28 compatible = "arm,cortex-a53";
30 enable-method = "psci";
40 reg = <0x1 0x00000000 0x0 0x20000>;
45 reg = <0x1 0x30000000 0x0 0x08000000>; // 128M
50 reg = <0x1 0x38000000 0x0 0x08000000>; // 128M
56 compatible = "arm,psci-0.2";
61 compatible = "arm,armv8-timer";
62 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
63 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
64 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
65 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
69 compatible = "simple-bus";
74 gic: interrupt-controller@50001000 {
75 compatible = "arm,gic-400";
76 reg = <0x0 0x50001000 0x0 0x1000>,
77 <0x0 0x50002000 0x0 0x2000>;
78 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
80 #interrupt-cells = <3>;
83 uart0: serial@58018000 {
84 compatible = "snps,dw-apb-uart";
85 reg = <0x0 0x58018000 0x0 0x2000>;
86 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
92 uart1: serial@5801A000 {
93 compatible = "snps,dw-apb-uart";
94 reg = <0x0 0x5801a000 0x0 0x2000>;
95 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
101 uart2: serial@5801C000 {
102 compatible = "snps,dw-apb-uart";
103 reg = <0x0 0x5801c000 0x0 0x2000>;
104 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
110 uart3: serial@5801E000 {
111 compatible = "snps,dw-apb-uart";
112 reg = <0x0 0x5801e000 0x0 0x2000>;
113 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;