sys/gnu/dts/arm64/freescale/fsl-ls1012a.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Device Tree Include file for Freescale Layerscape-1012A family SoC.
   4  *
   5  * Copyright 2016 Freescale Semiconductor, Inc.
   6  *
   7  */
   8
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/thermal/thermal.h>
  11
  12 / {
  13         compatible = "fsl,ls1012a";
  14         interrupt-parent = <&gic>;
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         aliases {
  19                 crypto = &crypto;
  20                 rtic-a = &rtic_a;
  21                 rtic-b = &rtic_b;
  22                 rtic-c = &rtic_c;
  23                 rtic-d = &rtic_d;
  24                 sec-mon = &sec_mon;
  25         };
  26
  27         cpus {
  28                 #address-cells = <1>;
  29                 #size-cells = <0>;
  30
  31                 cpu0: cpu@0 {
  32                         device_type = "cpu";
  33                         compatible = "arm,cortex-a53";
  34                         reg = <0x0>;
  35                         clocks = <&clockgen 1 0>;
  36                         #cooling-cells = <2>;
  37                         cpu-idle-states = <&CPU_PH20>;
  38                 };
  39         };
  40
  41         idle-states {
  42                 /*
  43                  * PSCI node is not added default, U-boot will add missing
  44                  * parts if it determines to use PSCI.
  45                  */
  46                 entry-method = "psci";
  47
  48                 CPU_PH20: cpu-ph20 {
  49                         compatible = "arm,idle-state";
  50                         idle-state-name = "PH20";
  51                         arm,psci-suspend-param = <0x0>;
  52                         entry-latency-us = <1000>;
  53                         exit-latency-us = <1000>;
  54                         min-residency-us = <3000>;
  55                 };
  56         };
  57
  58         sysclk: sysclk {
  59                 compatible = "fixed-clock";
  60                 #clock-cells = <0>;
  61                 clock-frequency = <125000000>;
  62                 clock-output-names = "sysclk";
  63         };
  64
  65         coreclk: coreclk {
  66                 compatible = "fixed-clock";
  67                 #clock-cells = <0>;
  68                 clock-frequency = <100000000>;
  69                 clock-output-names = "coreclk";
  70         };
  71
  72         timer {
  73                 compatible = "arm,armv8-timer";
  74                 interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
  75                              <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
  76                              <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
  77                              <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
  78         };
  79
  80         pmu {
  81                 compatible = "arm,armv8-pmuv3";
  82                 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
  83         };
  84
  85         gic: interrupt-controller@1400000 {
  86                 compatible = "arm,gic-400";
  87                 #interrupt-cells = <3>;
  88                 interrupt-controller;
  89                 reg = <0x0 0x1401000 0 0x1000>, /* GICD */
  90                       <0x0 0x1402000 0 0x2000>, /* GICC */
  91                       <0x0 0x1404000 0 0x2000>, /* GICH */
  92                       <0x0 0x1406000 0 0x2000>; /* GICV */
  93                 interrupts = <1 9 IRQ_TYPE_LEVEL_LOW>;
  94         };
  95
  96         reboot {
  97                 compatible = "syscon-reboot";
  98                 regmap = <&dcfg>;
  99                 offset = <0xb0>;
 100                 mask = <0x02>;
 101         };
 102
 103         thermal-zones {
 104                 cpu_thermal: cpu-thermal {
 105                         polling-delay-passive = <1000>;
 106                         polling-delay = <5000>;
 107                         thermal-sensors = <&tmu 0>;
 108
 109                         trips {
 110                                 cpu_alert: cpu-alert {
 111                                         temperature = <85000>;
 112                                         hysteresis = <2000>;
 113                                         type = "passive";
 114                                 };
 115
 116                                 cpu_crit: cpu-crit {
 117                                         temperature = <95000>;
 118                                         hysteresis = <2000>;
 119                                         type = "critical";
 120                                 };
 121                         };
 122
 123                         cooling-maps {
 124                                 map0 {
 125                                         trip = <&cpu_alert>;
 126                                         cooling-device =
 127                                                 <&cpu0 THERMAL_NO_LIMIT
 128                                                 THERMAL_NO_LIMIT>;
 129                                 };
 130                         };
 131                 };
 132         };
 133
 134         soc {
 135                 compatible = "simple-bus";
 136                 #address-cells = <2>;
 137                 #size-cells = <2>;
 138                 ranges;
 139
 140                 qspi: spi@1550000 {
 141                         compatible = "fsl,ls1021a-qspi";
 142                         #address-cells = <1>;
 143                         #size-cells = <0>;
 144                         reg = <0x0 0x1550000 0x0 0x10000>,
 145                                 <0x0 0x40000000 0x0 0x10000000>;
 146                         reg-names = "QuadSPI", "QuadSPI-memory";
 147                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 148                         clock-names = "qspi_en", "qspi";
 149                         clocks = <&clockgen 4 0>, <&clockgen 4 0>;
 150                         status = "disabled";
 151                 };
 152
 153                 esdhc0: esdhc@1560000 {
 154                         compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
 155                         reg = <0x0 0x1560000 0x0 0x10000>;
 156                         interrupts = <0 62 0x4>;
 157                         clocks = <&clockgen 4 0>;
 158                         voltage-ranges = <1800 1800 3300 3300>;
 159                         sdhci,auto-cmd12;
 160                         big-endian;
 161                         bus-width = <4>;
 162                         status = "disabled";
 163                 };
 164
 165                 scfg: scfg@1570000 {
 166                         compatible = "fsl,ls1012a-scfg", "syscon";
 167                         reg = <0x0 0x1570000 0x0 0x10000>;
 168                         big-endian;
 169                 };
 170
 171                 esdhc1: esdhc@1580000 {
 172                         compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
 173                         reg = <0x0 0x1580000 0x0 0x10000>;
 174                         interrupts = <0 65 0x4>;
 175                         clocks = <&clockgen 4 0>;
 176                         voltage-ranges = <1800 1800 3300 3300>;
 177                         sdhci,auto-cmd12;
 178                         big-endian;
 179                         broken-cd;
 180                         bus-width = <4>;
 181                         status = "disabled";
 182                 };
 183
 184                 crypto: crypto@1700000 {
 185                         compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
 186                                      "fsl,sec-v4.0";
 187                         fsl,sec-era = <8>;
 188                         #address-cells = <1>;
 189                         #size-cells = <1>;
 190                         ranges = <0x0 0x00 0x1700000 0x100000>;
 191                         reg = <0x00 0x1700000 0x0 0x100000>;
 192                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 193
 194                         sec_jr0: jr@10000 {
 195                                 compatible = "fsl,sec-v5.4-job-ring",
 196                                              "fsl,sec-v5.0-job-ring",
 197                                              "fsl,sec-v4.0-job-ring";
 198                                 reg        = <0x10000 0x10000>;
 199                                 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 200                         };
 201
 202                         sec_jr1: jr@20000 {
 203                                 compatible = "fsl,sec-v5.4-job-ring",
 204                                              "fsl,sec-v5.0-job-ring",
 205                                              "fsl,sec-v4.0-job-ring";
 206                                 reg        = <0x20000 0x10000>;
 207                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 208                         };
 209
 210                         sec_jr2: jr@30000 {
 211                                 compatible = "fsl,sec-v5.4-job-ring",
 212                                              "fsl,sec-v5.0-job-ring",
 213                                              "fsl,sec-v4.0-job-ring";
 214                                 reg        = <0x30000 0x10000>;
 215                                 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 216                         };
 217
 218                         sec_jr3: jr@40000 {
 219                                 compatible = "fsl,sec-v5.4-job-ring",
 220                                              "fsl,sec-v5.0-job-ring",
 221                                              "fsl,sec-v4.0-job-ring";
 222                                 reg        = <0x40000 0x10000>;
 223                                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 224                         };
 225
 226                         rtic@60000 {
 227                                 compatible = "fsl,sec-v5.4-rtic",
 228                                              "fsl,sec-v5.0-rtic",
 229                                              "fsl,sec-v4.0-rtic";
 230                                 #address-cells = <1>;
 231                                 #size-cells = <1>;
 232                                 reg = <0x60000 0x100 0x60e00 0x18>;
 233                                 ranges = <0x0 0x60100 0x500>;
 234
 235                                 rtic_a: rtic-a@0 {
 236                                         compatible = "fsl,sec-v5.4-rtic-memory",
 237                                                      "fsl,sec-v5.0-rtic-memory",
 238                                                      "fsl,sec-v4.0-rtic-memory";
 239                                         reg = <0x00 0x20 0x100 0x100>;
 240                                 };
 241
 242                                 rtic_b: rtic-b@20 {
 243                                         compatible = "fsl,sec-v5.4-rtic-memory",
 244                                                      "fsl,sec-v5.0-rtic-memory",
 245                                                      "fsl,sec-v4.0-rtic-memory";
 246                                         reg = <0x20 0x20 0x200 0x100>;
 247                                 };
 248
 249                                 rtic_c: rtic-c@40 {
 250                                         compatible = "fsl,sec-v5.4-rtic-memory",
 251                                                      "fsl,sec-v5.0-rtic-memory",
 252                                                      "fsl,sec-v4.0-rtic-memory";
 253                                         reg = <0x40 0x20 0x300 0x100>;
 254                                 };
 255
 256                                 rtic_d: rtic-d@60 {
 257                                         compatible = "fsl,sec-v5.4-rtic-memory",
 258                                                      "fsl,sec-v5.0-rtic-memory",
 259                                                      "fsl,sec-v4.0-rtic-memory";
 260                                         reg = <0x60 0x20 0x400 0x100>;
 261                                 };
 262                         };
 263                 };
 264
 265                 sec_mon: sec_mon@1e90000 {
 266                         compatible = "fsl,sec-v5.4-mon", "fsl,sec-v5.0-mon",
 267                                      "fsl,sec-v4.0-mon";
 268                         reg = <0x0 0x1e90000 0x0 0x10000>;
 269                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
 270                                      <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 271                 };
 272
 273                 dcfg: dcfg@1ee0000 {
 274                         compatible = "fsl,ls1012a-dcfg",
 275                                      "syscon";
 276                         reg = <0x0 0x1ee0000 0x0 0x10000>;
 277                         big-endian;
 278                 };
 279
 280                 clockgen: clocking@1ee1000 {
 281                         compatible = "fsl,ls1012a-clockgen";
 282                         reg = <0x0 0x1ee1000 0x0 0x1000>;
 283                         #clock-cells = <2>;
 284                         clocks = <&sysclk &coreclk>;
 285                         clock-names = "sysclk", "coreclk";
 286                 };
 287
 288                 tmu: tmu@1f00000 {
 289                         compatible = "fsl,qoriq-tmu";
 290                         reg = <0x0 0x1f00000 0x0 0x10000>;
 291                         interrupts = <0 33 0x4>;
 292                         fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
 293                         fsl,tmu-calibration = <0x00000000 0x00000026
 294                                                0x00000001 0x0000002d
 295                                                0x00000002 0x00000032
 296                                                0x00000003 0x00000039
 297                                                0x00000004 0x0000003f
 298                                                0x00000005 0x00000046
 299                                                0x00000006 0x0000004d
 300                                                0x00000007 0x00000054
 301                                                0x00000008 0x0000005a
 302                                                0x00000009 0x00000061
 303                                                0x0000000a 0x0000006a
 304                                                0x0000000b 0x00000071
 305
 306                                                0x00010000 0x00000025
 307                                                0x00010001 0x0000002c
 308                                                0x00010002 0x00000035
 309                                                0x00010003 0x0000003d
 310                                                0x00010004 0x00000045
 311                                                0x00010005 0x0000004e
 312                                                0x00010006 0x00000057
 313                                                0x00010007 0x00000061
 314                                                0x00010008 0x0000006b
 315                                                0x00010009 0x00000076
 316
 317                                                0x00020000 0x00000029
 318                                                0x00020001 0x00000033
 319                                                0x00020002 0x0000003d
 320                                                0x00020003 0x00000049
 321                                                0x00020004 0x00000056
 322                                                0x00020005 0x00000061
 323                                                0x00020006 0x0000006d
 324
 325                                                0x00030000 0x00000021
 326                                                0x00030001 0x0000002a
 327                                                0x00030002 0x0000003c
 328                                                0x00030003 0x0000004e>;
 329                         big-endian;
 330                         #thermal-sensor-cells = <1>;
 331                 };
 332
 333                 i2c0: i2c@2180000 {
 334                         compatible = "fsl,vf610-i2c";
 335                         #address-cells = <1>;
 336                         #size-cells = <0>;
 337                         reg = <0x0 0x2180000 0x0 0x10000>;
 338                         interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
 339                         clocks = <&clockgen 4 3>;
 340                         status = "disabled";
 341                 };
 342
 343                 i2c1: i2c@2190000 {
 344                         compatible = "fsl,vf610-i2c";
 345                         #address-cells = <1>;
 346                         #size-cells = <0>;
 347                         reg = <0x0 0x2190000 0x0 0x10000>;
 348                         interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
 349                         clocks = <&clockgen 4 3>;
 350                         status = "disabled";
 351                 };
 352
 353                 dspi: spi@2100000 {
 354                         compatible = "fsl,ls1012a-dspi", "fsl,ls1021a-v1.0-dspi";
 355                         #address-cells = <1>;
 356                         #size-cells = <0>;
 357                         reg = <0x0 0x2100000 0x0 0x10000>;
 358                         interrupts = <0 64 IRQ_TYPE_LEVEL_HIGH>;
 359                         clock-names = "dspi";
 360                         clocks = <&clockgen 4 0>;
 361                         spi-num-chipselects = <5>;
 362                         big-endian;
 363                         status = "disabled";
 364                 };
 365
 366                 duart0: serial@21c0500 {
 367                         compatible = "fsl,ns16550", "ns16550a";
 368                         reg = <0x00 0x21c0500 0x0 0x100>;
 369                         interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
 370                         clocks = <&clockgen 4 0>;
 371                         status = "disabled";
 372                 };
 373
 374                 duart1: serial@21c0600 {
 375                         compatible = "fsl,ns16550", "ns16550a";
 376                         reg = <0x00 0x21c0600 0x0 0x100>;
 377                         interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
 378                         clocks = <&clockgen 4 0>;
 379                         status = "disabled";
 380                 };
 381
 382                 gpio0: gpio@2300000 {
 383                         compatible = "fsl,qoriq-gpio";
 384                         reg = <0x0 0x2300000 0x0 0x10000>;
 385                         interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>;
 386                         gpio-controller;
 387                         #gpio-cells = <2>;
 388                         interrupt-controller;
 389                         #interrupt-cells = <2>;
 390                 };
 391
 392                 gpio1: gpio@2310000 {
 393                         compatible = "fsl,qoriq-gpio";
 394                         reg = <0x0 0x2310000 0x0 0x10000>;
 395                         interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
 396                         gpio-controller;
 397                         #gpio-cells = <2>;
 398                         interrupt-controller;
 399                         #interrupt-cells = <2>;
 400                 };
 401
 402                 wdog0: wdog@2ad0000 {
 403                         compatible = "fsl,ls1012a-wdt",
 404                                      "fsl,imx21-wdt";
 405                         reg = <0x0 0x2ad0000 0x0 0x10000>;
 406                         interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
 407                         clocks = <&clockgen 4 0>;
 408                         big-endian;
 409                 };
 410
 411                 sai1: sai@2b50000 {
 412                         #sound-dai-cells = <0>;
 413                         compatible = "fsl,vf610-sai";
 414                         reg = <0x0 0x2b50000 0x0 0x10000>;
 415                         interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
 416                         clocks = <&clockgen 4 3>, <&clockgen 4 3>,
 417                                  <&clockgen 4 3>, <&clockgen 4 3>;
 418                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 419                         dma-names = "tx", "rx";
 420                         dmas = <&edma0 1 47>,
 421                                <&edma0 1 46>;
 422                         status = "disabled";
 423                 };
 424
 425                 sai2: sai@2b60000 {
 426                         #sound-dai-cells = <0>;
 427                         compatible = "fsl,vf610-sai";
 428                         reg = <0x0 0x2b60000 0x0 0x10000>;
 429                         interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
 430                         clocks = <&clockgen 4 3>, <&clockgen 4 3>,
 431                                  <&clockgen 4 3>, <&clockgen 4 3>;
 432                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 433                         dma-names = "tx", "rx";
 434                         dmas = <&edma0 1 45>,
 435                                <&edma0 1 44>;
 436                         status = "disabled";
 437                 };
 438
 439                 edma0: edma@2c00000 {
 440                         #dma-cells = <2>;
 441                         compatible = "fsl,vf610-edma";
 442                         reg = <0x0 0x2c00000 0x0 0x10000>,
 443                               <0x0 0x2c10000 0x0 0x10000>,
 444                               <0x0 0x2c20000 0x0 0x10000>;
 445                         interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>,
 446                                      <0 103 IRQ_TYPE_LEVEL_HIGH>;
 447                         interrupt-names = "edma-tx", "edma-err";
 448                         dma-channels = <32>;
 449                         big-endian;
 450                         clock-names = "dmamux0", "dmamux1";
 451                         clocks = <&clockgen 4 3>,
 452                                  <&clockgen 4 3>;
 453                 };
 454
 455                 usb0: usb3@2f00000 {
 456                         compatible = "snps,dwc3";
 457                         reg = <0x0 0x2f00000 0x0 0x10000>;
 458                         interrupts = <0 60 0x4>;
 459                         dr_mode = "host";
 460                         snps,quirk-frame-length-adjustment = <0x20>;
 461                         snps,dis_rxdet_inp3_quirk;
 462                         snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
 463                 };
 464
 465                 sata: sata@3200000 {
 466                         compatible = "fsl,ls1012a-ahci", "fsl,ls1043a-ahci";
 467                         reg = <0x0 0x3200000 0x0 0x10000>,
 468                                 <0x0 0x20140520 0x0 0x4>;
 469                         reg-names = "ahci", "sata-ecc";
 470                         interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
 471                         clocks = <&clockgen 4 0>;
 472                         dma-coherent;
 473                         status = "disabled";
 474                 };
 475
 476                 usb1: usb2@8600000 {
 477                         compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
 478                         reg = <0x0 0x8600000 0x0 0x1000>;
 479                         interrupts = <0 139 0x4>;
 480                         dr_mode = "host";
 481                         phy_type = "ulpi";
 482                 };
 483
 484                 msi: msi-controller1@1572000 {
 485                         compatible = "fsl,ls1012a-msi";
 486                         reg = <0x0 0x1572000 0x0 0x8>;
 487                         msi-controller;
 488                         interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>;
 489                 };
 490
 491                 pcie: pcie@3400000 {
 492                         compatible = "fsl,ls1012a-pcie";
 493                         reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
 494                                0x40 0x00000000 0x0 0x00002000>; /* configuration space */
 495                         reg-names = "regs", "config";
 496                         interrupts = <0 118 0x4>, /* controller interrupt */
 497                                      <0 117 0x4>; /* PME interrupt */
 498                         interrupt-names = "aer", "pme";
 499                         #address-cells = <3>;
 500                         #size-cells = <2>;
 501                         device_type = "pci";
 502                         num-viewport = <2>;
 503                         bus-range = <0x0 0xff>;
 504                         ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
 505                                   0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 506                         msi-parent = <&msi>;
 507                         #interrupt-cells = <1>;
 508                         interrupt-map-mask = <0 0 0 7>;
 509                         interrupt-map = <0000 0 0 1 &gic 0 110 IRQ_TYPE_LEVEL_HIGH>,
 510                                         <0000 0 0 2 &gic 0 111 IRQ_TYPE_LEVEL_HIGH>,
 511                                         <0000 0 0 3 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>,
 512                                         <0000 0 0 4 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
 513                         status = "disabled";
 514                 };
 515         };
 516
 517         firmware {
 518                 optee {
 519                         compatible = "linaro,optee-tz";
 520                         method = "smc";
 521                 };
 522         };
 523 };