sys/gnu/dts/arm64/freescale/fsl-ls1028a.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Device Tree Include file for NXP Layerscape-1028A family SoC.
   4  *
   5  * Copyright 2018 NXP
   6  *
   7  * Harninder Rai <harninder.rai@nxp.com>
   8  *
   9  */
  10
  11 #include <dt-bindings/interrupt-controller/arm-gic.h>
  12 #include <dt-bindings/thermal/thermal.h>
  13
  14 / {
  15         compatible = "fsl,ls1028a";
  16         interrupt-parent = <&gic>;
  17         #address-cells = <2>;
  18         #size-cells = <2>;
  19
  20         cpus {
  21                 #address-cells = <1>;
  22                 #size-cells = <0>;
  23
  24                 cpu0: cpu@0 {
  25                         device_type = "cpu";
  26                         compatible = "arm,cortex-a72";
  27                         reg = <0x0>;
  28                         enable-method = "psci";
  29                         clocks = <&clockgen 1 0>;
  30                         next-level-cache = <&l2>;
  31                         cpu-idle-states = <&CPU_PW20>;
  32                         #cooling-cells = <2>;
  33                 };
  34
  35                 cpu1: cpu@1 {
  36                         device_type = "cpu";
  37                         compatible = "arm,cortex-a72";
  38                         reg = <0x1>;
  39                         enable-method = "psci";
  40                         clocks = <&clockgen 1 0>;
  41                         next-level-cache = <&l2>;
  42                         cpu-idle-states = <&CPU_PW20>;
  43                         #cooling-cells = <2>;
  44                 };
  45
  46                 l2: l2-cache {
  47                         compatible = "cache";
  48                 };
  49         };
  50
  51         idle-states {
  52                 /*
  53                  * PSCI node is not added default, U-boot will add missing
  54                  * parts if it determines to use PSCI.
  55                  */
  56                 entry-method = "psci";
  57
  58                 CPU_PW20: cpu-pw20 {
  59                           compatible = "arm,idle-state";
  60                           idle-state-name = "PW20";
  61                           arm,psci-suspend-param = <0x0>;
  62                           entry-latency-us = <2000>;
  63                           exit-latency-us = <2000>;
  64                           min-residency-us = <6000>;
  65                 };
  66         };
  67
  68         sysclk: clock-sysclk {
  69                 compatible = "fixed-clock";
  70                 #clock-cells = <0>;
  71                 clock-frequency = <100000000>;
  72                 clock-output-names = "sysclk";
  73         };
  74
  75         osc_27m: clock-osc-27m {
  76                 compatible = "fixed-clock";
  77                 #clock-cells = <0>;
  78                 clock-frequency = <27000000>;
  79                 clock-output-names = "phy_27m";
  80         };
  81
  82         dpclk: clock-controller@f1f0000 {
  83                 compatible = "fsl,ls1028a-plldig";
  84                 reg = <0x0 0xf1f0000 0x0 0xffff>;
  85                 #clock-cells = <0>;
  86                 clocks = <&osc_27m>;
  87         };
  88
  89         reboot {
  90                 compatible ="syscon-reboot";
  91                 regmap = <&rst>;
  92                 offset = <0xb0>;
  93                 mask = <0x02>;
  94         };
  95
  96         timer {
  97                 compatible = "arm,armv8-timer";
  98                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
  99                                           IRQ_TYPE_LEVEL_LOW)>,
 100                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
 101                                           IRQ_TYPE_LEVEL_LOW)>,
 102                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
 103                                           IRQ_TYPE_LEVEL_LOW)>,
 104                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
 105                                           IRQ_TYPE_LEVEL_LOW)>;
 106         };
 107
 108         pmu {
 109                 compatible = "arm,cortex-a72-pmu";
 110                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
 111         };
 112
 113         gic: interrupt-controller@6000000 {
 114                 compatible= "arm,gic-v3";
 115                 #address-cells = <2>;
 116                 #size-cells = <2>;
 117                 ranges;
 118                 reg= <0x0 0x06000000 0 0x10000>, /* GIC Dist */
 119                         <0x0 0x06040000 0 0x40000>; /* GIC Redistributor */
 120                 #interrupt-cells= <3>;
 121                 interrupt-controller;
 122                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
 123                                          IRQ_TYPE_LEVEL_LOW)>;
 124                 its: gic-its@6020000 {
 125                         compatible = "arm,gic-v3-its";
 126                         msi-controller;
 127                         reg = <0x0 0x06020000 0 0x20000>;/* GIC Translater */
 128                 };
 129         };
 130
 131         thermal-zones {
 132                 core-cluster {
 133                         polling-delay-passive = <1000>;
 134                         polling-delay = <5000>;
 135                         thermal-sensors = <&tmu 0>;
 136
 137                         trips {
 138                                 core_cluster_alert: core-cluster-alert {
 139                                         temperature = <85000>;
 140                                         hysteresis = <2000>;
 141                                         type = "passive";
 142                                 };
 143
 144                                 core_cluster_crit: core-cluster-crit {
 145                                         temperature = <95000>;
 146                                         hysteresis = <2000>;
 147                                         type = "critical";
 148                                 };
 149                         };
 150
 151                         cooling-maps {
 152                                 map0 {
 153                                         trip = <&core_cluster_alert>;
 154                                         cooling-device =
 155                                                 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 156                                                 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 157                                 };
 158                         };
 159                 };
 160         };
 161
 162         soc: soc {
 163                 compatible = "simple-bus";
 164                 #address-cells = <2>;
 165                 #size-cells = <2>;
 166                 ranges;
 167
 168                 ddr: memory-controller@1080000 {
 169                         compatible = "fsl,qoriq-memory-controller";
 170                         reg = <0x0 0x1080000 0x0 0x1000>;
 171                         interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 172                         big-endian;
 173                 };
 174
 175                 dcfg: syscon@1e00000 {
 176                         compatible = "fsl,ls1028a-dcfg", "syscon";
 177                         reg = <0x0 0x1e00000 0x0 0x10000>;
 178                         little-endian;
 179                 };
 180
 181                 rst: syscon@1e60000 {
 182                         compatible = "syscon";
 183                         reg = <0x0 0x1e60000 0x0 0x10000>;
 184                         little-endian;
 185                 };
 186
 187                 scfg: syscon@1fc0000 {
 188                         compatible = "fsl,ls1028a-scfg", "syscon";
 189                         reg = <0x0 0x1fc0000 0x0 0x10000>;
 190                         big-endian;
 191                 };
 192
 193                 clockgen: clock-controller@1300000 {
 194                         compatible = "fsl,ls1028a-clockgen";
 195                         reg = <0x0 0x1300000 0x0 0xa0000>;
 196                         #clock-cells = <2>;
 197                         clocks = <&sysclk>;
 198                 };
 199
 200                 i2c0: i2c@2000000 {
 201                         compatible = "fsl,vf610-i2c";
 202                         #address-cells = <1>;
 203                         #size-cells = <0>;
 204                         reg = <0x0 0x2000000 0x0 0x10000>;
 205                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 206                         clocks = <&clockgen 4 3>;
 207                         status = "disabled";
 208                 };
 209
 210                 i2c1: i2c@2010000 {
 211                         compatible = "fsl,vf610-i2c";
 212                         #address-cells = <1>;
 213                         #size-cells = <0>;
 214                         reg = <0x0 0x2010000 0x0 0x10000>;
 215                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 216                         clocks = <&clockgen 4 3>;
 217                         status = "disabled";
 218                 };
 219
 220                 i2c2: i2c@2020000 {
 221                         compatible = "fsl,vf610-i2c";
 222                         #address-cells = <1>;
 223                         #size-cells = <0>;
 224                         reg = <0x0 0x2020000 0x0 0x10000>;
 225                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 226                         clocks = <&clockgen 4 3>;
 227                         status = "disabled";
 228                 };
 229
 230                 i2c3: i2c@2030000 {
 231                         compatible = "fsl,vf610-i2c";
 232                         #address-cells = <1>;
 233                         #size-cells = <0>;
 234                         reg = <0x0 0x2030000 0x0 0x10000>;
 235                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 236                         clocks = <&clockgen 4 3>;
 237                         status = "disabled";
 238                 };
 239
 240                 i2c4: i2c@2040000 {
 241                         compatible = "fsl,vf610-i2c";
 242                         #address-cells = <1>;
 243                         #size-cells = <0>;
 244                         reg = <0x0 0x2040000 0x0 0x10000>;
 245                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 246                         clocks = <&clockgen 4 3>;
 247                         status = "disabled";
 248                 };
 249
 250                 i2c5: i2c@2050000 {
 251                         compatible = "fsl,vf610-i2c";
 252                         #address-cells = <1>;
 253                         #size-cells = <0>;
 254                         reg = <0x0 0x2050000 0x0 0x10000>;
 255                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 256                         clocks = <&clockgen 4 3>;
 257                         status = "disabled";
 258                 };
 259
 260                 i2c6: i2c@2060000 {
 261                         compatible = "fsl,vf610-i2c";
 262                         #address-cells = <1>;
 263                         #size-cells = <0>;
 264                         reg = <0x0 0x2060000 0x0 0x10000>;
 265                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 266                         clocks = <&clockgen 4 3>;
 267                         status = "disabled";
 268                 };
 269
 270                 i2c7: i2c@2070000 {
 271                         compatible = "fsl,vf610-i2c";
 272                         #address-cells = <1>;
 273                         #size-cells = <0>;
 274                         reg = <0x0 0x2070000 0x0 0x10000>;
 275                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 276                         clocks = <&clockgen 4 3>;
 277                         status = "disabled";
 278                 };
 279
 280                 fspi: spi@20c0000 {
 281                         compatible = "nxp,lx2160a-fspi";
 282                         #address-cells = <1>;
 283                         #size-cells = <0>;
 284                         reg = <0x0 0x20c0000 0x0 0x10000>,
 285                               <0x0 0x20000000 0x0 0x10000000>;
 286                         reg-names = "fspi_base", "fspi_mmap";
 287                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 288                         clocks = <&clockgen 4 3>, <&clockgen 4 3>;
 289                         clock-names = "fspi_en", "fspi";
 290                         status = "disabled";
 291                 };
 292
 293                 dspi0: spi@2100000 {
 294                         compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi";
 295                         #address-cells = <1>;
 296                         #size-cells = <0>;
 297                         reg = <0x0 0x2100000 0x0 0x10000>;
 298                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 299                         clock-names = "dspi";
 300                         clocks = <&clockgen 4 1>;
 301                         dmas = <&edma0 0 62>, <&edma0 0 60>;
 302                         dma-names = "tx", "rx";
 303                         spi-num-chipselects = <4>;
 304                         little-endian;
 305                         status = "disabled";
 306                 };
 307
 308                 dspi1: spi@2110000 {
 309                         compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi";
 310                         #address-cells = <1>;
 311                         #size-cells = <0>;
 312                         reg = <0x0 0x2110000 0x0 0x10000>;
 313                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 314                         clock-names = "dspi";
 315                         clocks = <&clockgen 4 1>;
 316                         dmas = <&edma0 0 58>, <&edma0 0 56>;
 317                         dma-names = "tx", "rx";
 318                         spi-num-chipselects = <4>;
 319                         little-endian;
 320                         status = "disabled";
 321                 };
 322
 323                 dspi2: spi@2120000 {
 324                         compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi";
 325                         #address-cells = <1>;
 326                         #size-cells = <0>;
 327                         reg = <0x0 0x2120000 0x0 0x10000>;
 328                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 329                         clock-names = "dspi";
 330                         clocks = <&clockgen 4 1>;
 331                         dmas = <&edma0 0 54>, <&edma0 0 2>;
 332                         dma-names = "tx", "rx";
 333                         spi-num-chipselects = <3>;
 334                         little-endian;
 335                         status = "disabled";
 336                 };
 337
 338                 esdhc: mmc@2140000 {
 339                         compatible = "fsl,ls1028a-esdhc", "fsl,esdhc";
 340                         reg = <0x0 0x2140000 0x0 0x10000>;
 341                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 342                         clock-frequency = <0>; /* fixed up by bootloader */
 343                         clocks = <&clockgen 2 1>;
 344                         voltage-ranges = <1800 1800 3300 3300>;
 345                         sdhci,auto-cmd12;
 346                         little-endian;
 347                         bus-width = <4>;
 348                         status = "disabled";
 349                 };
 350
 351                 esdhc1: mmc@2150000 {
 352                         compatible = "fsl,ls1028a-esdhc", "fsl,esdhc";
 353                         reg = <0x0 0x2150000 0x0 0x10000>;
 354                         interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 355                         clock-frequency = <0>; /* fixed up by bootloader */
 356                         clocks = <&clockgen 2 1>;
 357                         voltage-ranges = <1800 1800 3300 3300>;
 358                         sdhci,auto-cmd12;
 359                         broken-cd;
 360                         little-endian;
 361                         bus-width = <4>;
 362                         status = "disabled";
 363                 };
 364
 365                 duart0: serial@21c0500 {
 366                         compatible = "fsl,ns16550", "ns16550a";
 367                         reg = <0x00 0x21c0500 0x0 0x100>;
 368                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 369                         clocks = <&clockgen 4 1>;
 370                         status = "disabled";
 371                 };
 372
 373                 duart1: serial@21c0600 {
 374                         compatible = "fsl,ns16550", "ns16550a";
 375                         reg = <0x00 0x21c0600 0x0 0x100>;
 376                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 377                         clocks = <&clockgen 4 1>;
 378                         status = "disabled";
 379                 };
 380
 381
 382                 lpuart0: serial@2260000 {
 383                         compatible = "fsl,ls1028a-lpuart";
 384                         reg = <0x0 0x2260000 0x0 0x1000>;
 385                         interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
 386                         clocks = <&clockgen 4 1>;
 387                         clock-names = "ipg";
 388                         dma-names = "rx","tx";
 389                         dmas = <&edma0 1 32>,
 390                                <&edma0 1 33>;
 391                         status = "disabled";
 392                 };
 393
 394                 lpuart1: serial@2270000 {
 395                         compatible = "fsl,ls1028a-lpuart";
 396                         reg = <0x0 0x2270000 0x0 0x1000>;
 397                         interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
 398                         clocks = <&clockgen 4 1>;
 399                         clock-names = "ipg";
 400                         dma-names = "rx","tx";
 401                         dmas = <&edma0 1 30>,
 402                                <&edma0 1 31>;
 403                         status = "disabled";
 404                 };
 405
 406                 lpuart2: serial@2280000 {
 407                         compatible = "fsl,ls1028a-lpuart";
 408                         reg = <0x0 0x2280000 0x0 0x1000>;
 409                         interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
 410                         clocks = <&clockgen 4 1>;
 411                         clock-names = "ipg";
 412                         dma-names = "rx","tx";
 413                         dmas = <&edma0 1 28>,
 414                                <&edma0 1 29>;
 415                         status = "disabled";
 416                 };
 417
 418                 lpuart3: serial@2290000 {
 419                         compatible = "fsl,ls1028a-lpuart";
 420                         reg = <0x0 0x2290000 0x0 0x1000>;
 421                         interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
 422                         clocks = <&clockgen 4 1>;
 423                         clock-names = "ipg";
 424                         dma-names = "rx","tx";
 425                         dmas = <&edma0 1 26>,
 426                                <&edma0 1 27>;
 427                         status = "disabled";
 428                 };
 429
 430                 lpuart4: serial@22a0000 {
 431                         compatible = "fsl,ls1028a-lpuart";
 432                         reg = <0x0 0x22a0000 0x0 0x1000>;
 433                         interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
 434                         clocks = <&clockgen 4 1>;
 435                         clock-names = "ipg";
 436                         dma-names = "rx","tx";
 437                         dmas = <&edma0 1 24>,
 438                                <&edma0 1 25>;
 439                         status = "disabled";
 440                 };
 441
 442                 lpuart5: serial@22b0000 {
 443                         compatible = "fsl,ls1028a-lpuart";
 444                         reg = <0x0 0x22b0000 0x0 0x1000>;
 445                         interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
 446                         clocks = <&clockgen 4 1>;
 447                         clock-names = "ipg";
 448                         dma-names = "rx","tx";
 449                         dmas = <&edma0 1 22>,
 450                                <&edma0 1 23>;
 451                         status = "disabled";
 452                 };
 453
 454                 edma0: dma-controller@22c0000 {
 455                         #dma-cells = <2>;
 456                         compatible = "fsl,ls1028a-edma", "fsl,vf610-edma";
 457                         reg = <0x0 0x22c0000 0x0 0x10000>,
 458                               <0x0 0x22d0000 0x0 0x10000>,
 459                               <0x0 0x22e0000 0x0 0x10000>;
 460                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
 461                                      <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 462                         interrupt-names = "edma-tx", "edma-err";
 463                         dma-channels = <32>;
 464                         clock-names = "dmamux0", "dmamux1";
 465                         clocks = <&clockgen 4 1>,
 466                                  <&clockgen 4 1>;
 467                 };
 468
 469                 gpio1: gpio@2300000 {
 470                         compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio";
 471                         reg = <0x0 0x2300000 0x0 0x10000>;
 472                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 473                         gpio-controller;
 474                         #gpio-cells = <2>;
 475                         interrupt-controller;
 476                         #interrupt-cells = <2>;
 477                         little-endian;
 478                 };
 479
 480                 gpio2: gpio@2310000 {
 481                         compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio";
 482                         reg = <0x0 0x2310000 0x0 0x10000>;
 483                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 484                         gpio-controller;
 485                         #gpio-cells = <2>;
 486                         interrupt-controller;
 487                         #interrupt-cells = <2>;
 488                         little-endian;
 489                 };
 490
 491                 gpio3: gpio@2320000 {
 492                         compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio";
 493                         reg = <0x0 0x2320000 0x0 0x10000>;
 494                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 495                         gpio-controller;
 496                         #gpio-cells = <2>;
 497                         interrupt-controller;
 498                         #interrupt-cells = <2>;
 499                         little-endian;
 500                 };
 501
 502                 usb0: usb@3100000 {
 503                         compatible = "fsl,ls1028a-dwc3", "snps,dwc3";
 504                         reg = <0x0 0x3100000 0x0 0x10000>;
 505                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 506                         dr_mode = "host";
 507                         snps,dis_rxdet_inp3_quirk;
 508                         snps,quirk-frame-length-adjustment = <0x20>;
 509                         snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
 510                 };
 511
 512                 usb1: usb@3110000 {
 513                         compatible = "fsl,ls1028a-dwc3", "snps,dwc3";
 514                         reg = <0x0 0x3110000 0x0 0x10000>;
 515                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 516                         dr_mode = "host";
 517                         snps,dis_rxdet_inp3_quirk;
 518                         snps,quirk-frame-length-adjustment = <0x20>;
 519                         snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
 520                 };
 521
 522                 sata: sata@3200000 {
 523                         compatible = "fsl,ls1028a-ahci";
 524                         reg = <0x0 0x3200000 0x0 0x10000>,
 525                                 <0x7 0x100520 0x0 0x4>;
 526                         reg-names = "ahci", "sata-ecc";
 527                         interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
 528                         clocks = <&clockgen 4 1>;
 529                         status = "disabled";
 530                 };
 531
 532                 pcie@3400000 {
 533                         compatible = "fsl,ls1028a-pcie";
 534                         reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
 535                                0x80 0x00000000 0x0 0x00002000>; /* configuration space */
 536                         reg-names = "regs", "config";
 537                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
 538                                      <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
 539                         interrupt-names = "pme", "aer";
 540                         #address-cells = <3>;
 541                         #size-cells = <2>;
 542                         device_type = "pci";
 543                         dma-coherent;
 544                         num-viewport = <8>;
 545                         bus-range = <0x0 0xff>;
 546                         ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 0x00010000   /* downstream I/O */
 547                                   0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 548                         msi-parent = <&its>;
 549                         #interrupt-cells = <1>;
 550                         interrupt-map-mask = <0 0 0 7>;
 551                         interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 552                                         <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 553                                         <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 554                                         <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 555                         iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
 556                         status = "disabled";
 557                 };
 558
 559                 pcie@3500000 {
 560                         compatible = "fsl,ls1028a-pcie";
 561                         reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
 562                                0x88 0x00000000 0x0 0x00002000>; /* configuration space */
 563                         reg-names = "regs", "config";
 564                         interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 565                                      <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 566                         interrupt-names = "pme", "aer";
 567                         #address-cells = <3>;
 568                         #size-cells = <2>;
 569                         device_type = "pci";
 570                         dma-coherent;
 571                         num-viewport = <8>;
 572                         bus-range = <0x0 0xff>;
 573                         ranges = <0x81000000 0x0 0x00000000 0x88 0x00010000 0x0 0x00010000   /* downstream I/O */
 574                                   0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 575                         msi-parent = <&its>;
 576                         #interrupt-cells = <1>;
 577                         interrupt-map-mask = <0 0 0 7>;
 578                         interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 579                                         <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 580                                         <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 581                                         <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 582                         iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
 583                         status = "disabled";
 584                 };
 585
 586                 smmu: iommu@5000000 {
 587                         compatible = "arm,mmu-500";
 588                         reg = <0 0x5000000 0 0x800000>;
 589                         #global-interrupts = <8>;
 590                         #iommu-cells = <1>;
 591                         stream-match-mask = <0x7c00>;
 592                         /* global secure fault */
 593                         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 594                         /* combined secure interrupt */
 595                                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 596                         /* global non-secure fault */
 597                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 598                         /* combined non-secure interrupt */
 599                                      <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 600                         /* performance counter interrupts 0-7 */
 601                                      <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
 602                                      <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
 603                         /* per context interrupt, 64 interrupts */
 604                                      <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
 605                                      <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
 606                                      <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
 607                                      <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
 608                                      <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
 609                                      <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
 610                                      <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
 611                                      <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
 612                                      <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
 613                                      <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
 614                                      <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
 615                                      <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
 616                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
 617                                      <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
 618                                      <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
 619                                      <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
 620                                      <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
 621                                      <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
 622                                      <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
 623                                      <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
 624                                      <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
 625                                      <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
 626                                      <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
 627                                      <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
 628                                      <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
 629                                      <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
 630                                      <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
 631                                      <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
 632                                      <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
 633                                      <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
 634                                      <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
 635                                      <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
 636                 };
 637
 638                 crypto: crypto@8000000 {
 639                         compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
 640                         fsl,sec-era = <10>;
 641                         #address-cells = <1>;
 642                         #size-cells = <1>;
 643                         ranges = <0x0 0x00 0x8000000 0x100000>;
 644                         reg = <0x00 0x8000000 0x0 0x100000>;
 645                         interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
 646                         dma-coherent;
 647
 648                         sec_jr0: jr@10000 {
 649                                 compatible = "fsl,sec-v5.0-job-ring",
 650                                              "fsl,sec-v4.0-job-ring";
 651                                 reg     = <0x10000 0x10000>;
 652                                 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
 653                         };
 654
 655                         sec_jr1: jr@20000 {
 656                                 compatible = "fsl,sec-v5.0-job-ring",
 657                                              "fsl,sec-v4.0-job-ring";
 658                                 reg     = <0x20000 0x10000>;
 659                                 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
 660                         };
 661
 662                         sec_jr2: jr@30000 {
 663                                 compatible = "fsl,sec-v5.0-job-ring",
 664                                              "fsl,sec-v4.0-job-ring";
 665                                 reg     = <0x30000 0x10000>;
 666                                 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
 667                         };
 668
 669                         sec_jr3: jr@40000 {
 670                                 compatible = "fsl,sec-v5.0-job-ring",
 671                                              "fsl,sec-v4.0-job-ring";
 672                                 reg     = <0x40000 0x10000>;
 673                                 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 674                         };
 675                 };
 676
 677                 qdma: dma-controller@8380000 {
 678                         compatible = "fsl,ls1028a-qdma", "fsl,ls1021a-qdma";
 679                         reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
 680                               <0x0 0x8390000 0x0 0x10000>, /* Status regs */
 681                               <0x0 0x83a0000 0x0 0x40000>; /* Block regs */
 682                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
 683                                      <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
 684                                      <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
 685                                      <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
 686                                      <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>;
 687                         interrupt-names = "qdma-error", "qdma-queue0",
 688                                 "qdma-queue1", "qdma-queue2", "qdma-queue3";
 689                         dma-channels = <8>;
 690                         block-number = <1>;
 691                         block-offset = <0x10000>;
 692                         fsl,dma-queues = <2>;
 693                         status-sizes = <64>;
 694                         queue-sizes = <64 64>;
 695                 };
 696
 697                 cluster1_core0_watchdog: watchdog@c000000 {
 698                         compatible = "arm,sp805", "arm,primecell";
 699                         reg = <0x0 0xc000000 0x0 0x1000>;
 700                         clocks = <&clockgen 4 15>, <&clockgen 4 15>;
 701                         clock-names = "apb_pclk", "wdog_clk";
 702                 };
 703
 704                 cluster1_core1_watchdog: watchdog@c010000 {
 705                         compatible = "arm,sp805", "arm,primecell";
 706                         reg = <0x0 0xc010000 0x0 0x1000>;
 707                         clocks = <&clockgen 4 15>, <&clockgen 4 15>;
 708                         clock-names = "apb_pclk", "wdog_clk";
 709                 };
 710
 711                 sai1: audio-controller@f100000 {
 712                         #sound-dai-cells = <0>;
 713                         compatible = "fsl,vf610-sai";
 714                         reg = <0x0 0xf100000 0x0 0x10000>;
 715                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 716                         clocks = <&clockgen 4 1>, <&clockgen 4 1>,
 717                                  <&clockgen 4 1>, <&clockgen 4 1>;
 718                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 719                         dma-names = "tx", "rx";
 720                         dmas = <&edma0 1 4>,
 721                                <&edma0 1 3>;
 722                         fsl,sai-asynchronous;
 723                         status = "disabled";
 724                 };
 725
 726                 sai2: audio-controller@f110000 {
 727                         #sound-dai-cells = <0>;
 728                         compatible = "fsl,vf610-sai";
 729                         reg = <0x0 0xf110000 0x0 0x10000>;
 730                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 731                         clocks = <&clockgen 4 1>, <&clockgen 4 1>,
 732                                  <&clockgen 4 1>, <&clockgen 4 1>;
 733                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 734                         dma-names = "tx", "rx";
 735                         dmas = <&edma0 1 6>,
 736                                <&edma0 1 5>;
 737                         fsl,sai-asynchronous;
 738                         status = "disabled";
 739                 };
 740
 741                 sai3: audio-controller@f120000 {
 742                         #sound-dai-cells = <0>;
 743                         compatible = "fsl,vf610-sai";
 744                         reg = <0x0 0xf120000 0x0 0x10000>;
 745                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 746                         clocks = <&clockgen 4 1>, <&clockgen 4 1>,
 747                                  <&clockgen 4 1>, <&clockgen 4 1>;
 748                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 749                         dma-names = "tx", "rx";
 750                         dmas = <&edma0 1 8>,
 751                                <&edma0 1 7>;
 752                         fsl,sai-asynchronous;
 753                         status = "disabled";
 754                 };
 755
 756                 sai4: audio-controller@f130000 {
 757                         #sound-dai-cells = <0>;
 758                         compatible = "fsl,vf610-sai";
 759                         reg = <0x0 0xf130000 0x0 0x10000>;
 760                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 761                         clocks = <&clockgen 4 1>, <&clockgen 4 1>,
 762                                  <&clockgen 4 1>, <&clockgen 4 1>;
 763                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 764                         dma-names = "tx", "rx";
 765                         dmas = <&edma0 1 10>,
 766                                <&edma0 1 9>;
 767                         fsl,sai-asynchronous;
 768                         status = "disabled";
 769                 };
 770
 771                 sai5: audio-controller@f140000 {
 772                         #sound-dai-cells = <0>;
 773                         compatible = "fsl,vf610-sai";
 774                         reg = <0x0 0xf140000 0x0 0x10000>;
 775                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 776                         clocks = <&clockgen 4 1>, <&clockgen 4 1>,
 777                                  <&clockgen 4 1>, <&clockgen 4 1>;
 778                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 779                         dma-names = "tx", "rx";
 780                         dmas = <&edma0 1 12>,
 781                                <&edma0 1 11>;
 782                         fsl,sai-asynchronous;
 783                         status = "disabled";
 784                 };
 785
 786                 sai6: audio-controller@f150000 {
 787                         #sound-dai-cells = <0>;
 788                         compatible = "fsl,vf610-sai";
 789                         reg = <0x0 0xf150000 0x0 0x10000>;
 790                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 791                         clocks = <&clockgen 4 1>, <&clockgen 4 1>,
 792                                  <&clockgen 4 1>, <&clockgen 4 1>;
 793                         clock-names = "bus", "mclk1", "mclk2", "mclk3";
 794                         dma-names = "tx", "rx";
 795                         dmas = <&edma0 1 14>,
 796                                <&edma0 1 13>;
 797                         fsl,sai-asynchronous;
 798                         status = "disabled";
 799                 };
 800
 801                 tmu: tmu@1f80000 {
 802                         compatible = "fsl,qoriq-tmu";
 803                         reg = <0x0 0x1f80000 0x0 0x10000>;
 804                         interrupts = <0 23 0x4>;
 805                         fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>;
 806                         fsl,tmu-calibration = <0x00000000 0x00000024
 807                                                0x00000001 0x0000002b
 808                                                0x00000002 0x00000031
 809                                                0x00000003 0x00000038
 810                                                0x00000004 0x0000003f
 811                                                0x00000005 0x00000045
 812                                                0x00000006 0x0000004c
 813                                                0x00000007 0x00000053
 814                                                0x00000008 0x00000059
 815                                                0x00000009 0x00000060
 816                                                0x0000000a 0x00000066
 817                                                0x0000000b 0x0000006d
 818
 819                                                0x00010000 0x0000001c
 820                                                0x00010001 0x00000024
 821                                                0x00010002 0x0000002c
 822                                                0x00010003 0x00000035
 823                                                0x00010004 0x0000003d
 824                                                0x00010005 0x00000045
 825                                                0x00010006 0x0000004d
 826                                                0x00010007 0x00000055
 827                                                0x00010008 0x0000005e
 828                                                0x00010009 0x00000066
 829                                                0x0001000a 0x0000006e
 830
 831                                                0x00020000 0x00000018
 832                                                0x00020001 0x00000022
 833                                                0x00020002 0x0000002d
 834                                                0x00020003 0x00000038
 835                                                0x00020004 0x00000043
 836                                                0x00020005 0x0000004d
 837                                                0x00020006 0x00000058
 838                                                0x00020007 0x00000063
 839                                                0x00020008 0x0000006e
 840
 841                                                0x00030000 0x00000010
 842                                                0x00030001 0x0000001c
 843                                                0x00030002 0x00000029
 844                                                0x00030003 0x00000036
 845                                                0x00030004 0x00000042
 846                                                0x00030005 0x0000004f
 847                                                0x00030006 0x0000005b
 848                                                0x00030007 0x00000068>;
 849                         little-endian;
 850                         #thermal-sensor-cells = <1>;
 851                 };
 852
 853                 pcie@1f0000000 { /* Integrated Endpoint Root Complex */
 854                         compatible = "pci-host-ecam-generic";
 855                         reg = <0x01 0xf0000000 0x0 0x100000>;
 856                         #address-cells = <3>;
 857                         #size-cells = <2>;
 858                         msi-parent = <&its>;
 859                         device_type = "pci";
 860                         bus-range = <0x0 0x0>;
 861                         dma-coherent;
 862                         msi-map = <0 &its 0x17 0xe>;
 863                         iommu-map = <0 &smmu 0x17 0xe>;
 864                                   /* PF0-6 BAR0 - non-prefetchable memory */
 865                         ranges = <0x82000000 0x0 0x00000000  0x1 0xf8000000  0x0 0x160000
 866                                   /* PF0-6 BAR2 - prefetchable memory */
 867                                   0xc2000000 0x0 0x00000000  0x1 0xf8160000  0x0 0x070000
 868                                   /* PF0: VF0-1 BAR0 - non-prefetchable memory */
 869                                   0x82000000 0x0 0x00000000  0x1 0xf81d0000  0x0 0x020000
 870                                   /* PF0: VF0-1 BAR2 - prefetchable memory */
 871                                   0xc2000000 0x0 0x00000000  0x1 0xf81f0000  0x0 0x020000
 872                                   /* PF1: VF0-1 BAR0 - non-prefetchable memory */
 873                                   0x82000000 0x0 0x00000000  0x1 0xf8210000  0x0 0x020000
 874                                   /* PF1: VF0-1 BAR2 - prefetchable memory */
 875                                   0xc2000000 0x0 0x00000000  0x1 0xf8230000  0x0 0x020000
 876                                   /* BAR4 (PF5) - non-prefetchable memory */
 877                                   0x82000000 0x0 0x00000000  0x1 0xfc000000  0x0 0x400000>;
 878
 879                         enetc_port0: ethernet@0,0 {
 880                                 compatible = "fsl,enetc";
 881                                 reg = <0x000000 0 0 0 0>;
 882                                 status = "disabled";
 883                         };
 884
 885                         enetc_port1: ethernet@0,1 {
 886                                 compatible = "fsl,enetc";
 887                                 reg = <0x000100 0 0 0 0>;
 888                                 status = "disabled";
 889                         };
 890
 891                         enetc_port2: ethernet@0,2 {
 892                                 compatible = "fsl,enetc";
 893                                 reg = <0x000200 0 0 0 0>;
 894                                 phy-mode = "internal";
 895                                 status = "disabled";
 896
 897                                 fixed-link {
 898                                         speed = <1000>;
 899                                         full-duplex;
 900                                 };
 901                         };
 902
 903                         enetc_mdio_pf3: mdio@0,3 {
 904                                 compatible = "fsl,enetc-mdio";
 905                                 reg = <0x000300 0 0 0 0>;
 906                                 #address-cells = <1>;
 907                                 #size-cells = <0>;
 908                         };
 909
 910                         ethernet@0,4 {
 911                                 compatible = "fsl,enetc-ptp";
 912                                 reg = <0x000400 0 0 0 0>;
 913                                 clocks = <&clockgen 4 0>;
 914                                 little-endian;
 915                                 fsl,extts-fifo;
 916                         };
 917
 918                         mscc_felix: ethernet-switch@0,5 {
 919                                 reg = <0x000500 0 0 0 0>;
 920                                 /* IEP INT_B */
 921                                 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 922                                 status = "disabled";
 923
 924                                 ports {
 925                                         #address-cells = <1>;
 926                                         #size-cells = <0>;
 927
 928                                         /* External ports */
 929                                         mscc_felix_port0: port@0 {
 930                                                 reg = <0>;
 931                                                 status = "disabled";
 932                                         };
 933
 934                                         mscc_felix_port1: port@1 {
 935                                                 reg = <1>;
 936                                                 status = "disabled";
 937                                         };
 938
 939                                         mscc_felix_port2: port@2 {
 940                                                 reg = <2>;
 941                                                 status = "disabled";
 942                                         };
 943
 944                                         mscc_felix_port3: port@3 {
 945                                                 reg = <3>;
 946                                                 status = "disabled";
 947                                         };
 948
 949                                         /* Internal ports */
 950                                         mscc_felix_port4: port@4 {
 951                                                 reg = <4>;
 952                                                 phy-mode = "internal";
 953                                                 status = "disabled";
 954
 955                                                 fixed-link {
 956                                                         speed = <2500>;
 957                                                         full-duplex;
 958                                                 };
 959                                         };
 960
 961                                         mscc_felix_port5: port@5 {
 962                                                 reg = <5>;
 963                                                 phy-mode = "internal";
 964                                                 status = "disabled";
 965
 966                                                 fixed-link {
 967                                                         speed = <1000>;
 968                                                         full-duplex;
 969                                                 };
 970                                         };
 971                                 };
 972                         };
 973
 974                         enetc_port3: ethernet@0,6 {
 975                                 compatible = "fsl,enetc";
 976                                 reg = <0x000600 0 0 0 0>;
 977                                 phy-mode = "internal";
 978                                 status = "disabled";
 979
 980                                 fixed-link {
 981                                         speed = <1000>;
 982                                         full-duplex;
 983                                 };
 984                         };
 985                 };
 986         };
 987
 988         malidp0: display@f080000 {
 989                 compatible = "arm,mali-dp500";
 990                 reg = <0x0 0xf080000 0x0 0x10000>;
 991                 interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
 992                              <0 223 IRQ_TYPE_LEVEL_HIGH>;
 993                 interrupt-names = "DE", "SE";
 994                 clocks = <&dpclk>, <&clockgen 2 2>, <&clockgen 2 2>,
 995                          <&clockgen 2 2>;
 996                 clock-names = "pxlclk", "mclk", "aclk", "pclk";
 997                 arm,malidp-output-port-lines = /bits/ 8 <8 8 8>;
 998                 arm,malidp-arqos-value = <0xd000d000>;
 999
1000                 port {
1001                         dp0_out: endpoint {
1002
1003                         };
1004                 };
1005         };
1006 };