sys/gnu/dts/arm64/freescale/fsl-lx2160a.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 //
   3 // Device Tree Include file for Layerscape-LX2160A family SoC.
   4 //
   5 // Copyright 2018 NXP
   6
   7 #include <dt-bindings/gpio/gpio.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9
  10 /memreserve/ 0x80000000 0x00010000;
  11
  12 / {
  13         compatible = "fsl,lx2160a";
  14         interrupt-parent = <&gic>;
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         cpus {
  19                 #address-cells = <1>;
  20                 #size-cells = <0>;
  21
  22                 // 8 clusters having 2 Cortex-A72 cores each
  23                 cpu@0 {
  24                         device_type = "cpu";
  25                         compatible = "arm,cortex-a72";
  26                         enable-method = "psci";
  27                         reg = <0x0>;
  28                         clocks = <&clockgen 1 0>;
  29                         d-cache-size = <0x8000>;
  30                         d-cache-line-size = <64>;
  31                         d-cache-sets = <128>;
  32                         i-cache-size = <0xC000>;
  33                         i-cache-line-size = <64>;
  34                         i-cache-sets = <192>;
  35                         next-level-cache = <&cluster0_l2>;
  36                 };
  37
  38                 cpu@1 {
  39                         device_type = "cpu";
  40                         compatible = "arm,cortex-a72";
  41                         enable-method = "psci";
  42                         reg = <0x1>;
  43                         clocks = <&clockgen 1 0>;
  44                         d-cache-size = <0x8000>;
  45                         d-cache-line-size = <64>;
  46                         d-cache-sets = <128>;
  47                         i-cache-size = <0xC000>;
  48                         i-cache-line-size = <64>;
  49                         i-cache-sets = <192>;
  50                         next-level-cache = <&cluster0_l2>;
  51                 };
  52
  53                 cpu@100 {
  54                         device_type = "cpu";
  55                         compatible = "arm,cortex-a72";
  56                         enable-method = "psci";
  57                         reg = <0x100>;
  58                         clocks = <&clockgen 1 1>;
  59                         d-cache-size = <0x8000>;
  60                         d-cache-line-size = <64>;
  61                         d-cache-sets = <128>;
  62                         i-cache-size = <0xC000>;
  63                         i-cache-line-size = <64>;
  64                         i-cache-sets = <192>;
  65                         next-level-cache = <&cluster1_l2>;
  66                 };
  67
  68                 cpu@101 {
  69                         device_type = "cpu";
  70                         compatible = "arm,cortex-a72";
  71                         enable-method = "psci";
  72                         reg = <0x101>;
  73                         clocks = <&clockgen 1 1>;
  74                         d-cache-size = <0x8000>;
  75                         d-cache-line-size = <64>;
  76                         d-cache-sets = <128>;
  77                         i-cache-size = <0xC000>;
  78                         i-cache-line-size = <64>;
  79                         i-cache-sets = <192>;
  80                         next-level-cache = <&cluster1_l2>;
  81                 };
  82
  83                 cpu@200 {
  84                         device_type = "cpu";
  85                         compatible = "arm,cortex-a72";
  86                         enable-method = "psci";
  87                         reg = <0x200>;
  88                         clocks = <&clockgen 1 2>;
  89                         d-cache-size = <0x8000>;
  90                         d-cache-line-size = <64>;
  91                         d-cache-sets = <128>;
  92                         i-cache-size = <0xC000>;
  93                         i-cache-line-size = <64>;
  94                         i-cache-sets = <192>;
  95                         next-level-cache = <&cluster2_l2>;
  96                 };
  97
  98                 cpu@201 {
  99                         device_type = "cpu";
 100                         compatible = "arm,cortex-a72";
 101                         enable-method = "psci";
 102                         reg = <0x201>;
 103                         clocks = <&clockgen 1 2>;
 104                         d-cache-size = <0x8000>;
 105                         d-cache-line-size = <64>;
 106                         d-cache-sets = <128>;
 107                         i-cache-size = <0xC000>;
 108                         i-cache-line-size = <64>;
 109                         i-cache-sets = <192>;
 110                         next-level-cache = <&cluster2_l2>;
 111                 };
 112
 113                 cpu@300 {
 114                         device_type = "cpu";
 115                         compatible = "arm,cortex-a72";
 116                         enable-method = "psci";
 117                         reg = <0x300>;
 118                         clocks = <&clockgen 1 3>;
 119                         d-cache-size = <0x8000>;
 120                         d-cache-line-size = <64>;
 121                         d-cache-sets = <128>;
 122                         i-cache-size = <0xC000>;
 123                         i-cache-line-size = <64>;
 124                         i-cache-sets = <192>;
 125                         next-level-cache = <&cluster3_l2>;
 126                 };
 127
 128                 cpu@301 {
 129                         device_type = "cpu";
 130                         compatible = "arm,cortex-a72";
 131                         enable-method = "psci";
 132                         reg = <0x301>;
 133                         clocks = <&clockgen 1 3>;
 134                         d-cache-size = <0x8000>;
 135                         d-cache-line-size = <64>;
 136                         d-cache-sets = <128>;
 137                         i-cache-size = <0xC000>;
 138                         i-cache-line-size = <64>;
 139                         i-cache-sets = <192>;
 140                         next-level-cache = <&cluster3_l2>;
 141                 };
 142
 143                 cpu@400 {
 144                         device_type = "cpu";
 145                         compatible = "arm,cortex-a72";
 146                         enable-method = "psci";
 147                         reg = <0x400>;
 148                         clocks = <&clockgen 1 4>;
 149                         d-cache-size = <0x8000>;
 150                         d-cache-line-size = <64>;
 151                         d-cache-sets = <128>;
 152                         i-cache-size = <0xC000>;
 153                         i-cache-line-size = <64>;
 154                         i-cache-sets = <192>;
 155                         next-level-cache = <&cluster4_l2>;
 156                 };
 157
 158                 cpu@401 {
 159                         device_type = "cpu";
 160                         compatible = "arm,cortex-a72";
 161                         enable-method = "psci";
 162                         reg = <0x401>;
 163                         clocks = <&clockgen 1 4>;
 164                         d-cache-size = <0x8000>;
 165                         d-cache-line-size = <64>;
 166                         d-cache-sets = <128>;
 167                         i-cache-size = <0xC000>;
 168                         i-cache-line-size = <64>;
 169                         i-cache-sets = <192>;
 170                         next-level-cache = <&cluster4_l2>;
 171                 };
 172
 173                 cpu@500 {
 174                         device_type = "cpu";
 175                         compatible = "arm,cortex-a72";
 176                         enable-method = "psci";
 177                         reg = <0x500>;
 178                         clocks = <&clockgen 1 5>;
 179                         d-cache-size = <0x8000>;
 180                         d-cache-line-size = <64>;
 181                         d-cache-sets = <128>;
 182                         i-cache-size = <0xC000>;
 183                         i-cache-line-size = <64>;
 184                         i-cache-sets = <192>;
 185                         next-level-cache = <&cluster5_l2>;
 186                 };
 187
 188                 cpu@501 {
 189                         device_type = "cpu";
 190                         compatible = "arm,cortex-a72";
 191                         enable-method = "psci";
 192                         reg = <0x501>;
 193                         clocks = <&clockgen 1 5>;
 194                         d-cache-size = <0x8000>;
 195                         d-cache-line-size = <64>;
 196                         d-cache-sets = <128>;
 197                         i-cache-size = <0xC000>;
 198                         i-cache-line-size = <64>;
 199                         i-cache-sets = <192>;
 200                         next-level-cache = <&cluster5_l2>;
 201                 };
 202
 203                 cpu@600 {
 204                         device_type = "cpu";
 205                         compatible = "arm,cortex-a72";
 206                         enable-method = "psci";
 207                         reg = <0x600>;
 208                         clocks = <&clockgen 1 6>;
 209                         d-cache-size = <0x8000>;
 210                         d-cache-line-size = <64>;
 211                         d-cache-sets = <128>;
 212                         i-cache-size = <0xC000>;
 213                         i-cache-line-size = <64>;
 214                         i-cache-sets = <192>;
 215                         next-level-cache = <&cluster6_l2>;
 216                 };
 217
 218                 cpu@601 {
 219                         device_type = "cpu";
 220                         compatible = "arm,cortex-a72";
 221                         enable-method = "psci";
 222                         reg = <0x601>;
 223                         clocks = <&clockgen 1 6>;
 224                         d-cache-size = <0x8000>;
 225                         d-cache-line-size = <64>;
 226                         d-cache-sets = <128>;
 227                         i-cache-size = <0xC000>;
 228                         i-cache-line-size = <64>;
 229                         i-cache-sets = <192>;
 230                         next-level-cache = <&cluster6_l2>;
 231                 };
 232
 233                 cpu@700 {
 234                         device_type = "cpu";
 235                         compatible = "arm,cortex-a72";
 236                         enable-method = "psci";
 237                         reg = <0x700>;
 238                         clocks = <&clockgen 1 7>;
 239                         d-cache-size = <0x8000>;
 240                         d-cache-line-size = <64>;
 241                         d-cache-sets = <128>;
 242                         i-cache-size = <0xC000>;
 243                         i-cache-line-size = <64>;
 244                         i-cache-sets = <192>;
 245                         next-level-cache = <&cluster7_l2>;
 246                 };
 247
 248                 cpu@701 {
 249                         device_type = "cpu";
 250                         compatible = "arm,cortex-a72";
 251                         enable-method = "psci";
 252                         reg = <0x701>;
 253                         clocks = <&clockgen 1 7>;
 254                         d-cache-size = <0x8000>;
 255                         d-cache-line-size = <64>;
 256                         d-cache-sets = <128>;
 257                         i-cache-size = <0xC000>;
 258                         i-cache-line-size = <64>;
 259                         i-cache-sets = <192>;
 260                         next-level-cache = <&cluster7_l2>;
 261                 };
 262
 263                 cluster0_l2: l2-cache0 {
 264                         compatible = "cache";
 265                         cache-size = <0x100000>;
 266                         cache-line-size = <64>;
 267                         cache-sets = <1024>;
 268                         cache-level = <2>;
 269                 };
 270
 271                 cluster1_l2: l2-cache1 {
 272                         compatible = "cache";
 273                         cache-size = <0x100000>;
 274                         cache-line-size = <64>;
 275                         cache-sets = <1024>;
 276                         cache-level = <2>;
 277                 };
 278
 279                 cluster2_l2: l2-cache2 {
 280                         compatible = "cache";
 281                         cache-size = <0x100000>;
 282                         cache-line-size = <64>;
 283                         cache-sets = <1024>;
 284                         cache-level = <2>;
 285                 };
 286
 287                 cluster3_l2: l2-cache3 {
 288                         compatible = "cache";
 289                         cache-size = <0x100000>;
 290                         cache-line-size = <64>;
 291                         cache-sets = <1024>;
 292                         cache-level = <2>;
 293                 };
 294
 295                 cluster4_l2: l2-cache4 {
 296                         compatible = "cache";
 297                         cache-size = <0x100000>;
 298                         cache-line-size = <64>;
 299                         cache-sets = <1024>;
 300                         cache-level = <2>;
 301                 };
 302
 303                 cluster5_l2: l2-cache5 {
 304                         compatible = "cache";
 305                         cache-size = <0x100000>;
 306                         cache-line-size = <64>;
 307                         cache-sets = <1024>;
 308                         cache-level = <2>;
 309                 };
 310
 311                 cluster6_l2: l2-cache6 {
 312                         compatible = "cache";
 313                         cache-size = <0x100000>;
 314                         cache-line-size = <64>;
 315                         cache-sets = <1024>;
 316                         cache-level = <2>;
 317                 };
 318
 319                 cluster7_l2: l2-cache7 {
 320                         compatible = "cache";
 321                         cache-size = <0x100000>;
 322                         cache-line-size = <64>;
 323                         cache-sets = <1024>;
 324                         cache-level = <2>;
 325                 };
 326         };
 327
 328         gic: interrupt-controller@6000000 {
 329                 compatible = "arm,gic-v3";
 330                 reg = <0x0 0x06000000 0 0x10000>, // GIC Dist
 331                         <0x0 0x06200000 0 0x200000>, // GICR (RD_base +
 332                                                      // SGI_base)
 333                         <0x0 0x0c0c0000 0 0x2000>, // GICC
 334                         <0x0 0x0c0d0000 0 0x1000>, // GICH
 335                         <0x0 0x0c0e0000 0 0x20000>; // GICV
 336                 #interrupt-cells = <3>;
 337                 #address-cells = <2>;
 338                 #size-cells = <2>;
 339                 ranges;
 340                 interrupt-controller;
 341                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 342
 343                 its: gic-its@6020000 {
 344                         compatible = "arm,gic-v3-its";
 345                         msi-controller;
 346                         reg = <0x0 0x6020000 0 0x20000>;
 347                 };
 348         };
 349
 350         timer {
 351                 compatible = "arm,armv8-timer";
 352                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
 353                              <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
 354                              <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
 355                              <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
 356         };
 357
 358         pmu {
 359                 compatible = "arm,cortex-a72-pmu";
 360                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 361         };
 362
 363         psci {
 364                 compatible = "arm,psci-0.2";
 365                 method = "smc";
 366         };
 367
 368         memory@80000000 {
 369                 // DRAM space - 1, size : 2 GB DRAM
 370                 device_type = "memory";
 371                 reg = <0x00000000 0x80000000 0 0x80000000>;
 372         };
 373
 374         ddr1: memory-controller@1080000 {
 375                 compatible = "fsl,qoriq-memory-controller";
 376                 reg = <0x0 0x1080000 0x0 0x1000>;
 377                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 378                 little-endian;
 379         };
 380
 381         ddr2: memory-controller@1090000 {
 382                 compatible = "fsl,qoriq-memory-controller";
 383                 reg = <0x0 0x1090000 0x0 0x1000>;
 384                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 385                 little-endian;
 386         };
 387
 388         // One clock unit-sysclk node which bootloader require during DT fix-up
 389         sysclk: sysclk {
 390                 compatible = "fixed-clock";
 391                 #clock-cells = <0>;
 392                 clock-frequency = <100000000>; // fixed up by bootloader
 393                 clock-output-names = "sysclk";
 394         };
 395
 396         soc {
 397                 compatible = "simple-bus";
 398                 #address-cells = <2>;
 399                 #size-cells = <2>;
 400                 ranges;
 401
 402                 crypto: crypto@8000000 {
 403                         compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
 404                         fsl,sec-era = <10>;
 405                         #address-cells = <1>;
 406                         #size-cells = <1>;
 407                         ranges = <0x0 0x00 0x8000000 0x100000>;
 408                         reg = <0x00 0x8000000 0x0 0x100000>;
 409                         interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
 410                         dma-coherent;
 411                         status = "disabled";
 412
 413                         sec_jr0: jr@10000 {
 414                                 compatible = "fsl,sec-v5.0-job-ring",
 415                                              "fsl,sec-v4.0-job-ring";
 416                                 reg        = <0x10000 0x10000>;
 417                                 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
 418                         };
 419
 420                         sec_jr1: jr@20000 {
 421                                 compatible = "fsl,sec-v5.0-job-ring",
 422                                              "fsl,sec-v4.0-job-ring";
 423                                 reg        = <0x20000 0x10000>;
 424                                 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
 425                         };
 426
 427                         sec_jr2: jr@30000 {
 428                                 compatible = "fsl,sec-v5.0-job-ring",
 429                                              "fsl,sec-v4.0-job-ring";
 430                                 reg        = <0x30000 0x10000>;
 431                                 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
 432                         };
 433
 434                         sec_jr3: jr@40000 {
 435                                 compatible = "fsl,sec-v5.0-job-ring",
 436                                              "fsl,sec-v4.0-job-ring";
 437                                 reg        = <0x40000 0x10000>;
 438                                 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 439                         };
 440                 };
 441
 442                 clockgen: clock-controller@1300000 {
 443                         compatible = "fsl,lx2160a-clockgen";
 444                         reg = <0 0x1300000 0 0xa0000>;
 445                         #clock-cells = <2>;
 446                         clocks = <&sysclk>;
 447                 };
 448
 449                 dcfg: syscon@1e00000 {
 450                         compatible = "fsl,lx2160a-dcfg", "syscon";
 451                         reg = <0x0 0x1e00000 0x0 0x10000>;
 452                         little-endian;
 453                 };
 454
 455                 i2c0: i2c@2000000 {
 456                         compatible = "fsl,vf610-i2c";
 457                         #address-cells = <1>;
 458                         #size-cells = <0>;
 459                         reg = <0x0 0x2000000 0x0 0x10000>;
 460                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 461                         clock-names = "i2c";
 462                         clocks = <&clockgen 4 7>;
 463                         scl-gpio = <&gpio2 15 GPIO_ACTIVE_HIGH>;
 464                         status = "disabled";
 465                 };
 466
 467                 i2c1: i2c@2010000 {
 468                         compatible = "fsl,vf610-i2c";
 469                         #address-cells = <1>;
 470                         #size-cells = <0>;
 471                         reg = <0x0 0x2010000 0x0 0x10000>;
 472                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 473                         clock-names = "i2c";
 474                         clocks = <&clockgen 4 7>;
 475                         status = "disabled";
 476                 };
 477
 478                 i2c2: i2c@2020000 {
 479                         compatible = "fsl,vf610-i2c";
 480                         #address-cells = <1>;
 481                         #size-cells = <0>;
 482                         reg = <0x0 0x2020000 0x0 0x10000>;
 483                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 484                         clock-names = "i2c";
 485                         clocks = <&clockgen 4 7>;
 486                         status = "disabled";
 487                 };
 488
 489                 i2c3: i2c@2030000 {
 490                         compatible = "fsl,vf610-i2c";
 491                         #address-cells = <1>;
 492                         #size-cells = <0>;
 493                         reg = <0x0 0x2030000 0x0 0x10000>;
 494                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 495                         clock-names = "i2c";
 496                         clocks = <&clockgen 4 7>;
 497                         status = "disabled";
 498                 };
 499
 500                 i2c4: i2c@2040000 {
 501                         compatible = "fsl,vf610-i2c";
 502                         #address-cells = <1>;
 503                         #size-cells = <0>;
 504                         reg = <0x0 0x2040000 0x0 0x10000>;
 505                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 506                         clock-names = "i2c";
 507                         clocks = <&clockgen 4 7>;
 508                         scl-gpio = <&gpio2 16 GPIO_ACTIVE_HIGH>;
 509                         status = "disabled";
 510                 };
 511
 512                 i2c5: i2c@2050000 {
 513                         compatible = "fsl,vf610-i2c";
 514                         #address-cells = <1>;
 515                         #size-cells = <0>;
 516                         reg = <0x0 0x2050000 0x0 0x10000>;
 517                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 518                         clock-names = "i2c";
 519                         clocks = <&clockgen 4 7>;
 520                         status = "disabled";
 521                 };
 522
 523                 i2c6: i2c@2060000 {
 524                         compatible = "fsl,vf610-i2c";
 525                         #address-cells = <1>;
 526                         #size-cells = <0>;
 527                         reg = <0x0 0x2060000 0x0 0x10000>;
 528                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 529                         clock-names = "i2c";
 530                         clocks = <&clockgen 4 7>;
 531                         status = "disabled";
 532                 };
 533
 534                 i2c7: i2c@2070000 {
 535                         compatible = "fsl,vf610-i2c";
 536                         #address-cells = <1>;
 537                         #size-cells = <0>;
 538                         reg = <0x0 0x2070000 0x0 0x10000>;
 539                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 540                         clock-names = "i2c";
 541                         clocks = <&clockgen 4 7>;
 542                         status = "disabled";
 543                 };
 544
 545                 esdhc0: esdhc@2140000 {
 546                         compatible = "fsl,esdhc";
 547                         reg = <0x0 0x2140000 0x0 0x10000>;
 548                         interrupts = <0 28 0x4>; /* Level high type */
 549                         clocks = <&clockgen 4 1>;
 550                         voltage-ranges = <1800 1800 3300 3300>;
 551                         sdhci,auto-cmd12;
 552                         little-endian;
 553                         bus-width = <4>;
 554                         status = "disabled";
 555                 };
 556
 557                 esdhc1: esdhc@2150000 {
 558                         compatible = "fsl,esdhc";
 559                         reg = <0x0 0x2150000 0x0 0x10000>;
 560                         interrupts = <0 63 0x4>; /* Level high type */
 561                         clocks = <&clockgen 4 1>;
 562                         voltage-ranges = <1800 1800 3300 3300>;
 563                         sdhci,auto-cmd12;
 564                         broken-cd;
 565                         little-endian;
 566                         bus-width = <4>;
 567                         status = "disabled";
 568                 };
 569
 570                 uart0: serial@21c0000 {
 571                         compatible = "arm,sbsa-uart","arm,pl011";
 572                         reg = <0x0 0x21c0000 0x0 0x1000>;
 573                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 574                         current-speed = <115200>;
 575                         status = "disabled";
 576                 };
 577
 578                 uart1: serial@21d0000 {
 579                         compatible = "arm,sbsa-uart","arm,pl011";
 580                         reg = <0x0 0x21d0000 0x0 0x1000>;
 581                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 582                         current-speed = <115200>;
 583                         status = "disabled";
 584                 };
 585
 586                 uart2: serial@21e0000 {
 587                         compatible = "arm,sbsa-uart","arm,pl011";
 588                         reg = <0x0 0x21e0000 0x0 0x1000>;
 589                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 590                         current-speed = <115200>;
 591                         status = "disabled";
 592                 };
 593
 594                 uart3: serial@21f0000 {
 595                         compatible = "arm,sbsa-uart","arm,pl011";
 596                         reg = <0x0 0x21f0000 0x0 0x1000>;
 597                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 598                         current-speed = <115200>;
 599                         status = "disabled";
 600                 };
 601
 602                 gpio0: gpio@2300000 {
 603                         compatible = "fsl,qoriq-gpio";
 604                         reg = <0x0 0x2300000 0x0 0x10000>;
 605                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 606                         gpio-controller;
 607                         little-endian;
 608                         #gpio-cells = <2>;
 609                         interrupt-controller;
 610                         #interrupt-cells = <2>;
 611                 };
 612
 613                 gpio1: gpio@2310000 {
 614                         compatible = "fsl,qoriq-gpio";
 615                         reg = <0x0 0x2310000 0x0 0x10000>;
 616                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 617                         gpio-controller;
 618                         little-endian;
 619                         #gpio-cells = <2>;
 620                         interrupt-controller;
 621                         #interrupt-cells = <2>;
 622                 };
 623
 624                 gpio2: gpio@2320000 {
 625                         compatible = "fsl,qoriq-gpio";
 626                         reg = <0x0 0x2320000 0x0 0x10000>;
 627                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 628                         gpio-controller;
 629                         little-endian;
 630                         #gpio-cells = <2>;
 631                         interrupt-controller;
 632                         #interrupt-cells = <2>;
 633                 };
 634
 635                 gpio3: gpio@2330000 {
 636                         compatible = "fsl,qoriq-gpio";
 637                         reg = <0x0 0x2330000 0x0 0x10000>;
 638                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 639                         gpio-controller;
 640                         little-endian;
 641                         #gpio-cells = <2>;
 642                         interrupt-controller;
 643                         #interrupt-cells = <2>;
 644                 };
 645
 646                 watchdog@23a0000 {
 647                         compatible = "arm,sbsa-gwdt";
 648                         reg = <0x0 0x23a0000 0 0x1000>,
 649                               <0x0 0x2390000 0 0x1000>;
 650                         interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 651                         timeout-sec = <30>;
 652                 };
 653
 654                 usb0: usb@3100000 {
 655                         compatible = "snps,dwc3";
 656                         reg = <0x0 0x3100000 0x0 0x10000>;
 657                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 658                         dr_mode = "host";
 659                         snps,quirk-frame-length-adjustment = <0x20>;
 660                         snps,dis_rxdet_inp3_quirk;
 661                         status = "disabled";
 662                 };
 663
 664                 usb1: usb@3110000 {
 665                         compatible = "snps,dwc3";
 666                         reg = <0x0 0x3110000 0x0 0x10000>;
 667                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 668                         dr_mode = "host";
 669                         snps,quirk-frame-length-adjustment = <0x20>;
 670                         snps,dis_rxdet_inp3_quirk;
 671                         status = "disabled";
 672                 };
 673
 674                 smmu: iommu@5000000 {
 675                         compatible = "arm,mmu-500";
 676                         reg = <0 0x5000000 0 0x800000>;
 677                         #iommu-cells = <1>;
 678                         #global-interrupts = <14>;
 679                                      // global secure fault
 680                         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 681                                      // combined secure
 682                                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 683                                      // global non-secure fault
 684                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 685                                      // combined non-secure
 686                                      <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 687                                      // performance counter interrupts 0-9
 688                                      <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
 689                                      <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
 690                                      <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
 691                                      <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
 692                                      <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
 693                                      <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
 694                                      <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
 695                                      <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
 696                                      <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
 697                                      <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
 698                                      // per context interrupt, 64 interrupts
 699                                      <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 700                                      <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
 701                                      <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
 702                                      <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
 703                                      <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
 704                                      <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
 705                                      <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
 706                                      <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
 707                                      <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
 708                                      <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
 709                                      <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
 710                                      <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
 711                                      <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
 712                                      <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
 713                                      <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
 714                                      <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
 715                                      <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
 716                                      <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
 717                                      <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
 718                                      <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
 719                                      <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
 720                                      <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
 721                                      <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
 722                                      <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
 723                                      <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 724                                      <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
 725                                      <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
 726                                      <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
 727                                      <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
 728                                      <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
 729                                      <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
 730                                      <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
 731                                      <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
 732                                      <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
 733                                      <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
 734                                      <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
 735                                      <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
 736                                      <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
 737                                      <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
 738                                      <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
 739                                      <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
 740                                      <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
 741                                      <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
 742                                      <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
 743                                      <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
 744                                      <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
 745                                      <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
 746                                      <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
 747                                      <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
 748                                      <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
 749                                      <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
 750                                      <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
 751                                      <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
 752                                      <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
 753                                      <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
 754                                      <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
 755                                      <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
 756                                      <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
 757                                      <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
 758                                      <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
 759                                      <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
 760                                      <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
 761                                      <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
 762                                      <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
 763                         dma-coherent;
 764                 };
 765         };
 766 };