sys/gnu/dts/arm64/freescale/imx8mm-evk.dts

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright 2019 NXP
   4  */
   5
   6 /dts-v1/;
   7
   8 #include <dt-bindings/usb/pd.h>
   9 #include "imx8mm.dtsi"
  10
  11 / {
  12         model = "FSL i.MX8MM EVK board";
  13         compatible = "fsl,imx8mm-evk", "fsl,imx8mm";
  14
  15         chosen {
  16                 stdout-path = &uart2;
  17         };
  18
  19         memory@40000000 {
  20                 device_type = "memory";
  21                 reg = <0x0 0x40000000 0 0x80000000>;
  22         };
  23
  24         leds {
  25                 compatible = "gpio-leds";
  26                 pinctrl-names = "default";
  27                 pinctrl-0 = <&pinctrl_gpio_led>;
  28
  29                 status {
  30                         label = "status";
  31                         gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
  32                         default-state = "on";
  33                 };
  34         };
  35
  36         reg_usdhc2_vmmc: regulator-usdhc2 {
  37                 compatible = "regulator-fixed";
  38                 pinctrl-names = "default";
  39                 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
  40                 regulator-name = "VSD_3V3";
  41                 regulator-min-microvolt = <3300000>;
  42                 regulator-max-microvolt = <3300000>;
  43                 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
  44                 enable-active-high;
  45         };
  46
  47         wm8524: audio-codec {
  48                 #sound-dai-cells = <0>;
  49                 compatible = "wlf,wm8524";
  50                 pinctrl-names = "default";
  51                 pinctrl-0 = <&pinctrl_gpio_wlf>;
  52                 wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>;
  53         };
  54
  55         sound-wm8524 {
  56                 compatible = "simple-audio-card";
  57                 simple-audio-card,name = "wm8524-audio";
  58                 simple-audio-card,format = "i2s";
  59                 simple-audio-card,frame-master = <&cpudai>;
  60                 simple-audio-card,bitclock-master = <&cpudai>;
  61                 simple-audio-card,widgets =
  62                         "Line", "Left Line Out Jack",
  63                         "Line", "Right Line Out Jack";
  64                 simple-audio-card,routing =
  65                         "Left Line Out Jack", "LINEVOUTL",
  66                         "Right Line Out Jack", "LINEVOUTR";
  67
  68                 cpudai: simple-audio-card,cpu {
  69                         sound-dai = <&sai3>;
  70                         dai-tdm-slot-num = <2>;
  71                         dai-tdm-slot-width = <32>;
  72                 };
  73
  74                 simple-audio-card,codec {
  75                         sound-dai = <&wm8524>;
  76                         clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
  77                 };
  78         };
  79 };
  80
  81 &A53_0 {
  82         cpu-supply = <&buck2_reg>;
  83 };
  84
  85 &ddrc {
  86         operating-points-v2 = <&ddrc_opp_table>;
  87
  88         ddrc_opp_table: opp-table {
  89                 compatible = "operating-points-v2";
  90
  91                 opp-25M {
  92                         opp-hz = /bits/ 64 <25000000>;
  93                 };
  94
  95                 opp-100M {
  96                         opp-hz = /bits/ 64 <100000000>;
  97                 };
  98
  99                 opp-750M {
 100                         opp-hz = /bits/ 64 <750000000>;
 101                 };
 102         };
 103 };
 104
 105 &fec1 {
 106         pinctrl-names = "default";
 107         pinctrl-0 = <&pinctrl_fec1>;
 108         phy-mode = "rgmii-id";
 109         phy-handle = <&ethphy0>;
 110         phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
 111         phy-reset-duration = <10>;
 112         fsl,magic-packet;
 113         status = "okay";
 114
 115         mdio {
 116                 #address-cells = <1>;
 117                 #size-cells = <0>;
 118
 119                 ethphy0: ethernet-phy@0 {
 120                         compatible = "ethernet-phy-ieee802.3-c22";
 121                         reg = <0>;
 122                 };
 123         };
 124 };
 125
 126 &i2c1 {
 127         clock-frequency = <400000>;
 128         pinctrl-names = "default";
 129         pinctrl-0 = <&pinctrl_i2c1>;
 130         status = "okay";
 131
 132         pmic@4b {
 133                 compatible = "rohm,bd71847";
 134                 reg = <0x4b>;
 135                 pinctrl-0 = <&pinctrl_pmic>;
 136                 interrupt-parent = <&gpio1>;
 137                 interrupts = <3 GPIO_ACTIVE_LOW>;
 138                 rohm,reset-snvs-powered;
 139
 140                 regulators {
 141                         buck1_reg: BUCK1 {
 142                                 regulator-name = "BUCK1";
 143                                 regulator-min-microvolt = <700000>;
 144                                 regulator-max-microvolt = <1300000>;
 145                                 regulator-boot-on;
 146                                 regulator-always-on;
 147                                 regulator-ramp-delay = <1250>;
 148                         };
 149
 150                         buck2_reg: BUCK2 {
 151                                 regulator-name = "BUCK2";
 152                                 regulator-min-microvolt = <700000>;
 153                                 regulator-max-microvolt = <1300000>;
 154                                 regulator-boot-on;
 155                                 regulator-always-on;
 156                                 regulator-ramp-delay = <1250>;
 157                                 rohm,dvs-run-voltage = <1000000>;
 158                                 rohm,dvs-idle-voltage = <900000>;
 159                         };
 160
 161                         buck3_reg: BUCK3 {
 162                                 // BUCK5 in datasheet
 163                                 regulator-name = "BUCK3";
 164                                 regulator-min-microvolt = <700000>;
 165                                 regulator-max-microvolt = <1350000>;
 166                                 regulator-boot-on;
 167                                 regulator-always-on;
 168                         };
 169
 170                         buck4_reg: BUCK4 {
 171                                 // BUCK6 in datasheet
 172                                 regulator-name = "BUCK4";
 173                                 regulator-min-microvolt = <3000000>;
 174                                 regulator-max-microvolt = <3300000>;
 175                                 regulator-boot-on;
 176                                 regulator-always-on;
 177                         };
 178
 179                         buck5_reg: BUCK5 {
 180                                 // BUCK7 in datasheet
 181                                 regulator-name = "BUCK5";
 182                                 regulator-min-microvolt = <1605000>;
 183                                 regulator-max-microvolt = <1995000>;
 184                                 regulator-boot-on;
 185                                 regulator-always-on;
 186                         };
 187
 188                         buck6_reg: BUCK6 {
 189                                 // BUCK8 in datasheet
 190                                 regulator-name = "BUCK6";
 191                                 regulator-min-microvolt = <800000>;
 192                                 regulator-max-microvolt = <1400000>;
 193                                 regulator-boot-on;
 194                                 regulator-always-on;
 195                         };
 196
 197                         ldo1_reg: LDO1 {
 198                                 regulator-name = "LDO1";
 199                                 regulator-min-microvolt = <3000000>;
 200                                 regulator-max-microvolt = <3300000>;
 201                                 regulator-boot-on;
 202                                 regulator-always-on;
 203                         };
 204
 205                         ldo2_reg: LDO2 {
 206                                 regulator-name = "LDO2";
 207                                 regulator-min-microvolt = <900000>;
 208                                 regulator-max-microvolt = <900000>;
 209                                 regulator-boot-on;
 210                                 regulator-always-on;
 211                         };
 212
 213                         ldo3_reg: LDO3 {
 214                                 regulator-name = "LDO3";
 215                                 regulator-min-microvolt = <1800000>;
 216                                 regulator-max-microvolt = <3300000>;
 217                                 regulator-boot-on;
 218                                 regulator-always-on;
 219                         };
 220
 221                         ldo4_reg: LDO4 {
 222                                 regulator-name = "LDO4";
 223                                 regulator-min-microvolt = <900000>;
 224                                 regulator-max-microvolt = <1800000>;
 225                                 regulator-boot-on;
 226                                 regulator-always-on;
 227                         };
 228
 229                         ldo6_reg: LDO6 {
 230                                 regulator-name = "LDO6";
 231                                 regulator-min-microvolt = <900000>;
 232                                 regulator-max-microvolt = <1800000>;
 233                                 regulator-boot-on;
 234                                 regulator-always-on;
 235                         };
 236                 };
 237         };
 238 };
 239
 240 &i2c2 {
 241         clock-frequency = <400000>;
 242         pinctrl-names = "default";
 243         pinctrl-0 = <&pinctrl_i2c2>;
 244         status = "okay";
 245
 246         ptn5110: tcpc@50 {
 247                 compatible = "nxp,ptn5110";
 248                 pinctrl-names = "default";
 249                 pinctrl-0 = <&pinctrl_typec1>;
 250                 reg = <0x50>;
 251                 interrupt-parent = <&gpio2>;
 252                 interrupts = <11 8>;
 253                 status = "okay";
 254
 255                 port {
 256                         typec1_dr_sw: endpoint {
 257                                 remote-endpoint = <&usb1_drd_sw>;
 258                         };
 259                 };
 260
 261                 typec1_con: connector {
 262                         compatible = "usb-c-connector";
 263                         label = "USB-C";
 264                         power-role = "dual";
 265                         data-role = "dual";
 266                         try-power-role = "sink";
 267                         source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
 268                         sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
 269                                      PDO_VAR(5000, 20000, 3000)>;
 270                         op-sink-microwatt = <15000000>;
 271                         self-powered;
 272                 };
 273         };
 274 };
 275
 276 &i2c3 {
 277         clock-frequency = <400000>;
 278         pinctrl-names = "default";
 279         pinctrl-0 = <&pinctrl_i2c3>;
 280         status = "okay";
 281
 282         pca6416: gpio@20 {
 283                 compatible = "ti,tca6416";
 284                 reg = <0x20>;
 285                 gpio-controller;
 286                 #gpio-cells = <2>;
 287         };
 288 };
 289
 290 &sai3 {
 291         pinctrl-names = "default";
 292         pinctrl-0 = <&pinctrl_sai3>;
 293         assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
 294         assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
 295         assigned-clock-rates = <24576000>;
 296         status = "okay";
 297 };
 298
 299 &snvs_pwrkey {
 300         status = "okay";
 301 };
 302
 303 &uart2 { /* console */
 304         pinctrl-names = "default";
 305         pinctrl-0 = <&pinctrl_uart2>;
 306         status = "okay";
 307 };
 308
 309 &usbotg1 {
 310         dr_mode = "otg";
 311         hnp-disable;
 312         srp-disable;
 313         adp-disable;
 314         usb-role-switch;
 315         status = "okay";
 316
 317         port {
 318                 usb1_drd_sw: endpoint {
 319                         remote-endpoint = <&typec1_dr_sw>;
 320                 };
 321         };
 322 };
 323
 324 &usdhc2 {
 325         assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
 326         assigned-clock-rates = <200000000>;
 327         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 328         pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
 329         pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
 330         pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
 331         cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
 332         bus-width = <4>;
 333         vmmc-supply = <&reg_usdhc2_vmmc>;
 334         status = "okay";
 335 };
 336
 337 &usdhc3 {
 338         assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
 339         assigned-clock-rates = <400000000>;
 340         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 341         pinctrl-0 = <&pinctrl_usdhc3>;
 342         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 343         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 344         bus-width = <8>;
 345         non-removable;
 346         status = "okay";
 347 };
 348
 349 &wdog1 {
 350         pinctrl-names = "default";
 351         pinctrl-0 = <&pinctrl_wdog>;
 352         fsl,ext-reset-output;
 353         status = "okay";
 354 };
 355
 356 &iomuxc {
 357         pinctrl-names = "default";
 358
 359         pinctrl_fec1: fec1grp {
 360                 fsl,pins = <
 361                         MX8MM_IOMUXC_ENET_MDC_ENET1_MDC                 0x3
 362                         MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO               0x3
 363                         MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3           0x1f
 364                         MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2           0x1f
 365                         MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1           0x1f
 366                         MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0           0x1f
 367                         MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3           0x91
 368                         MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2           0x91
 369                         MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1           0x91
 370                         MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0           0x91
 371                         MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC           0x1f
 372                         MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC           0x91
 373                         MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL     0x91
 374                         MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL     0x1f
 375                         MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22                0x19
 376                 >;
 377         };
 378
 379         pinctrl_gpio_led: gpioledgrp {
 380                 fsl,pins = <
 381                         MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16    0x19
 382                 >;
 383         };
 384
 385         pinctrl_gpio_wlf: gpiowlfgrp {
 386                 fsl,pins = <
 387                         MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21        0xd6
 388                 >;
 389         };
 390
 391         pinctrl_i2c1: i2c1grp {
 392                 fsl,pins = <
 393                         MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL                  0x400001c3
 394                         MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA                  0x400001c3
 395                 >;
 396         };
 397
 398         pinctrl_i2c2: i2c2grp {
 399                 fsl,pins = <
 400                         MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL                  0x400001c3
 401                         MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA                  0x400001c3
 402                 >;
 403         };
 404
 405         pinctrl_i2c3: i2c3grp {
 406                 fsl,pins = <
 407                         MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL                  0x400001c3
 408                         MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA                  0x400001c3
 409                 >;
 410         };
 411
 412         pinctrl_pmic: pmicirq {
 413                 fsl,pins = <
 414                         MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3               0x41
 415                 >;
 416         };
 417
 418         pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
 419                 fsl,pins = <
 420                         MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19     0x41
 421                 >;
 422         };
 423
 424         pinctrl_sai3: sai3grp {
 425                 fsl,pins = <
 426                         MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC     0xd6
 427                         MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK      0xd6
 428                         MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK        0xd6
 429                         MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0     0xd6
 430                 >;
 431         };
 432
 433         pinctrl_typec1: typec1grp {
 434                 fsl,pins = <
 435                         MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11      0x159
 436                 >;
 437         };
 438
 439         pinctrl_uart2: uart2grp {
 440                 fsl,pins = <
 441                         MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX     0x140
 442                         MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX     0x140
 443                 >;
 444         };
 445
 446         pinctrl_usdhc2_gpio: usdhc2grpgpio {
 447                 fsl,pins = <
 448                         MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15      0x1c4
 449                 >;
 450         };
 451
 452         pinctrl_usdhc2: usdhc2grp {
 453                 fsl,pins = <
 454                         MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK         0x190
 455                         MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d0
 456                         MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d0
 457                         MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d0
 458                         MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d0
 459                         MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d0
 460                         MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0
 461                 >;
 462         };
 463
 464         pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
 465                 fsl,pins = <
 466                         MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK         0x194
 467                         MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d4
 468                         MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d4
 469                         MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d4
 470                         MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d4
 471                         MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d4
 472                         MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0
 473                 >;
 474         };
 475
 476         pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
 477                 fsl,pins = <
 478                         MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK         0x196
 479                         MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d6
 480                         MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d6
 481                         MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d6
 482                         MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d6
 483                         MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d6
 484                         MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0
 485                 >;
 486         };
 487
 488         pinctrl_usdhc3: usdhc3grp {
 489                 fsl,pins = <
 490                         MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK               0x190
 491                         MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d0
 492                         MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d0
 493                         MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d0
 494                         MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d0
 495                         MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d0
 496                         MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d0
 497                         MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d0
 498                         MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d0
 499                         MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d0
 500                         MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x190
 501                 >;
 502         };
 503
 504         pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
 505                 fsl,pins = <
 506                         MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK               0x194
 507                         MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d4
 508                         MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d4
 509                         MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d4
 510                         MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d4
 511                         MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d4
 512                         MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d4
 513                         MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d4
 514                         MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d4
 515                         MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d4
 516                         MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x194
 517                 >;
 518         };
 519
 520         pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
 521                 fsl,pins = <
 522                         MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK               0x196
 523                         MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d6
 524                         MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d6
 525                         MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d6
 526                         MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d6
 527                         MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d6
 528                         MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d6
 529                         MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d6
 530                         MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d6
 531                         MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d6
 532                         MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x196
 533                 >;
 534         };
 535
 536         pinctrl_wdog: wdoggrp {
 537                 fsl,pins = <
 538                         MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B    0xc6
 539                 >;
 540         };
 541 };