sys/gnu/dts/arm64/freescale/imx8mn-ddr4-evk.dts

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright 2019 NXP
   4  */
   5
   6 /dts-v1/;
   7
   8 #include "imx8mn.dtsi"
   9
  10 / {
  11         model = "NXP i.MX8MNano DDR4 EVK board";
  12         compatible = "fsl,imx8mn-ddr4-evk", "fsl,imx8mn";
  13
  14         chosen {
  15                 stdout-path = &uart2;
  16         };
  17
  18         reg_usdhc2_vmmc: regulator-usdhc2 {
  19                 compatible = "regulator-fixed";
  20                 pinctrl-names = "default";
  21                 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
  22                 regulator-name = "VSD_3V3";
  23                 regulator-min-microvolt = <3300000>;
  24                 regulator-max-microvolt = <3300000>;
  25                 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
  26                 enable-active-high;
  27         };
  28 };
  29
  30 &A53_0 {
  31         cpu-supply = <&buck2_reg>;
  32 };
  33
  34 &iomuxc {
  35         pinctrl-names = "default";
  36
  37         pinctrl_fec1: fec1grp {
  38                 fsl,pins = <
  39                         MX8MN_IOMUXC_ENET_MDC_ENET1_MDC         0x3
  40                         MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO       0x3
  41                         MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3   0x1f
  42                         MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2   0x1f
  43                         MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1   0x1f
  44                         MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0   0x1f
  45                         MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3   0x91
  46                         MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2   0x91
  47                         MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1   0x91
  48                         MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0   0x91
  49                         MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC   0x1f
  50                         MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC   0x91
  51                         MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL     0x91
  52                         MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL     0x1f
  53                         MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22        0x19
  54                 >;
  55         };
  56
  57         pinctrl_i2c1: i2c1grp {
  58                 fsl,pins = <
  59                         MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL          0x400001c3
  60                         MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA          0x400001c3
  61                 >;
  62         };
  63
  64         pinctrl_pmic: pmicirq {
  65                 fsl,pins = <
  66                         MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3       0x41
  67                 >;
  68         };
  69
  70         pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
  71                 fsl,pins = <
  72                         MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19     0x41
  73                 >;
  74         };
  75
  76         pinctrl_uart2: uart2grp {
  77                 fsl,pins = <
  78                         MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX     0x140
  79                         MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX     0x140
  80                 >;
  81         };
  82
  83         pinctrl_usdhc2_gpio: usdhc2grpgpio {
  84                 fsl,pins = <
  85                         MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15      0x1c4
  86                 >;
  87         };
  88
  89         pinctrl_usdhc2: usdhc2grp {
  90                 fsl,pins = <
  91                         MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK         0x190
  92                         MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d0
  93                         MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d0
  94                         MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d0
  95                         MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d0
  96                         MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d0
  97                         MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0
  98                 >;
  99         };
 100
 101         pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
 102                 fsl,pins = <
 103                         MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK         0x194
 104                         MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d4
 105                         MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d4
 106                         MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d4
 107                         MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d4
 108                         MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d4
 109                         MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0
 110                 >;
 111         };
 112
 113         pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
 114                 fsl,pins = <
 115                         MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK         0x196
 116                         MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD         0x1d6
 117                         MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0     0x1d6
 118                         MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1     0x1d6
 119                         MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2     0x1d6
 120                         MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3     0x1d6
 121                         MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0
 122                 >;
 123         };
 124
 125         pinctrl_usdhc3: usdhc3grp {
 126                 fsl,pins = <
 127                         MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK               0x40000190
 128                         MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d0
 129                         MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d0
 130                         MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d0
 131                         MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d0
 132                         MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d0
 133                         MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d0
 134                         MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d0
 135                         MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d0
 136                         MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d0
 137                         MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x190
 138                 >;
 139         };
 140
 141         pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
 142                 fsl,pins = <
 143                         MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK               0x40000194
 144                         MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d4
 145                         MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d4
 146                         MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d4
 147                         MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d4
 148                         MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d4
 149                         MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d4
 150                         MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d4
 151                         MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d4
 152                         MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d4
 153                         MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x194
 154                 >;
 155         };
 156
 157         pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
 158                 fsl,pins = <
 159                         MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK               0x40000196
 160                         MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d6
 161                         MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d6
 162                         MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d6
 163                         MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d6
 164                         MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d6
 165                         MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d6
 166                         MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d6
 167                         MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d6
 168                         MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d6
 169                         MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x196
 170                 >;
 171         };
 172
 173         pinctrl_wdog: wdoggrp {
 174                 fsl,pins = <
 175                         MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B            0xc6
 176                 >;
 177         };
 178 };
 179
 180 &fec1 {
 181         pinctrl-names = "default";
 182         pinctrl-0 = <&pinctrl_fec1>;
 183         phy-mode = "rgmii-id";
 184         phy-handle = <&ethphy0>;
 185         fsl,magic-packet;
 186         status = "okay";
 187
 188         mdio {
 189                 #address-cells = <1>;
 190                 #size-cells = <0>;
 191
 192                 ethphy0: ethernet-phy@0 {
 193                         compatible = "ethernet-phy-ieee802.3-c22";
 194                         reg = <0>;
 195                         at803x,led-act-blind-workaround;
 196                         at803x,eee-disabled;
 197                         at803x,vddio-1p8v;
 198                 };
 199         };
 200 };
 201
 202 &i2c1 {
 203         clock-frequency = <400000>;
 204         pinctrl-names = "default";
 205         pinctrl-0 = <&pinctrl_i2c1>;
 206         status = "okay";
 207
 208         pmic@4b {
 209                 compatible = "rohm,bd71847";
 210                 reg = <0x4b>;
 211                 pinctrl-0 = <&pinctrl_pmic>;
 212                 interrupt-parent = <&gpio1>;
 213                 interrupts = <3 GPIO_ACTIVE_LOW>;
 214                 rohm,reset-snvs-powered;
 215
 216                 regulators {
 217                         buck1_reg: BUCK1 {
 218                                 regulator-name = "BUCK1";
 219                                 regulator-min-microvolt = <700000>;
 220                                 regulator-max-microvolt = <1300000>;
 221                                 regulator-boot-on;
 222                                 regulator-always-on;
 223                                 regulator-ramp-delay = <1250>;
 224                         };
 225
 226                         buck2_reg: BUCK2 {
 227                                 regulator-name = "BUCK2";
 228                                 regulator-min-microvolt = <700000>;
 229                                 regulator-max-microvolt = <1300000>;
 230                                 regulator-boot-on;
 231                                 regulator-always-on;
 232                                 regulator-ramp-delay = <1250>;
 233                         };
 234
 235                         buck3_reg: BUCK3 {
 236                                 // BUCK5 in datasheet
 237                                 regulator-name = "BUCK3";
 238                                 regulator-min-microvolt = <700000>;
 239                                 regulator-max-microvolt = <1350000>;
 240                         };
 241
 242                         buck4_reg: BUCK4 {
 243                                 // BUCK6 in datasheet
 244                                 regulator-name = "BUCK4";
 245                                 regulator-min-microvolt = <3000000>;
 246                                 regulator-max-microvolt = <3300000>;
 247                                 regulator-boot-on;
 248                                 regulator-always-on;
 249                         };
 250
 251                         buck5_reg: BUCK5 {
 252                                 // BUCK7 in datasheet
 253                                 regulator-name = "BUCK5";
 254                                 regulator-min-microvolt = <1605000>;
 255                                 regulator-max-microvolt = <1995000>;
 256                                 regulator-boot-on;
 257                                 regulator-always-on;
 258                         };
 259
 260                         buck6_reg: BUCK6 {
 261                                 // BUCK8 in datasheet
 262                                 regulator-name = "BUCK6";
 263                                 regulator-min-microvolt = <800000>;
 264                                 regulator-max-microvolt = <1400000>;
 265                                 regulator-boot-on;
 266                                 regulator-always-on;
 267                         };
 268
 269                         ldo1_reg: LDO1 {
 270                                 regulator-name = "LDO1";
 271                                 regulator-min-microvolt = <3000000>;
 272                                 regulator-max-microvolt = <3300000>;
 273                                 regulator-boot-on;
 274                                 regulator-always-on;
 275                         };
 276
 277                         ldo2_reg: LDO2 {
 278                                 regulator-name = "LDO2";
 279                                 regulator-min-microvolt = <900000>;
 280                                 regulator-max-microvolt = <900000>;
 281                                 regulator-boot-on;
 282                                 regulator-always-on;
 283                         };
 284
 285                         ldo3_reg: LDO3 {
 286                                 regulator-name = "LDO3";
 287                                 regulator-min-microvolt = <1800000>;
 288                                 regulator-max-microvolt = <3300000>;
 289                                 regulator-boot-on;
 290                                 regulator-always-on;
 291                         };
 292
 293                         ldo4_reg: LDO4 {
 294                                 regulator-name = "LDO4";
 295                                 regulator-min-microvolt = <900000>;
 296                                 regulator-max-microvolt = <1800000>;
 297                                 regulator-boot-on;
 298                                 regulator-always-on;
 299                         };
 300
 301                         ldo6_reg: LDO6 {
 302                                 regulator-name = "LDO6";
 303                                 regulator-min-microvolt = <900000>;
 304                                 regulator-max-microvolt = <1800000>;
 305                                 regulator-boot-on;
 306                                 regulator-always-on;
 307                         };
 308                 };
 309         };
 310 };
 311
 312 &snvs_pwrkey {
 313         status = "okay";
 314 };
 315
 316 &uart2 { /* console */
 317         pinctrl-names = "default";
 318         pinctrl-0 = <&pinctrl_uart2>;
 319         status = "okay";
 320 };
 321
 322 &usdhc2 {
 323         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 324         pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
 325         pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
 326         pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
 327         cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
 328         bus-width = <4>;
 329         vmmc-supply = <&reg_usdhc2_vmmc>;
 330         status = "okay";
 331 };
 332
 333 &usdhc3 {
 334         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 335         pinctrl-0 = <&pinctrl_usdhc3>;
 336         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 337         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 338         bus-width = <8>;
 339         non-removable;
 340         status = "okay";
 341 };
 342
 343 &wdog1 {
 344         pinctrl-names = "default";
 345         pinctrl-0 = <&pinctrl_wdog>;
 346         fsl,ext-reset-output;
 347         status = "okay";
 348 };