1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
7 #include <dt-bindings/clock/imx8mq-clock.h>
8 #include <dt-bindings/power/imx8mq-power.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include "imx8mq-pinfunc.h"
14 interrupt-parent = <&gpc>;
34 compatible = "fixed-clock";
36 clock-frequency = <32768>;
37 clock-output-names = "ckil";
40 osc_25m: clock-osc-25m {
41 compatible = "fixed-clock";
43 clock-frequency = <25000000>;
44 clock-output-names = "osc_25m";
47 osc_27m: clock-osc-27m {
48 compatible = "fixed-clock";
50 clock-frequency = <27000000>;
51 clock-output-names = "osc_27m";
54 clk_ext1: clock-ext1 {
55 compatible = "fixed-clock";
57 clock-frequency = <133000000>;
58 clock-output-names = "clk_ext1";
61 clk_ext2: clock-ext2 {
62 compatible = "fixed-clock";
64 clock-frequency = <133000000>;
65 clock-output-names = "clk_ext2";
68 clk_ext3: clock-ext3 {
69 compatible = "fixed-clock";
71 clock-frequency = <133000000>;
72 clock-output-names = "clk_ext3";
75 clk_ext4: clock-ext4 {
76 compatible = "fixed-clock";
78 clock-frequency= <133000000>;
79 clock-output-names = "clk_ext4";
88 compatible = "arm,cortex-a53";
90 enable-method = "psci";
91 next-level-cache = <&A53_L2>;
96 compatible = "arm,cortex-a53";
98 enable-method = "psci";
99 next-level-cache = <&A53_L2>;
104 compatible = "arm,cortex-a53";
106 enable-method = "psci";
107 next-level-cache = <&A53_L2>;
112 compatible = "arm,cortex-a53";
114 enable-method = "psci";
115 next-level-cache = <&A53_L2>;
119 compatible = "cache";
124 compatible = "arm,cortex-a53-pmu";
125 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
126 interrupt-parent = <&gic>;
127 interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>;
131 compatible = "arm,psci-1.0";
136 compatible = "arm,armv8-timer";
137 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
138 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
139 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
140 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
141 interrupt-parent = <&gic>;
142 arm,no-tick-in-suspend;
146 compatible = "simple-bus";
147 #address-cells = <1>;
149 ranges = <0x0 0x0 0x0 0x3e000000>;
150 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
152 bus@30000000 { /* AIPS1 */
153 compatible = "fsl,imx8mq-aips-bus", "simple-bus";
154 #address-cells = <1>;
156 ranges = <0x30000000 0x30000000 0x400000>;
158 gpio1: gpio@30200000 {
159 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
160 reg = <0x30200000 0x10000>;
161 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
162 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
165 interrupt-controller;
166 #interrupt-cells = <2>;
169 gpio2: gpio@30210000 {
170 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
171 reg = <0x30210000 0x10000>;
172 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
173 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
176 interrupt-controller;
177 #interrupt-cells = <2>;
180 gpio3: gpio@30220000 {
181 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
182 reg = <0x30220000 0x10000>;
183 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
184 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
187 interrupt-controller;
188 #interrupt-cells = <2>;
191 gpio4: gpio@30230000 {
192 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
193 reg = <0x30230000 0x10000>;
194 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
195 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
198 interrupt-controller;
199 #interrupt-cells = <2>;
202 gpio5: gpio@30240000 {
203 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
204 reg = <0x30240000 0x10000>;
205 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
206 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
209 interrupt-controller;
210 #interrupt-cells = <2>;
213 wdog1: watchdog@30280000 {
214 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
215 reg = <0x30280000 0x10000>;
216 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
217 clocks = <&clk IMX8MQ_CLK_WDOG1_ROOT>;
221 wdog2: watchdog@30290000 {
222 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
223 reg = <0x30290000 0x10000>;
224 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
225 clocks = <&clk IMX8MQ_CLK_WDOG2_ROOT>;
229 wdog3: watchdog@302a0000 {
230 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
231 reg = <0x302a0000 0x10000>;
232 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
233 clocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>;
237 iomuxc: iomuxc@30330000 {
238 compatible = "fsl,imx8mq-iomuxc";
239 reg = <0x30330000 0x10000>;
242 iomuxc_gpr: syscon@30340000 {
243 compatible = "fsl,imx8mq-iomuxc-gpr", "syscon";
244 reg = <0x30340000 0x10000>;
247 anatop: syscon@30360000 {
248 compatible = "fsl,imx8mq-anatop", "syscon";
249 reg = <0x30360000 0x10000>;
250 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
253 snvs: snvs@30370000 {
254 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
255 reg = <0x30370000 0x10000>;
257 snvs_rtc: snvs-rtc-lp{
258 compatible = "fsl,sec-v4.0-mon-rtc-lp";
261 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
262 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
267 clk: clock-controller@30380000 {
268 compatible = "fsl,imx8mq-ccm";
269 reg = <0x30380000 0x10000>;
270 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
271 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
273 clocks = <&ckil>, <&osc_25m>, <&osc_27m>,
274 <&clk_ext1>, <&clk_ext2>,
275 <&clk_ext3>, <&clk_ext4>;
276 clock-names = "ckil", "osc_25m", "osc_27m",
277 "clk_ext1", "clk_ext2",
278 "clk_ext3", "clk_ext4";
282 compatible = "fsl,imx8mq-gpc";
283 reg = <0x303a0000 0x10000>;
284 interrupt-parent = <&gic>;
285 interrupt-controller;
286 #interrupt-cells = <3>;
289 #address-cells = <1>;
292 pgc_mipi: power-domain@0 {
293 #power-domain-cells = <0>;
294 reg = <IMX8M_POWER_DOMAIN_MIPI>;
297 pgc_pcie1: power-domain@1 {
298 #power-domain-cells = <0>;
299 reg = <IMX8M_POWER_DOMAIN_PCIE1>;
302 pgc_otg1: power-domain@2 {
303 #power-domain-cells = <0>;
304 reg = <IMX8M_POWER_DOMAIN_USB_OTG1>;
307 pgc_otg2: power-domain@3 {
308 #power-domain-cells = <0>;
309 reg = <IMX8M_POWER_DOMAIN_USB_OTG2>;
312 pgc_ddr1: power-domain@4 {
313 #power-domain-cells = <0>;
314 reg = <IMX8M_POWER_DOMAIN_DDR1>;
317 pgc_gpu: power-domain@5 {
318 #power-domain-cells = <0>;
319 reg = <IMX8M_POWER_DOMAIN_GPU>;
320 clocks = <&clk IMX8MQ_CLK_GPU_ROOT>,
321 <&clk IMX8MQ_CLK_GPU_SHADER_DIV>,
322 <&clk IMX8MQ_CLK_GPU_AXI>,
323 <&clk IMX8MQ_CLK_GPU_AHB>;
326 pgc_vpu: power-domain@6 {
327 #power-domain-cells = <0>;
328 reg = <IMX8M_POWER_DOMAIN_VPU>;
331 pgc_disp: power-domain@7 {
332 #power-domain-cells = <0>;
333 reg = <IMX8M_POWER_DOMAIN_DISP>;
336 pgc_mipi_csi1: power-domain@8 {
337 #power-domain-cells = <0>;
338 reg = <IMX8M_POWER_DOMAIN_MIPI_CSI1>;
341 pgc_mipi_csi2: power-domain@9 {
342 #power-domain-cells = <0>;
343 reg = <IMX8M_POWER_DOMAIN_MIPI_CSI2>;
346 pgc_pcie2: power-domain@a {
347 #power-domain-cells = <0>;
348 reg = <IMX8M_POWER_DOMAIN_PCIE2>;
354 bus@30400000 { /* AIPS2 */
355 compatible = "fsl,imx8mq-aips-bus", "simple-bus";
356 #address-cells = <1>;
358 ranges = <0x30400000 0x30400000 0x400000>;
361 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
362 reg = <0x30660000 0x10000>;
363 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
364 clocks = <&clk IMX8MQ_CLK_PWM1_ROOT>,
365 <&clk IMX8MQ_CLK_PWM1_ROOT>;
366 clock-names = "ipg", "per";
372 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
373 reg = <0x30670000 0x10000>;
374 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
375 clocks = <&clk IMX8MQ_CLK_PWM2_ROOT>,
376 <&clk IMX8MQ_CLK_PWM2_ROOT>;
377 clock-names = "ipg", "per";
383 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
384 reg = <0x30680000 0x10000>;
385 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
386 clocks = <&clk IMX8MQ_CLK_PWM3_ROOT>,
387 <&clk IMX8MQ_CLK_PWM3_ROOT>;
388 clock-names = "ipg", "per";
394 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
395 reg = <0x30690000 0x10000>;
396 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
397 clocks = <&clk IMX8MQ_CLK_PWM4_ROOT>,
398 <&clk IMX8MQ_CLK_PWM4_ROOT>;
399 clock-names = "ipg", "per";
405 bus@30800000 { /* AIPS3 */
406 compatible = "fsl,imx8mq-aips-bus", "simple-bus";
407 #address-cells = <1>;
409 ranges = <0x30800000 0x30800000 0x400000>,
410 <0x08000000 0x08000000 0x10000000>;
412 ecspi1: spi@30820000 {
413 #address-cells = <1>;
415 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
416 reg = <0x30820000 0x10000>;
417 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
418 clocks = <&clk IMX8MQ_CLK_ECSPI1_ROOT>,
419 <&clk IMX8MQ_CLK_ECSPI1_ROOT>;
420 clock-names = "ipg", "per";
424 ecspi2: spi@30830000 {
425 #address-cells = <1>;
427 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
428 reg = <0x30830000 0x10000>;
429 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
430 clocks = <&clk IMX8MQ_CLK_ECSPI2_ROOT>,
431 <&clk IMX8MQ_CLK_ECSPI2_ROOT>;
432 clock-names = "ipg", "per";
436 ecspi3: spi@30840000 {
437 #address-cells = <1>;
439 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
440 reg = <0x30840000 0x10000>;
441 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
442 clocks = <&clk IMX8MQ_CLK_ECSPI3_ROOT>,
443 <&clk IMX8MQ_CLK_ECSPI3_ROOT>;
444 clock-names = "ipg", "per";
448 uart1: serial@30860000 {
449 compatible = "fsl,imx8mq-uart",
451 reg = <0x30860000 0x10000>;
452 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
453 clocks = <&clk IMX8MQ_CLK_UART1_ROOT>,
454 <&clk IMX8MQ_CLK_UART1_ROOT>;
455 clock-names = "ipg", "per";
459 uart3: serial@30880000 {
460 compatible = "fsl,imx8mq-uart",
462 reg = <0x30880000 0x10000>;
463 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
464 clocks = <&clk IMX8MQ_CLK_UART3_ROOT>,
465 <&clk IMX8MQ_CLK_UART3_ROOT>;
466 clock-names = "ipg", "per";
470 uart2: serial@30890000 {
471 compatible = "fsl,imx8mq-uart",
473 reg = <0x30890000 0x10000>;
474 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
475 clocks = <&clk IMX8MQ_CLK_UART2_ROOT>,
476 <&clk IMX8MQ_CLK_UART2_ROOT>;
477 clock-names = "ipg", "per";
482 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
483 reg = <0x30a20000 0x10000>;
484 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
485 clocks = <&clk IMX8MQ_CLK_I2C1_ROOT>;
486 #address-cells = <1>;
492 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
493 reg = <0x30a30000 0x10000>;
494 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
495 clocks = <&clk IMX8MQ_CLK_I2C2_ROOT>;
496 #address-cells = <1>;
502 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
503 reg = <0x30a40000 0x10000>;
504 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
505 clocks = <&clk IMX8MQ_CLK_I2C3_ROOT>;
506 #address-cells = <1>;
512 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
513 reg = <0x30a50000 0x10000>;
514 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
515 clocks = <&clk IMX8MQ_CLK_I2C4_ROOT>;
516 #address-cells = <1>;
521 uart4: serial@30a60000 {
522 compatible = "fsl,imx8mq-uart",
524 reg = <0x30a60000 0x10000>;
525 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
526 clocks = <&clk IMX8MQ_CLK_UART4_ROOT>,
527 <&clk IMX8MQ_CLK_UART4_ROOT>;
528 clock-names = "ipg", "per";
532 usdhc1: mmc@30b40000 {
533 compatible = "fsl,imx8mq-usdhc",
535 reg = <0x30b40000 0x10000>;
536 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
537 clocks = <&clk IMX8MQ_CLK_DUMMY>,
538 <&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
539 <&clk IMX8MQ_CLK_USDHC1_ROOT>;
540 clock-names = "ipg", "ahb", "per";
541 assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
542 assigned-clock-rates = <400000000>;
543 fsl,tuning-start-tap = <20>;
544 fsl,tuning-step = <2>;
549 usdhc2: mmc@30b50000 {
550 compatible = "fsl,imx8mq-usdhc",
552 reg = <0x30b50000 0x10000>;
553 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
554 clocks = <&clk IMX8MQ_CLK_DUMMY>,
555 <&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
556 <&clk IMX8MQ_CLK_USDHC2_ROOT>;
557 clock-names = "ipg", "ahb", "per";
558 fsl,tuning-start-tap = <20>;
559 fsl,tuning-step = <2>;
564 qspi0: spi@30bb0000 {
565 #address-cells = <1>;
567 compatible = "fsl,imx8mq-qspi", "fsl,imx7d-qspi";
568 reg = <0x30bb0000 0x10000>,
569 <0x08000000 0x10000000>;
570 reg-names = "QuadSPI", "QuadSPI-memory";
571 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
572 clocks = <&clk IMX8MQ_CLK_QSPI_ROOT>,
573 <&clk IMX8MQ_CLK_QSPI_ROOT>;
574 clock-names = "qspi_en", "qspi";
578 fec1: ethernet@30be0000 {
579 compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec";
580 reg = <0x30be0000 0x10000>;
581 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
582 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
583 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
584 clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>,
585 <&clk IMX8MQ_CLK_ENET1_ROOT>,
586 <&clk IMX8MQ_CLK_ENET_TIMER>,
587 <&clk IMX8MQ_CLK_ENET_REF>,
588 <&clk IMX8MQ_CLK_ENET_PHY_REF>;
589 clock-names = "ipg", "ahb", "ptp",
590 "enet_clk_ref", "enet_out";
591 fsl,num-tx-queues = <3>;
592 fsl,num-rx-queues = <3>;
597 usb_dwc3_0: usb@38100000 {
598 compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
599 reg = <0x38100000 0x10000>;
600 clocks = <&clk IMX8MQ_CLK_USB_BUS>,
601 <&clk IMX8MQ_CLK_USB_CORE_REF>,
602 <&clk IMX8MQ_CLK_USB1_CTRL_ROOT>;
603 clock-names = "bus_early", "ref", "suspend";
604 assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>,
605 <&clk IMX8MQ_CLK_USB_CORE_REF>;
606 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
607 <&clk IMX8MQ_SYS1_PLL_100M>;
608 assigned-clock-rates = <500000000>, <100000000>;
609 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
610 phys = <&usb3_phy0>, <&usb3_phy0>;
611 phy-names = "usb2-phy", "usb3-phy";
612 power-domains = <&pgc_otg1>;
613 usb3-resume-missing-cas;
617 usb3_phy0: usb-phy@381f0040 {
618 compatible = "fsl,imx8mq-usb-phy";
619 reg = <0x381f0040 0x40>;
620 clocks = <&clk IMX8MQ_CLK_USB1_PHY_ROOT>;
622 assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>;
623 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
624 assigned-clock-rates = <100000000>;
629 usb_dwc3_1: usb@38200000 {
630 compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
631 reg = <0x38200000 0x10000>;
632 clocks = <&clk IMX8MQ_CLK_USB_BUS>,
633 <&clk IMX8MQ_CLK_USB_CORE_REF>,
634 <&clk IMX8MQ_CLK_USB2_CTRL_ROOT>;
635 clock-names = "bus_early", "ref", "suspend";
636 assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>,
637 <&clk IMX8MQ_CLK_USB_CORE_REF>;
638 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
639 <&clk IMX8MQ_SYS1_PLL_100M>;
640 assigned-clock-rates = <500000000>, <100000000>;
641 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
642 phys = <&usb3_phy1>, <&usb3_phy1>;
643 phy-names = "usb2-phy", "usb3-phy";
644 power-domains = <&pgc_otg2>;
645 usb3-resume-missing-cas;
649 usb3_phy1: usb-phy@382f0040 {
650 compatible = "fsl,imx8mq-usb-phy";
651 reg = <0x382f0040 0x40>;
652 clocks = <&clk IMX8MQ_CLK_USB2_PHY_ROOT>;
654 assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>;
655 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
656 assigned-clock-rates = <100000000>;
661 gic: interrupt-controller@38800000 {
662 compatible = "arm,gic-v3";
663 reg = <0x38800000 0x10000>, /* GIC Dist */
664 <0x38880000 0xc0000>, /* GICR */
665 <0x31000000 0x2000>, /* GICC */
666 <0x31010000 0x2000>, /* GICV */
667 <0x31020000 0x2000>; /* GICH */
668 #interrupt-cells = <3>;
669 interrupt-controller;
670 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
671 interrupt-parent = <&gic>;