sys/gnu/dts/arm64/freescale/imx8mq.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright 2017 NXP
   4  * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
   5  */
   6
   7 #include <dt-bindings/clock/imx8mq-clock.h>
   8 #include <dt-bindings/power/imx8mq-power.h>
   9 #include <dt-bindings/reset/imx8mq-reset.h>
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include "dt-bindings/input/input.h"
  12 #include <dt-bindings/interrupt-controller/arm-gic.h>
  13 #include <dt-bindings/thermal/thermal.h>
  14 #include "imx8mq-pinfunc.h"
  15
  16 / {
  17         interrupt-parent = <&gpc>;
  18
  19         #address-cells = <2>;
  20         #size-cells = <2>;
  21
  22         aliases {
  23                 gpio0 = &gpio1;
  24                 gpio1 = &gpio2;
  25                 gpio2 = &gpio3;
  26                 gpio3 = &gpio4;
  27                 gpio4 = &gpio5;
  28                 i2c0 = &i2c1;
  29                 i2c1 = &i2c2;
  30                 i2c2 = &i2c3;
  31                 i2c3 = &i2c4;
  32                 serial0 = &uart1;
  33                 serial1 = &uart2;
  34                 serial2 = &uart3;
  35                 serial3 = &uart4;
  36                 spi0 = &ecspi1;
  37                 spi1 = &ecspi2;
  38                 spi2 = &ecspi3;
  39         };
  40
  41         ckil: clock-ckil {
  42                 compatible = "fixed-clock";
  43                 #clock-cells = <0>;
  44                 clock-frequency = <32768>;
  45                 clock-output-names = "ckil";
  46         };
  47
  48         osc_25m: clock-osc-25m {
  49                 compatible = "fixed-clock";
  50                 #clock-cells = <0>;
  51                 clock-frequency = <25000000>;
  52                 clock-output-names = "osc_25m";
  53         };
  54
  55         osc_27m: clock-osc-27m {
  56                 compatible = "fixed-clock";
  57                 #clock-cells = <0>;
  58                 clock-frequency = <27000000>;
  59                 clock-output-names = "osc_27m";
  60         };
  61
  62         clk_ext1: clock-ext1 {
  63                 compatible = "fixed-clock";
  64                 #clock-cells = <0>;
  65                 clock-frequency = <133000000>;
  66                 clock-output-names = "clk_ext1";
  67         };
  68
  69         clk_ext2: clock-ext2 {
  70                 compatible = "fixed-clock";
  71                 #clock-cells = <0>;
  72                 clock-frequency = <133000000>;
  73                 clock-output-names = "clk_ext2";
  74         };
  75
  76         clk_ext3: clock-ext3 {
  77                 compatible = "fixed-clock";
  78                 #clock-cells = <0>;
  79                 clock-frequency = <133000000>;
  80                 clock-output-names = "clk_ext3";
  81         };
  82
  83         clk_ext4: clock-ext4 {
  84                 compatible = "fixed-clock";
  85                 #clock-cells = <0>;
  86                 clock-frequency= <133000000>;
  87                 clock-output-names = "clk_ext4";
  88         };
  89
  90         cpus {
  91                 #address-cells = <1>;
  92                 #size-cells = <0>;
  93
  94                 A53_0: cpu@0 {
  95                         device_type = "cpu";
  96                         compatible = "arm,cortex-a53";
  97                         reg = <0x0>;
  98                         clock-latency = <61036>; /* two CLK32 periods */
  99                         clocks = <&clk IMX8MQ_CLK_ARM>;
 100                         enable-method = "psci";
 101                         next-level-cache = <&A53_L2>;
 102                         operating-points-v2 = <&a53_opp_table>;
 103                         #cooling-cells = <2>;
 104                         nvmem-cells = <&cpu_speed_grade>;
 105                         nvmem-cell-names = "speed_grade";
 106                 };
 107
 108                 A53_1: cpu@1 {
 109                         device_type = "cpu";
 110                         compatible = "arm,cortex-a53";
 111                         reg = <0x1>;
 112                         clock-latency = <61036>; /* two CLK32 periods */
 113                         clocks = <&clk IMX8MQ_CLK_ARM>;
 114                         enable-method = "psci";
 115                         next-level-cache = <&A53_L2>;
 116                         operating-points-v2 = <&a53_opp_table>;
 117                         #cooling-cells = <2>;
 118                 };
 119
 120                 A53_2: cpu@2 {
 121                         device_type = "cpu";
 122                         compatible = "arm,cortex-a53";
 123                         reg = <0x2>;
 124                         clock-latency = <61036>; /* two CLK32 periods */
 125                         clocks = <&clk IMX8MQ_CLK_ARM>;
 126                         enable-method = "psci";
 127                         next-level-cache = <&A53_L2>;
 128                         operating-points-v2 = <&a53_opp_table>;
 129                         #cooling-cells = <2>;
 130                 };
 131
 132                 A53_3: cpu@3 {
 133                         device_type = "cpu";
 134                         compatible = "arm,cortex-a53";
 135                         reg = <0x3>;
 136                         clock-latency = <61036>; /* two CLK32 periods */
 137                         clocks = <&clk IMX8MQ_CLK_ARM>;
 138                         enable-method = "psci";
 139                         next-level-cache = <&A53_L2>;
 140                         operating-points-v2 = <&a53_opp_table>;
 141                         #cooling-cells = <2>;
 142                 };
 143
 144                 A53_L2: l2-cache0 {
 145                         compatible = "cache";
 146                 };
 147         };
 148
 149         a53_opp_table: opp-table {
 150                 compatible = "operating-points-v2";
 151                 opp-shared;
 152
 153                 opp-800000000 {
 154                         opp-hz = /bits/ 64 <800000000>;
 155                         opp-microvolt = <900000>;
 156                         /* Industrial only */
 157                         opp-supported-hw = <0xf>, <0x4>;
 158                         clock-latency-ns = <150000>;
 159                         opp-suspend;
 160                 };
 161
 162                 opp-1000000000 {
 163                         opp-hz = /bits/ 64 <1000000000>;
 164                         opp-microvolt = <900000>;
 165                         /* Consumer only */
 166                         opp-supported-hw = <0xe>, <0x3>;
 167                         clock-latency-ns = <150000>;
 168                         opp-suspend;
 169                 };
 170
 171                 opp-1300000000 {
 172                         opp-hz = /bits/ 64 <1300000000>;
 173                         opp-microvolt = <1000000>;
 174                         opp-supported-hw = <0xc>, <0x4>;
 175                         clock-latency-ns = <150000>;
 176                         opp-suspend;
 177                 };
 178
 179                 opp-1500000000 {
 180                         opp-hz = /bits/ 64 <1500000000>;
 181                         opp-microvolt = <1000000>;
 182                         opp-supported-hw = <0x8>, <0x3>;
 183                         clock-latency-ns = <150000>;
 184                         opp-suspend;
 185                 };
 186         };
 187
 188         pmu {
 189                 compatible = "arm,cortex-a53-pmu";
 190                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
 191                 interrupt-parent = <&gic>;
 192                 interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>;
 193         };
 194
 195         psci {
 196                 compatible = "arm,psci-1.0";
 197                 method = "smc";
 198         };
 199
 200         thermal-zones {
 201                 cpu_thermal: cpu-thermal {
 202                         polling-delay-passive = <250>;
 203                         polling-delay = <2000>;
 204                         thermal-sensors = <&tmu 0>;
 205
 206                         trips {
 207                                 cpu_alert: cpu-alert {
 208                                         temperature = <80000>;
 209                                         hysteresis = <2000>;
 210                                         type = "passive";
 211                                 };
 212
 213                                 cpu-crit {
 214                                         temperature = <90000>;
 215                                         hysteresis = <2000>;
 216                                         type = "critical";
 217                                 };
 218                         };
 219
 220                         cooling-maps {
 221                                 map0 {
 222                                         trip = <&cpu_alert>;
 223                                         cooling-device =
 224                                                 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 225                                                 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 226                                                 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 227                                                 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 228                                 };
 229                         };
 230                 };
 231
 232                 gpu-thermal {
 233                         polling-delay-passive = <250>;
 234                         polling-delay = <2000>;
 235                         thermal-sensors = <&tmu 1>;
 236
 237                         trips {
 238                                 gpu_alert: gpu-alert {
 239                                         temperature = <80000>;
 240                                         hysteresis = <2000>;
 241                                         type = "passive";
 242                                 };
 243
 244                                 gpu-crit {
 245                                         temperature = <90000>;
 246                                         hysteresis = <2000>;
 247                                         type = "critical";
 248                                 };
 249                         };
 250
 251                         cooling-maps {
 252                                 map0 {
 253                                         trip = <&gpu_alert>;
 254                                         cooling-device =
 255                                                 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 256                                 };
 257                         };
 258                 };
 259
 260                 vpu-thermal {
 261                         polling-delay-passive = <250>;
 262                         polling-delay = <2000>;
 263                         thermal-sensors = <&tmu 2>;
 264
 265                         trips {
 266                                 vpu-crit {
 267                                         temperature = <90000>;
 268                                         hysteresis = <2000>;
 269                                         type = "critical";
 270                                 };
 271                         };
 272                 };
 273         };
 274
 275         timer {
 276                 compatible = "arm,armv8-timer";
 277                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
 278                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
 279                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
 280                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
 281                 interrupt-parent = <&gic>;
 282                 arm,no-tick-in-suspend;
 283         };
 284
 285         soc@0 {
 286                 compatible = "simple-bus";
 287                 #address-cells = <1>;
 288                 #size-cells = <1>;
 289                 ranges = <0x0 0x0 0x0 0x3e000000>;
 290                 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
 291
 292                 bus@30000000 { /* AIPS1 */
 293                         compatible = "fsl,aips-bus", "simple-bus";
 294                         reg = <0x30000000 0x400000>;
 295                         #address-cells = <1>;
 296                         #size-cells = <1>;
 297                         ranges = <0x30000000 0x30000000 0x400000>;
 298
 299                         sai1: sai@30010000 {
 300                                 #sound-dai-cells = <0>;
 301                                 compatible = "fsl,imx8mq-sai";
 302                                 reg = <0x30010000 0x10000>;
 303                                 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 304                                 clocks = <&clk IMX8MQ_CLK_SAI1_IPG>,
 305                                          <&clk IMX8MQ_CLK_SAI1_ROOT>,
 306                                          <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
 307                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
 308                                 dmas = <&sdma2 8 24 0>, <&sdma1 9 24 0>;
 309                                 dma-names = "rx", "tx";
 310                                 status = "disabled";
 311                         };
 312
 313                         sai6: sai@30030000 {
 314                                 #sound-dai-cells = <0>;
 315                                 compatible = "fsl,imx8mq-sai";
 316                                 reg = <0x30030000 0x10000>;
 317                                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 318                                 clocks = <&clk IMX8MQ_CLK_SAI6_IPG>,
 319                                          <&clk IMX8MQ_CLK_SAI6_ROOT>,
 320                                          <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
 321                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
 322                                 dmas = <&sdma2 4 24 0>, <&sdma2 5 24 0>;
 323                                 dma-names = "rx", "tx";
 324                                 status = "disabled";
 325                         };
 326
 327                         sai5: sai@30040000 {
 328                                 #sound-dai-cells = <0>;
 329                                 compatible = "fsl,imx8mq-sai";
 330                                 reg = <0x30040000 0x10000>;
 331                                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 332                                 clocks = <&clk IMX8MQ_CLK_SAI5_IPG>,
 333                                          <&clk IMX8MQ_CLK_SAI5_ROOT>,
 334                                          <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
 335                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
 336                                 dmas = <&sdma2 2 24 0>, <&sdma2 3 24 0>;
 337                                 dma-names = "rx", "tx";
 338                                 status = "disabled";
 339                         };
 340
 341                         sai4: sai@30050000 {
 342                                 #sound-dai-cells = <0>;
 343                                 compatible = "fsl,imx8mq-sai";
 344                                 reg = <0x30050000 0x10000>;
 345                                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 346                                 clocks = <&clk IMX8MQ_CLK_SAI4_IPG>,
 347                                          <&clk IMX8MQ_CLK_SAI4_ROOT>,
 348                                          <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
 349                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
 350                                 dmas = <&sdma2 0 24 0>, <&sdma2 1 24 0>;
 351                                 dma-names = "rx", "tx";
 352                                 status = "disabled";
 353                         };
 354
 355                         gpio1: gpio@30200000 {
 356                                 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
 357                                 reg = <0x30200000 0x10000>;
 358                                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
 359                                              <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 360                                 clocks = <&clk IMX8MQ_CLK_GPIO1_ROOT>;
 361                                 gpio-controller;
 362                                 #gpio-cells = <2>;
 363                                 interrupt-controller;
 364                                 #interrupt-cells = <2>;
 365                                 gpio-ranges = <&iomuxc 0 10 30>;
 366                         };
 367
 368                         gpio2: gpio@30210000 {
 369                                 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
 370                                 reg = <0x30210000 0x10000>;
 371                                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 372                                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 373                                 clocks = <&clk IMX8MQ_CLK_GPIO2_ROOT>;
 374                                 gpio-controller;
 375                                 #gpio-cells = <2>;
 376                                 interrupt-controller;
 377                                 #interrupt-cells = <2>;
 378                                 gpio-ranges = <&iomuxc 0 40 21>;
 379                         };
 380
 381                         gpio3: gpio@30220000 {
 382                                 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
 383                                 reg = <0x30220000 0x10000>;
 384                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 385                                              <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 386                                 clocks = <&clk IMX8MQ_CLK_GPIO3_ROOT>;
 387                                 gpio-controller;
 388                                 #gpio-cells = <2>;
 389                                 interrupt-controller;
 390                                 #interrupt-cells = <2>;
 391                                 gpio-ranges = <&iomuxc 0 61 26>;
 392                         };
 393
 394                         gpio4: gpio@30230000 {
 395                                 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
 396                                 reg = <0x30230000 0x10000>;
 397                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 398                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 399                                 clocks = <&clk IMX8MQ_CLK_GPIO4_ROOT>;
 400                                 gpio-controller;
 401                                 #gpio-cells = <2>;
 402                                 interrupt-controller;
 403                                 #interrupt-cells = <2>;
 404                                 gpio-ranges = <&iomuxc 0 87 32>;
 405                         };
 406
 407                         gpio5: gpio@30240000 {
 408                                 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
 409                                 reg = <0x30240000 0x10000>;
 410                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 411                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 412                                 clocks = <&clk IMX8MQ_CLK_GPIO5_ROOT>;
 413                                 gpio-controller;
 414                                 #gpio-cells = <2>;
 415                                 interrupt-controller;
 416                                 #interrupt-cells = <2>;
 417                                 gpio-ranges = <&iomuxc 0 119 30>;
 418                         };
 419
 420                         tmu: tmu@30260000 {
 421                                 compatible = "fsl,imx8mq-tmu";
 422                                 reg = <0x30260000 0x10000>;
 423                                 interrupt = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 424                                 clocks = <&clk IMX8MQ_CLK_TMU_ROOT>;
 425                                 little-endian;
 426                                 fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>;
 427                                 fsl,tmu-calibration = <0x00000000 0x00000023
 428                                                        0x00000001 0x00000029
 429                                                        0x00000002 0x0000002f
 430                                                        0x00000003 0x00000035
 431                                                        0x00000004 0x0000003d
 432                                                        0x00000005 0x00000043
 433                                                        0x00000006 0x0000004b
 434                                                        0x00000007 0x00000051
 435                                                        0x00000008 0x00000057
 436                                                        0x00000009 0x0000005f
 437                                                        0x0000000a 0x00000067
 438                                                        0x0000000b 0x0000006f
 439
 440                                                        0x00010000 0x0000001b
 441                                                        0x00010001 0x00000023
 442                                                        0x00010002 0x0000002b
 443                                                        0x00010003 0x00000033
 444                                                        0x00010004 0x0000003b
 445                                                        0x00010005 0x00000043
 446                                                        0x00010006 0x0000004b
 447                                                        0x00010007 0x00000055
 448                                                        0x00010008 0x0000005d
 449                                                        0x00010009 0x00000067
 450                                                        0x0001000a 0x00000070
 451
 452                                                        0x00020000 0x00000017
 453                                                        0x00020001 0x00000023
 454                                                        0x00020002 0x0000002d
 455                                                        0x00020003 0x00000037
 456                                                        0x00020004 0x00000041
 457                                                        0x00020005 0x0000004b
 458                                                        0x00020006 0x00000057
 459                                                        0x00020007 0x00000063
 460                                                        0x00020008 0x0000006f
 461
 462                                                        0x00030000 0x00000015
 463                                                        0x00030001 0x00000021
 464                                                        0x00030002 0x0000002d
 465                                                        0x00030003 0x00000039
 466                                                        0x00030004 0x00000045
 467                                                        0x00030005 0x00000053
 468                                                        0x00030006 0x0000005f
 469                                                        0x00030007 0x00000071>;
 470                                 #thermal-sensor-cells =  <1>;
 471                         };
 472
 473                         wdog1: watchdog@30280000 {
 474                                 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
 475                                 reg = <0x30280000 0x10000>;
 476                                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 477                                 clocks = <&clk IMX8MQ_CLK_WDOG1_ROOT>;
 478                                 status = "disabled";
 479                         };
 480
 481                         wdog2: watchdog@30290000 {
 482                                 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
 483                                 reg = <0x30290000 0x10000>;
 484                                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 485                                 clocks = <&clk IMX8MQ_CLK_WDOG2_ROOT>;
 486                                 status = "disabled";
 487                         };
 488
 489                         wdog3: watchdog@302a0000 {
 490                                 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
 491                                 reg = <0x302a0000 0x10000>;
 492                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 493                                 clocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>;
 494                                 status = "disabled";
 495                         };
 496
 497                         sdma2: sdma@302c0000 {
 498                                 compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma";
 499                                 reg = <0x302c0000 0x10000>;
 500                                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 501                                 clocks = <&clk IMX8MQ_CLK_SDMA2_ROOT>,
 502                                          <&clk IMX8MQ_CLK_SDMA2_ROOT>;
 503                                 clock-names = "ipg", "ahb";
 504                                 #dma-cells = <3>;
 505                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
 506                         };
 507
 508                         lcdif: lcd-controller@30320000 {
 509                                 compatible = "fsl,imx8mq-lcdif", "fsl,imx28-lcdif";
 510                                 reg = <0x30320000 0x10000>;
 511                                 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 512                                 clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>;
 513                                 clock-names = "pix";
 514                                 assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
 515                                                   <&clk IMX8MQ_VIDEO_PLL1_BYPASS>,
 516                                                   <&clk IMX8MQ_CLK_LCDIF_PIXEL>,
 517                                                   <&clk IMX8MQ_VIDEO_PLL1>;
 518                                 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>,
 519                                                   <&clk IMX8MQ_VIDEO_PLL1>,
 520                                                   <&clk IMX8MQ_VIDEO_PLL1_OUT>;
 521                                 assigned-clock-rates = <0>, <0>, <0>, <594000000>;
 522                                 status = "disabled";
 523                         };
 524
 525                         iomuxc: pinctrl@30330000 {
 526                                 compatible = "fsl,imx8mq-iomuxc";
 527                                 reg = <0x30330000 0x10000>;
 528                         };
 529
 530                         iomuxc_gpr: syscon@30340000 {
 531                                 compatible = "fsl,imx8mq-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr",
 532                                              "syscon", "simple-mfd";
 533                                 reg = <0x30340000 0x10000>;
 534
 535                                 mux: mux-controller {
 536                                         compatible = "mmio-mux";
 537                                         #mux-control-cells = <1>;
 538                                         mux-reg-masks = <0x34 0x00000004>; /* MIPI_MUX_SEL */
 539                                 };
 540                         };
 541
 542                         ocotp: ocotp-ctrl@30350000 {
 543                                 compatible = "fsl,imx8mq-ocotp", "syscon";
 544                                 reg = <0x30350000 0x10000>;
 545                                 clocks = <&clk IMX8MQ_CLK_OCOTP_ROOT>;
 546                                 #address-cells = <1>;
 547                                 #size-cells = <1>;
 548
 549                                 cpu_speed_grade: speed-grade@10 {
 550                                         reg = <0x10 4>;
 551                                 };
 552                         };
 553
 554                         anatop: syscon@30360000 {
 555                                 compatible = "fsl,imx8mq-anatop", "syscon";
 556                                 reg = <0x30360000 0x10000>;
 557                                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 558                         };
 559
 560                         snvs: snvs@30370000 {
 561                                 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
 562                                 reg = <0x30370000 0x10000>;
 563
 564                                 snvs_rtc: snvs-rtc-lp{
 565                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 566                                         regmap =<&snvs>;
 567                                         offset = <0x34>;
 568                                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 569                                                 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 570                                         clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>;
 571                                         clock-names = "snvs-rtc";
 572                                 };
 573
 574                                 snvs_pwrkey: snvs-powerkey {
 575                                         compatible = "fsl,sec-v4.0-pwrkey";
 576                                         regmap = <&snvs>;
 577                                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 578                                         clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>;
 579                                         clock-names = "snvs-pwrkey";
 580                                         linux,keycode = <KEY_POWER>;
 581                                         wakeup-source;
 582                                         status = "disabled";
 583                                 };
 584                         };
 585
 586                         clk: clock-controller@30380000 {
 587                                 compatible = "fsl,imx8mq-ccm";
 588                                 reg = <0x30380000 0x10000>;
 589                                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
 590                                              <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 591                                 #clock-cells = <1>;
 592                                 clocks = <&ckil>, <&osc_25m>, <&osc_27m>,
 593                                          <&clk_ext1>, <&clk_ext2>,
 594                                          <&clk_ext3>, <&clk_ext4>;
 595                                 clock-names = "ckil", "osc_25m", "osc_27m",
 596                                               "clk_ext1", "clk_ext2",
 597                                               "clk_ext3", "clk_ext4";
 598                                 assigned-clocks = <&clk IMX8MQ_CLK_NOC>;
 599                                 assigned-clock-rates = <800000000>;
 600                         };
 601
 602                         src: reset-controller@30390000 {
 603                                 compatible = "fsl,imx8mq-src", "syscon";
 604                                 reg = <0x30390000 0x10000>;
 605                                 #reset-cells = <1>;
 606                         };
 607
 608                         gpc: gpc@303a0000 {
 609                                 compatible = "fsl,imx8mq-gpc";
 610                                 reg = <0x303a0000 0x10000>;
 611                                 interrupt-parent = <&gic>;
 612                                 interrupt-controller;
 613                                 #interrupt-cells = <3>;
 614
 615                                 pgc {
 616                                         #address-cells = <1>;
 617                                         #size-cells = <0>;
 618
 619                                         pgc_mipi: power-domain@0 {
 620                                                 #power-domain-cells = <0>;
 621                                                 reg = <IMX8M_POWER_DOMAIN_MIPI>;
 622                                         };
 623
 624                                         /*
 625                                          * As per comment in ATF source code:
 626                                          *
 627                                          * PCIE1 and PCIE2 share the
 628                                          * same reset signal, if we
 629                                          * power down PCIE2, PCIE1
 630                                          * will be held in reset too.
 631                                          *
 632                                          * So instead of creating two
 633                                          * separate power domains for
 634                                          * PCIE1 and PCIE2 we create a
 635                                          * link between both and use
 636                                          * it as a shared PCIE power
 637                                          * domain.
 638                                          */
 639                                         pgc_pcie: power-domain@1 {
 640                                                 #power-domain-cells = <0>;
 641                                                 reg = <IMX8M_POWER_DOMAIN_PCIE1>;
 642                                                 power-domains = <&pgc_pcie2>;
 643                                         };
 644
 645                                         pgc_otg1: power-domain@2 {
 646                                                 #power-domain-cells = <0>;
 647                                                 reg = <IMX8M_POWER_DOMAIN_USB_OTG1>;
 648                                         };
 649
 650                                         pgc_otg2: power-domain@3 {
 651                                                 #power-domain-cells = <0>;
 652                                                 reg = <IMX8M_POWER_DOMAIN_USB_OTG2>;
 653                                         };
 654
 655                                         pgc_ddr1: power-domain@4 {
 656                                                 #power-domain-cells = <0>;
 657                                                 reg = <IMX8M_POWER_DOMAIN_DDR1>;
 658                                         };
 659
 660                                         pgc_gpu: power-domain@5 {
 661                                                 #power-domain-cells = <0>;
 662                                                 reg = <IMX8M_POWER_DOMAIN_GPU>;
 663                                                 clocks = <&clk IMX8MQ_CLK_GPU_ROOT>,
 664                                                          <&clk IMX8MQ_CLK_GPU_SHADER_DIV>,
 665                                                          <&clk IMX8MQ_CLK_GPU_AXI>,
 666                                                          <&clk IMX8MQ_CLK_GPU_AHB>;
 667                                         };
 668
 669                                         pgc_vpu: power-domain@6 {
 670                                                 #power-domain-cells = <0>;
 671                                                 reg = <IMX8M_POWER_DOMAIN_VPU>;
 672                                         };
 673
 674                                         pgc_disp: power-domain@7 {
 675                                                 #power-domain-cells = <0>;
 676                                                 reg = <IMX8M_POWER_DOMAIN_DISP>;
 677                                         };
 678
 679                                         pgc_mipi_csi1: power-domain@8 {
 680                                                 #power-domain-cells = <0>;
 681                                                 reg = <IMX8M_POWER_DOMAIN_MIPI_CSI1>;
 682                                         };
 683
 684                                         pgc_mipi_csi2: power-domain@9 {
 685                                                 #power-domain-cells = <0>;
 686                                                 reg = <IMX8M_POWER_DOMAIN_MIPI_CSI2>;
 687                                         };
 688
 689                                         pgc_pcie2: power-domain@a {
 690                                                 #power-domain-cells = <0>;
 691                                                 reg = <IMX8M_POWER_DOMAIN_PCIE2>;
 692                                         };
 693                                 };
 694                         };
 695                 };
 696
 697                 bus@30400000 { /* AIPS2 */
 698                         compatible = "fsl,aips-bus", "simple-bus";
 699                         reg = <0x30400000 0x400000>;
 700                         #address-cells = <1>;
 701                         #size-cells = <1>;
 702                         ranges = <0x30400000 0x30400000 0x400000>;
 703
 704                         pwm1: pwm@30660000 {
 705                                 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
 706                                 reg = <0x30660000 0x10000>;
 707                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 708                                 clocks = <&clk IMX8MQ_CLK_PWM1_ROOT>,
 709                                          <&clk IMX8MQ_CLK_PWM1_ROOT>;
 710                                 clock-names = "ipg", "per";
 711                                 #pwm-cells = <2>;
 712                                 status = "disabled";
 713                         };
 714
 715                         pwm2: pwm@30670000 {
 716                                 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
 717                                 reg = <0x30670000 0x10000>;
 718                                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 719                                 clocks = <&clk IMX8MQ_CLK_PWM2_ROOT>,
 720                                          <&clk IMX8MQ_CLK_PWM2_ROOT>;
 721                                 clock-names = "ipg", "per";
 722                                 #pwm-cells = <2>;
 723                                 status = "disabled";
 724                         };
 725
 726                         pwm3: pwm@30680000 {
 727                                 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
 728                                 reg = <0x30680000 0x10000>;
 729                                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 730                                 clocks = <&clk IMX8MQ_CLK_PWM3_ROOT>,
 731                                          <&clk IMX8MQ_CLK_PWM3_ROOT>;
 732                                 clock-names = "ipg", "per";
 733                                 #pwm-cells = <2>;
 734                                 status = "disabled";
 735                         };
 736
 737                         pwm4: pwm@30690000 {
 738                                 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
 739                                 reg = <0x30690000 0x10000>;
 740                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 741                                 clocks = <&clk IMX8MQ_CLK_PWM4_ROOT>,
 742                                          <&clk IMX8MQ_CLK_PWM4_ROOT>;
 743                                 clock-names = "ipg", "per";
 744                                 #pwm-cells = <2>;
 745                                 status = "disabled";
 746                         };
 747
 748                         system_counter: timer@306a0000 {
 749                                 compatible = "nxp,sysctr-timer";
 750                                 reg = <0x306a0000 0x20000>;
 751                                 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 752                                 clocks = <&osc_25m>;
 753                                 clock-names = "per";
 754                         };
 755                 };
 756
 757                 bus@30800000 { /* AIPS3 */
 758                         compatible = "fsl,aips-bus", "simple-bus";
 759                         reg = <0x30800000 0x400000>;
 760                         #address-cells = <1>;
 761                         #size-cells = <1>;
 762                         ranges = <0x30800000 0x30800000 0x400000>,
 763                                  <0x08000000 0x08000000 0x10000000>;
 764
 765                         ecspi1: spi@30820000 {
 766                                 #address-cells = <1>;
 767                                 #size-cells = <0>;
 768                                 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
 769                                 reg = <0x30820000 0x10000>;
 770                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 771                                 clocks = <&clk IMX8MQ_CLK_ECSPI1_ROOT>,
 772                                          <&clk IMX8MQ_CLK_ECSPI1_ROOT>;
 773                                 clock-names = "ipg", "per";
 774                                 status = "disabled";
 775                         };
 776
 777                         ecspi2: spi@30830000 {
 778                                 #address-cells = <1>;
 779                                 #size-cells = <0>;
 780                                 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
 781                                 reg = <0x30830000 0x10000>;
 782                                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 783                                 clocks = <&clk IMX8MQ_CLK_ECSPI2_ROOT>,
 784                                          <&clk IMX8MQ_CLK_ECSPI2_ROOT>;
 785                                 clock-names = "ipg", "per";
 786                                 status = "disabled";
 787                         };
 788
 789                         ecspi3: spi@30840000 {
 790                                 #address-cells = <1>;
 791                                 #size-cells = <0>;
 792                                 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
 793                                 reg = <0x30840000 0x10000>;
 794                                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 795                                 clocks = <&clk IMX8MQ_CLK_ECSPI3_ROOT>,
 796                                          <&clk IMX8MQ_CLK_ECSPI3_ROOT>;
 797                                 clock-names = "ipg", "per";
 798                                 status = "disabled";
 799                         };
 800
 801                         uart1: serial@30860000 {
 802                                 compatible = "fsl,imx8mq-uart",
 803                                              "fsl,imx6q-uart";
 804                                 reg = <0x30860000 0x10000>;
 805                                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 806                                 clocks = <&clk IMX8MQ_CLK_UART1_ROOT>,
 807                                          <&clk IMX8MQ_CLK_UART1_ROOT>;
 808                                 clock-names = "ipg", "per";
 809                                 status = "disabled";
 810                         };
 811
 812                         uart3: serial@30880000 {
 813                                 compatible = "fsl,imx8mq-uart",
 814                                              "fsl,imx6q-uart";
 815                                 reg = <0x30880000 0x10000>;
 816                                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 817                                 clocks = <&clk IMX8MQ_CLK_UART3_ROOT>,
 818                                          <&clk IMX8MQ_CLK_UART3_ROOT>;
 819                                 clock-names = "ipg", "per";
 820                                 status = "disabled";
 821                         };
 822
 823                         uart2: serial@30890000 {
 824                                 compatible = "fsl,imx8mq-uart",
 825                                              "fsl,imx6q-uart";
 826                                 reg = <0x30890000 0x10000>;
 827                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 828                                 clocks = <&clk IMX8MQ_CLK_UART2_ROOT>,
 829                                          <&clk IMX8MQ_CLK_UART2_ROOT>;
 830                                 clock-names = "ipg", "per";
 831                                 status = "disabled";
 832                         };
 833
 834                         sai2: sai@308b0000 {
 835                                 #sound-dai-cells = <0>;
 836                                 compatible = "fsl,imx8mq-sai";
 837                                 reg = <0x308b0000 0x10000>;
 838                                 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 839                                 clocks = <&clk IMX8MQ_CLK_SAI2_IPG>,
 840                                          <&clk IMX8MQ_CLK_SAI2_ROOT>,
 841                                          <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
 842                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
 843                                 dmas = <&sdma1 10 24 0>, <&sdma1 11 24 0>;
 844                                 dma-names = "rx", "tx";
 845                                 status = "disabled";
 846                         };
 847
 848                         sai3: sai@308c0000 {
 849                                 #sound-dai-cells = <0>;
 850                                 compatible = "fsl,imx8mq-sai";
 851                                 reg = <0x308c0000 0x10000>;
 852                                 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 853                                 clocks = <&clk IMX8MQ_CLK_SAI3_IPG>,
 854                                          <&clk IMX8MQ_CLK_SAI3_ROOT>,
 855                                          <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
 856                                 clock-names = "bus", "mclk1", "mclk2", "mclk3";
 857                                 dmas = <&sdma1 12 24 0>, <&sdma1 13 24 0>;
 858                                 dma-names = "rx", "tx";
 859                                 status = "disabled";
 860                         };
 861
 862                         crypto: crypto@30900000 {
 863                                 compatible = "fsl,sec-v4.0";
 864                                 #address-cells = <1>;
 865                                 #size-cells = <1>;
 866                                 reg = <0x30900000 0x40000>;
 867                                 ranges = <0 0x30900000 0x40000>;
 868                                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 869                                 clocks = <&clk IMX8MQ_CLK_AHB>,
 870                                          <&clk IMX8MQ_CLK_IPG_ROOT>;
 871                                 clock-names = "aclk", "ipg";
 872
 873                                 sec_jr0: jr@1000 {
 874                                         compatible = "fsl,sec-v4.0-job-ring";
 875                                         reg = <0x1000 0x1000>;
 876                                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 877                                 };
 878
 879                                 sec_jr1: jr@2000 {
 880                                         compatible = "fsl,sec-v4.0-job-ring";
 881                                         reg = <0x2000 0x1000>;
 882                                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 883                                 };
 884
 885                                 sec_jr2: jr@3000 {
 886                                         compatible = "fsl,sec-v4.0-job-ring";
 887                                         reg = <0x3000 0x1000>;
 888                                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 889                                 };
 890                         };
 891
 892                         dphy: dphy@30a00300 {
 893                                 compatible = "fsl,imx8mq-mipi-dphy";
 894                                 reg = <0x30a00300 0x100>;
 895                                 clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
 896                                 clock-names = "phy_ref";
 897                                 assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
 898                                 assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>;
 899                                 assigned-clock-rates = <24000000>;
 900                                 #phy-cells = <0>;
 901                                 power-domains = <&pgc_mipi>;
 902                                 status = "disabled";
 903                         };
 904
 905                         i2c1: i2c@30a20000 {
 906                                 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
 907                                 reg = <0x30a20000 0x10000>;
 908                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 909                                 clocks = <&clk IMX8MQ_CLK_I2C1_ROOT>;
 910                                 #address-cells = <1>;
 911                                 #size-cells = <0>;
 912                                 status = "disabled";
 913                         };
 914
 915                         i2c2: i2c@30a30000 {
 916                                 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
 917                                 reg = <0x30a30000 0x10000>;
 918                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 919                                 clocks = <&clk IMX8MQ_CLK_I2C2_ROOT>;
 920                                 #address-cells = <1>;
 921                                 #size-cells = <0>;
 922                                 status = "disabled";
 923                         };
 924
 925                         i2c3: i2c@30a40000 {
 926                                 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
 927                                 reg = <0x30a40000 0x10000>;
 928                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 929                                 clocks = <&clk IMX8MQ_CLK_I2C3_ROOT>;
 930                                 #address-cells = <1>;
 931                                 #size-cells = <0>;
 932                                 status = "disabled";
 933                         };
 934
 935                         i2c4: i2c@30a50000 {
 936                                 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
 937                                 reg = <0x30a50000 0x10000>;
 938                                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 939                                 clocks = <&clk IMX8MQ_CLK_I2C4_ROOT>;
 940                                 #address-cells = <1>;
 941                                 #size-cells = <0>;
 942                                 status = "disabled";
 943                         };
 944
 945                         uart4: serial@30a60000 {
 946                                 compatible = "fsl,imx8mq-uart",
 947                                              "fsl,imx6q-uart";
 948                                 reg = <0x30a60000 0x10000>;
 949                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 950                                 clocks = <&clk IMX8MQ_CLK_UART4_ROOT>,
 951                                          <&clk IMX8MQ_CLK_UART4_ROOT>;
 952                                 clock-names = "ipg", "per";
 953                                 status = "disabled";
 954                         };
 955
 956                         usdhc1: mmc@30b40000 {
 957                                 compatible = "fsl,imx8mq-usdhc",
 958                                              "fsl,imx7d-usdhc";
 959                                 reg = <0x30b40000 0x10000>;
 960                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 961                                 clocks = <&clk IMX8MQ_CLK_IPG_ROOT>,
 962                                          <&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
 963                                          <&clk IMX8MQ_CLK_USDHC1_ROOT>;
 964                                 clock-names = "ipg", "ahb", "per";
 965                                 fsl,tuning-start-tap = <20>;
 966                                 fsl,tuning-step = <2>;
 967                                 bus-width = <4>;
 968                                 status = "disabled";
 969                         };
 970
 971                         usdhc2: mmc@30b50000 {
 972                                 compatible = "fsl,imx8mq-usdhc",
 973                                              "fsl,imx7d-usdhc";
 974                                 reg = <0x30b50000 0x10000>;
 975                                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 976                                 clocks = <&clk IMX8MQ_CLK_IPG_ROOT>,
 977                                          <&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
 978                                          <&clk IMX8MQ_CLK_USDHC2_ROOT>;
 979                                 clock-names = "ipg", "ahb", "per";
 980                                 fsl,tuning-start-tap = <20>;
 981                                 fsl,tuning-step = <2>;
 982                                 bus-width = <4>;
 983                                 status = "disabled";
 984                         };
 985
 986                         qspi0: spi@30bb0000 {
 987                                 #address-cells = <1>;
 988                                 #size-cells = <0>;
 989                                 compatible = "fsl,imx8mq-qspi", "fsl,imx7d-qspi";
 990                                 reg = <0x30bb0000 0x10000>,
 991                                       <0x08000000 0x10000000>;
 992                                 reg-names = "QuadSPI", "QuadSPI-memory";
 993                                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 994                                 clocks = <&clk IMX8MQ_CLK_QSPI_ROOT>,
 995                                          <&clk IMX8MQ_CLK_QSPI_ROOT>;
 996                                 clock-names = "qspi_en", "qspi";
 997                                 status = "disabled";
 998                         };
 999
1000                         sdma1: sdma@30bd0000 {
1001                                 compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma";
1002                                 reg = <0x30bd0000 0x10000>;
1003                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1004                                 clocks = <&clk IMX8MQ_CLK_SDMA1_ROOT>,
1005                                          <&clk IMX8MQ_CLK_AHB>;
1006                                 clock-names = "ipg", "ahb";
1007                                 #dma-cells = <3>;
1008                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1009                         };
1010
1011                         fec1: ethernet@30be0000 {
1012                                 compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec";
1013                                 reg = <0x30be0000 0x10000>;
1014                                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1015                                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1016                                              <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1017                                 clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>,
1018                                          <&clk IMX8MQ_CLK_ENET1_ROOT>,
1019                                          <&clk IMX8MQ_CLK_ENET_TIMER>,
1020                                          <&clk IMX8MQ_CLK_ENET_REF>,
1021                                          <&clk IMX8MQ_CLK_ENET_PHY_REF>;
1022                                 clock-names = "ipg", "ahb", "ptp",
1023                                               "enet_clk_ref", "enet_out";
1024                                 fsl,num-tx-queues = <3>;
1025                                 fsl,num-rx-queues = <3>;
1026                                 status = "disabled";
1027                         };
1028                 };
1029
1030                 bus@32c00000 { /* AIPS4 */
1031                         compatible = "fsl,aips-bus", "simple-bus";
1032                         reg = <0x32c00000 0x400000>;
1033                         #address-cells = <1>;
1034                         #size-cells = <1>;
1035                         ranges = <0x32c00000 0x32c00000 0x400000>;
1036
1037                         irqsteer: interrupt-controller@32e2d000 {
1038                                 compatible = "fsl,imx8m-irqsteer", "fsl,imx-irqsteer";
1039                                 reg = <0x32e2d000 0x1000>;
1040                                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1041                                 clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>;
1042                                 clock-names = "ipg";
1043                                 fsl,channel = <0>;
1044                                 fsl,num-irqs = <64>;
1045                                 interrupt-controller;
1046                                 #interrupt-cells = <1>;
1047                         };
1048                 };
1049
1050                 gpu: gpu@38000000 {
1051                         compatible = "vivante,gc";
1052                         reg = <0x38000000 0x40000>;
1053                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1054                         clocks = <&clk IMX8MQ_CLK_GPU_ROOT>,
1055                                  <&clk IMX8MQ_CLK_GPU_SHADER_DIV>,
1056                                  <&clk IMX8MQ_CLK_GPU_AXI>,
1057                                  <&clk IMX8MQ_CLK_GPU_AHB>;
1058                         clock-names = "core", "shader", "bus", "reg";
1059                         #cooling-cells = <2>;
1060                         assigned-clocks = <&clk IMX8MQ_CLK_GPU_CORE_SRC>,
1061                                           <&clk IMX8MQ_CLK_GPU_SHADER_SRC>,
1062                                           <&clk IMX8MQ_CLK_GPU_AXI>,
1063                                           <&clk IMX8MQ_CLK_GPU_AHB>,
1064                                           <&clk IMX8MQ_GPU_PLL_BYPASS>;
1065                         assigned-clock-parents = <&clk IMX8MQ_GPU_PLL_OUT>,
1066                                                  <&clk IMX8MQ_GPU_PLL_OUT>,
1067                                                  <&clk IMX8MQ_GPU_PLL_OUT>,
1068                                                  <&clk IMX8MQ_GPU_PLL_OUT>,
1069                                                  <&clk IMX8MQ_GPU_PLL>;
1070                         assigned-clock-rates = <800000000>, <800000000>,
1071                                                <800000000>, <800000000>, <0>;
1072                         power-domains = <&pgc_gpu>;
1073                 };
1074
1075                 usb_dwc3_0: usb@38100000 {
1076                         compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
1077                         reg = <0x38100000 0x10000>;
1078                         clocks = <&clk IMX8MQ_CLK_USB1_CTRL_ROOT>,
1079                                  <&clk IMX8MQ_CLK_USB_CORE_REF>,
1080                                  <&clk IMX8MQ_CLK_32K>;
1081                         clock-names = "bus_early", "ref", "suspend";
1082                         assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>,
1083                                           <&clk IMX8MQ_CLK_USB_CORE_REF>;
1084                         assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
1085                                                  <&clk IMX8MQ_SYS1_PLL_100M>;
1086                         assigned-clock-rates = <500000000>, <100000000>;
1087                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1088                         phys = <&usb3_phy0>, <&usb3_phy0>;
1089                         phy-names = "usb2-phy", "usb3-phy";
1090                         power-domains = <&pgc_otg1>;
1091                         usb3-resume-missing-cas;
1092                         status = "disabled";
1093                 };
1094
1095                 usb3_phy0: usb-phy@381f0040 {
1096                         compatible = "fsl,imx8mq-usb-phy";
1097                         reg = <0x381f0040 0x40>;
1098                         clocks = <&clk IMX8MQ_CLK_USB1_PHY_ROOT>;
1099                         clock-names = "phy";
1100                         assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>;
1101                         assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
1102                         assigned-clock-rates = <100000000>;
1103                         #phy-cells = <0>;
1104                         status = "disabled";
1105                 };
1106
1107                 usb_dwc3_1: usb@38200000 {
1108                         compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
1109                         reg = <0x38200000 0x10000>;
1110                         clocks = <&clk IMX8MQ_CLK_USB2_CTRL_ROOT>,
1111                                  <&clk IMX8MQ_CLK_USB_CORE_REF>,
1112                                  <&clk IMX8MQ_CLK_32K>;
1113                         clock-names = "bus_early", "ref", "suspend";
1114                         assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>,
1115                                           <&clk IMX8MQ_CLK_USB_CORE_REF>;
1116                         assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
1117                                                  <&clk IMX8MQ_SYS1_PLL_100M>;
1118                         assigned-clock-rates = <500000000>, <100000000>;
1119                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1120                         phys = <&usb3_phy1>, <&usb3_phy1>;
1121                         phy-names = "usb2-phy", "usb3-phy";
1122                         power-domains = <&pgc_otg2>;
1123                         usb3-resume-missing-cas;
1124                         status = "disabled";
1125                 };
1126
1127                 usb3_phy1: usb-phy@382f0040 {
1128                         compatible = "fsl,imx8mq-usb-phy";
1129                         reg = <0x382f0040 0x40>;
1130                         clocks = <&clk IMX8MQ_CLK_USB2_PHY_ROOT>;
1131                         clock-names = "phy";
1132                         assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>;
1133                         assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
1134                         assigned-clock-rates = <100000000>;
1135                         #phy-cells = <0>;
1136                         status = "disabled";
1137                 };
1138
1139                 pcie0: pcie@33800000 {
1140                         compatible = "fsl,imx8mq-pcie";
1141                         reg = <0x33800000 0x400000>,
1142                               <0x1ff00000 0x80000>;
1143                         reg-names = "dbi", "config";
1144                         #address-cells = <3>;
1145                         #size-cells = <2>;
1146                         device_type = "pci";
1147                         bus-range = <0x00 0xff>;
1148                         ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */
1149                                   0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
1150                         num-lanes = <1>;
1151                         num-viewport = <4>;
1152                         interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1153                         interrupt-names = "msi";
1154                         #interrupt-cells = <1>;
1155                         interrupt-map-mask = <0 0 0 0x7>;
1156                         interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1157                                         <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1158                                         <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1159                                         <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1160                         fsl,max-link-speed = <2>;
1161                         power-domains = <&pgc_pcie>;
1162                         resets = <&src IMX8MQ_RESET_PCIEPHY>,
1163                                  <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
1164                                  <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
1165                         reset-names = "pciephy", "apps", "turnoff";
1166                         status = "disabled";
1167                 };
1168
1169                 pcie1: pcie@33c00000 {
1170                         compatible = "fsl,imx8mq-pcie";
1171                         reg = <0x33c00000 0x400000>,
1172                               <0x27f00000 0x80000>;
1173                         reg-names = "dbi", "config";
1174                         #address-cells = <3>;
1175                         #size-cells = <2>;
1176                         device_type = "pci";
1177                         ranges =  <0x81000000 0 0x00000000 0x27f80000 0 0x00010000 /* downstream I/O 64KB */
1178                                    0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */
1179                         num-lanes = <1>;
1180                         num-viewport = <4>;
1181                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1182                         interrupt-names = "msi";
1183                         #interrupt-cells = <1>;
1184                         interrupt-map-mask = <0 0 0 0x7>;
1185                         interrupt-map = <0 0 0 1 &gic GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
1186                                         <0 0 0 2 &gic GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
1187                                         <0 0 0 3 &gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
1188                                         <0 0 0 4 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1189                         fsl,max-link-speed = <2>;
1190                         power-domains = <&pgc_pcie>;
1191                         resets = <&src IMX8MQ_RESET_PCIEPHY2>,
1192                                  <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>,
1193                                  <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>;
1194                         reset-names = "pciephy", "apps", "turnoff";
1195                         status = "disabled";
1196                 };
1197
1198                 gic: interrupt-controller@38800000 {
1199                         compatible = "arm,gic-v3";
1200                         reg = <0x38800000 0x10000>,     /* GIC Dist */
1201                               <0x38880000 0xc0000>,     /* GICR */
1202                               <0x31000000 0x2000>,      /* GICC */
1203                               <0x31010000 0x2000>,      /* GICV */
1204                               <0x31020000 0x2000>;      /* GICH */
1205                         #interrupt-cells = <3>;
1206                         interrupt-controller;
1207                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1208                         interrupt-parent = <&gic>;
1209                 };
1210
1211                 ddrc: memory-controller@3d400000 {
1212                         compatible = "fsl,imx8mq-ddrc", "fsl,imx8m-ddrc";
1213                         reg = <0x3d400000 0x400000>;
1214                         clock-names = "core", "pll", "alt", "apb";
1215                         clocks = <&clk IMX8MQ_CLK_DRAM_CORE>,
1216                                  <&clk IMX8MQ_DRAM_PLL_OUT>,
1217                                  <&clk IMX8MQ_CLK_DRAM_ALT>,
1218                                  <&clk IMX8MQ_CLK_DRAM_APB>;
1219                 };
1220
1221                 ddr-pmu@3d800000 {
1222                         compatible = "fsl,imx8mq-ddr-pmu", "fsl,imx8m-ddr-pmu";
1223                         reg = <0x3d800000 0x400000>;
1224                         interrupt-parent = <&gic>;
1225                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1226                 };
1227         };
1228 };