sys/gnu/dts/arm64/freescale/imx8qxp.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2016 Freescale Semiconductor, Inc.
   4  * Copyright 2017-2018 NXP
   5  *      Dong Aisheng <aisheng.dong@nxp.com>
   6  */
   7
   8 #include <dt-bindings/clock/imx8-clock.h>
   9 #include <dt-bindings/firmware/imx/rsrc.h>
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include <dt-bindings/input/input.h>
  12 #include <dt-bindings/interrupt-controller/arm-gic.h>
  13 #include <dt-bindings/pinctrl/pads-imx8qxp.h>
  14 #include <dt-bindings/thermal/thermal.h>
  15
  16 / {
  17         interrupt-parent = <&gic>;
  18         #address-cells = <2>;
  19         #size-cells = <2>;
  20
  21         aliases {
  22                 gpio0 = &lsio_gpio0;
  23                 gpio1 = &lsio_gpio1;
  24                 gpio2 = &lsio_gpio2;
  25                 gpio3 = &lsio_gpio3;
  26                 gpio4 = &lsio_gpio4;
  27                 gpio5 = &lsio_gpio5;
  28                 gpio6 = &lsio_gpio6;
  29                 gpio7 = &lsio_gpio7;
  30                 mmc0 = &usdhc1;
  31                 mmc1 = &usdhc2;
  32                 mmc2 = &usdhc3;
  33                 mu1 = &lsio_mu1;
  34                 serial0 = &adma_lpuart0;
  35                 serial1 = &adma_lpuart1;
  36                 serial2 = &adma_lpuart2;
  37                 serial3 = &adma_lpuart3;
  38         };
  39
  40         cpus {
  41                 #address-cells = <2>;
  42                 #size-cells = <0>;
  43
  44                 /* We have 1 clusters with 4 Cortex-A35 cores */
  45                 A35_0: cpu@0 {
  46                         device_type = "cpu";
  47                         compatible = "arm,cortex-a35";
  48                         reg = <0x0 0x0>;
  49                         enable-method = "psci";
  50                         next-level-cache = <&A35_L2>;
  51                         clocks = <&clk IMX_A35_CLK>;
  52                         operating-points-v2 = <&a35_opp_table>;
  53                         #cooling-cells = <2>;
  54                 };
  55
  56                 A35_1: cpu@1 {
  57                         device_type = "cpu";
  58                         compatible = "arm,cortex-a35";
  59                         reg = <0x0 0x1>;
  60                         enable-method = "psci";
  61                         next-level-cache = <&A35_L2>;
  62                         clocks = <&clk IMX_A35_CLK>;
  63                         operating-points-v2 = <&a35_opp_table>;
  64                         #cooling-cells = <2>;
  65                 };
  66
  67                 A35_2: cpu@2 {
  68                         device_type = "cpu";
  69                         compatible = "arm,cortex-a35";
  70                         reg = <0x0 0x2>;
  71                         enable-method = "psci";
  72                         next-level-cache = <&A35_L2>;
  73                         clocks = <&clk IMX_A35_CLK>;
  74                         operating-points-v2 = <&a35_opp_table>;
  75                         #cooling-cells = <2>;
  76                 };
  77
  78                 A35_3: cpu@3 {
  79                         device_type = "cpu";
  80                         compatible = "arm,cortex-a35";
  81                         reg = <0x0 0x3>;
  82                         enable-method = "psci";
  83                         next-level-cache = <&A35_L2>;
  84                         clocks = <&clk IMX_A35_CLK>;
  85                         operating-points-v2 = <&a35_opp_table>;
  86                         #cooling-cells = <2>;
  87                 };
  88
  89                 A35_L2: l2-cache0 {
  90                         compatible = "cache";
  91                 };
  92         };
  93
  94         a35_opp_table: opp-table {
  95                 compatible = "operating-points-v2";
  96                 opp-shared;
  97
  98                 opp-900000000 {
  99                         opp-hz = /bits/ 64 <900000000>;
 100                         opp-microvolt = <1000000>;
 101                         clock-latency-ns = <150000>;
 102                 };
 103
 104                 opp-1200000000 {
 105                         opp-hz = /bits/ 64 <1200000000>;
 106                         opp-microvolt = <1100000>;
 107                         clock-latency-ns = <150000>;
 108                         opp-suspend;
 109                 };
 110         };
 111
 112         gic: interrupt-controller@51a00000 {
 113                 compatible = "arm,gic-v3";
 114                 reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
 115                       <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */
 116                 #interrupt-cells = <3>;
 117                 interrupt-controller;
 118                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 119         };
 120
 121         reserved-memory {
 122                 #address-cells = <2>;
 123                 #size-cells = <2>;
 124                 ranges;
 125
 126                 dsp_reserved: dsp@92400000 {
 127                         reg = <0 0x92400000 0 0x2000000>;
 128                         no-map;
 129                 };
 130         };
 131
 132         pmu {
 133                 compatible = "arm,armv8-pmuv3";
 134                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
 135         };
 136
 137         psci {
 138                 compatible = "arm,psci-1.0";
 139                 method = "smc";
 140         };
 141
 142         scu {
 143                 compatible = "fsl,imx-scu";
 144                 mbox-names = "tx0",
 145                              "rx0",
 146                              "gip3";
 147                 mboxes = <&lsio_mu1 0 0
 148                           &lsio_mu1 1 0
 149                           &lsio_mu1 3 3>;
 150
 151                 clk: clock-controller {
 152                         compatible = "fsl,imx8qxp-clk";
 153                         #clock-cells = <1>;
 154                         clocks = <&xtal32k &xtal24m>;
 155                         clock-names = "xtal_32KHz", "xtal_24Mhz";
 156                 };
 157
 158                 iomuxc: pinctrl {
 159                         compatible = "fsl,imx8qxp-iomuxc";
 160                 };
 161
 162                 ocotp: imx8qx-ocotp {
 163                         compatible = "fsl,imx8qxp-scu-ocotp";
 164                         #address-cells = <1>;
 165                         #size-cells = <1>;
 166                 };
 167
 168                 pd: imx8qx-pd {
 169                         compatible = "fsl,imx8qxp-scu-pd";
 170                         #power-domain-cells = <1>;
 171                 };
 172
 173                 scu_key: scu-key {
 174                         compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key";
 175                         linux,keycodes = <KEY_POWER>;
 176                         status = "disabled";
 177                 };
 178
 179                 rtc: rtc {
 180                         compatible = "fsl,imx8qxp-sc-rtc";
 181                 };
 182
 183                 watchdog {
 184                         compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt";
 185                         timeout-sec = <60>;
 186                 };
 187
 188                 tsens: thermal-sensor {
 189                         compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal";
 190                         #thermal-sensor-cells = <1>;
 191                 };
 192         };
 193
 194         timer {
 195                 compatible = "arm,armv8-timer";
 196                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
 197                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
 198                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
 199                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
 200         };
 201
 202         xtal32k: clock-xtal32k {
 203                 compatible = "fixed-clock";
 204                 #clock-cells = <0>;
 205                 clock-frequency = <32768>;
 206                 clock-output-names = "xtal_32KHz";
 207         };
 208
 209         xtal24m: clock-xtal24m {
 210                 compatible = "fixed-clock";
 211                 #clock-cells = <0>;
 212                 clock-frequency = <24000000>;
 213                 clock-output-names = "xtal_24MHz";
 214         };
 215
 216         adma_subsys: bus@59000000 {
 217                 compatible = "simple-bus";
 218                 #address-cells = <1>;
 219                 #size-cells = <1>;
 220                 ranges = <0x59000000 0x0 0x59000000 0x2000000>;
 221
 222                 adma_lpcg: clock-controller@59000000 {
 223                         compatible = "fsl,imx8qxp-lpcg-adma";
 224                         reg = <0x59000000 0x2000000>;
 225                         #clock-cells = <1>;
 226                 };
 227
 228                 adma_dsp: dsp@596e8000 {
 229                         compatible = "fsl,imx8qxp-dsp";
 230                         reg = <0x596e8000 0x88000>;
 231                         clocks = <&adma_lpcg IMX_ADMA_LPCG_DSP_IPG_CLK>,
 232                                 <&adma_lpcg IMX_ADMA_LPCG_OCRAM_IPG_CLK>,
 233                                 <&adma_lpcg IMX_ADMA_LPCG_DSP_CORE_CLK>;
 234                         clock-names = "ipg", "ocram", "core";
 235                         power-domains = <&pd IMX_SC_R_MU_13A>,
 236                                 <&pd IMX_SC_R_MU_13B>,
 237                                 <&pd IMX_SC_R_DSP>,
 238                                 <&pd IMX_SC_R_DSP_RAM>;
 239                         mbox-names = "txdb0", "txdb1",
 240                                 "rxdb0", "rxdb1";
 241                         mboxes = <&lsio_mu13 2 0>,
 242                                 <&lsio_mu13 2 1>,
 243                                 <&lsio_mu13 3 0>,
 244                                 <&lsio_mu13 3 1>;
 245                         memory-region = <&dsp_reserved>;
 246                         status = "disabled";
 247                 };
 248
 249                 adma_lpuart0: serial@5a060000 {
 250                         compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
 251                         reg = <0x5a060000 0x1000>;
 252                         interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
 253                         clocks = <&adma_lpcg IMX_ADMA_LPCG_UART0_IPG_CLK>,
 254                                  <&adma_lpcg IMX_ADMA_LPCG_UART0_BAUD_CLK>;
 255                         clock-names = "ipg", "baud";
 256                         power-domains = <&pd IMX_SC_R_UART_0>;
 257                         status = "disabled";
 258                 };
 259
 260                 adma_lpuart1: serial@5a070000 {
 261                         compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
 262                         reg = <0x5a070000 0x1000>;
 263                         interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
 264                         clocks = <&adma_lpcg IMX_ADMA_LPCG_UART1_IPG_CLK>,
 265                                  <&adma_lpcg IMX_ADMA_LPCG_UART1_BAUD_CLK>;
 266                         clock-names = "ipg", "baud";
 267                         power-domains = <&pd IMX_SC_R_UART_1>;
 268                         status = "disabled";
 269                 };
 270
 271                 adma_lpuart2: serial@5a080000 {
 272                         compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
 273                         reg = <0x5a080000 0x1000>;
 274                         interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
 275                         clocks = <&adma_lpcg IMX_ADMA_LPCG_UART2_IPG_CLK>,
 276                                  <&adma_lpcg IMX_ADMA_LPCG_UART2_BAUD_CLK>;
 277                         clock-names = "ipg", "baud";
 278                         power-domains = <&pd IMX_SC_R_UART_2>;
 279                         status = "disabled";
 280                 };
 281
 282                 adma_lpuart3: serial@5a090000 {
 283                         compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
 284                         reg = <0x5a090000 0x1000>;
 285                         interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
 286                         clocks = <&adma_lpcg IMX_ADMA_LPCG_UART3_IPG_CLK>,
 287                                  <&adma_lpcg IMX_ADMA_LPCG_UART3_BAUD_CLK>;
 288                         clock-names = "ipg", "baud";
 289                         power-domains = <&pd IMX_SC_R_UART_3>;
 290                         status = "disabled";
 291                 };
 292
 293                 adma_i2c0: i2c@5a800000 {
 294                         compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
 295                         reg = <0x5a800000 0x4000>;
 296                         interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
 297                         clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C0_CLK>;
 298                         clock-names = "per";
 299                         assigned-clocks = <&clk IMX_ADMA_I2C0_CLK>;
 300                         assigned-clock-rates = <24000000>;
 301                         power-domains = <&pd IMX_SC_R_I2C_0>;
 302                         status = "disabled";
 303                 };
 304
 305                 adma_i2c1: i2c@5a810000 {
 306                         compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
 307                         reg = <0x5a810000 0x4000>;
 308                         interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
 309                         clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C1_CLK>;
 310                         clock-names = "per";
 311                         assigned-clocks = <&clk IMX_ADMA_I2C1_CLK>;
 312                         assigned-clock-rates = <24000000>;
 313                         power-domains = <&pd IMX_SC_R_I2C_1>;
 314                         status = "disabled";
 315                 };
 316
 317                 adma_i2c2: i2c@5a820000 {
 318                         compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
 319                         reg = <0x5a820000 0x4000>;
 320                         interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
 321                         clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C2_CLK>;
 322                         clock-names = "per";
 323                         assigned-clocks = <&clk IMX_ADMA_I2C2_CLK>;
 324                         assigned-clock-rates = <24000000>;
 325                         power-domains = <&pd IMX_SC_R_I2C_2>;
 326                         status = "disabled";
 327                 };
 328
 329                 adma_i2c3: i2c@5a830000 {
 330                         compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
 331                         reg = <0x5a830000 0x4000>;
 332                         interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
 333                         clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C3_CLK>;
 334                         clock-names = "per";
 335                         assigned-clocks = <&clk IMX_ADMA_I2C3_CLK>;
 336                         assigned-clock-rates = <24000000>;
 337                         power-domains = <&pd IMX_SC_R_I2C_3>;
 338                         status = "disabled";
 339                 };
 340         };
 341
 342         conn_subsys: bus@5b000000 {
 343                 compatible = "simple-bus";
 344                 #address-cells = <1>;
 345                 #size-cells = <1>;
 346                 ranges = <0x5b000000 0x0 0x5b000000 0x1000000>;
 347
 348                 conn_lpcg: clock-controller@5b200000 {
 349                         compatible = "fsl,imx8qxp-lpcg-conn";
 350                         reg = <0x5b200000 0xb0000>;
 351                         #clock-cells = <1>;
 352                 };
 353
 354                 usdhc1: mmc@5b010000 {
 355                         compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
 356                         interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
 357                         reg = <0x5b010000 0x10000>;
 358                         clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC0_IPG_CLK>,
 359                                  <&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>,
 360                                  <&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>;
 361                         clock-names = "ipg", "per", "ahb";
 362                         power-domains = <&pd IMX_SC_R_SDHC_0>;
 363                         status = "disabled";
 364                 };
 365
 366                 usdhc2: mmc@5b020000 {
 367                         compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
 368                         interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
 369                         reg = <0x5b020000 0x10000>;
 370                         clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC1_IPG_CLK>,
 371                                  <&conn_lpcg IMX_CONN_LPCG_SDHC1_PER_CLK>,
 372                                  <&conn_lpcg IMX_CONN_LPCG_SDHC1_HCLK>;
 373                         clock-names = "ipg", "per", "ahb";
 374                         power-domains = <&pd IMX_SC_R_SDHC_1>;
 375                         fsl,tuning-start-tap = <20>;
 376                         fsl,tuning-step= <2>;
 377                         status = "disabled";
 378                 };
 379
 380                 usdhc3: mmc@5b030000 {
 381                         compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
 382                         interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
 383                         reg = <0x5b030000 0x10000>;
 384                         clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC2_IPG_CLK>,
 385                                  <&conn_lpcg IMX_CONN_LPCG_SDHC2_PER_CLK>,
 386                                  <&conn_lpcg IMX_CONN_LPCG_SDHC2_HCLK>;
 387                         clock-names = "ipg", "per", "ahb";
 388                         power-domains = <&pd IMX_SC_R_SDHC_2>;
 389                         status = "disabled";
 390                 };
 391
 392                 fec1: ethernet@5b040000 {
 393                         compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec";
 394                         reg = <0x5b040000 0x10000>;
 395                         interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
 396                                      <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
 397                                      <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
 398                                      <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
 399                         clocks = <&conn_lpcg IMX_CONN_LPCG_ENET0_IPG_CLK>,
 400                                  <&conn_lpcg IMX_CONN_LPCG_ENET0_AHB_CLK>,
 401                                  <&conn_lpcg IMX_CONN_LPCG_ENET0_TX_CLK>,
 402                                  <&conn_lpcg IMX_CONN_LPCG_ENET0_ROOT_CLK>;
 403                         clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
 404                         fsl,num-tx-queues=<3>;
 405                         fsl,num-rx-queues=<3>;
 406                         power-domains = <&pd IMX_SC_R_ENET_0>;
 407                         status = "disabled";
 408                 };
 409
 410                 fec2: ethernet@5b050000 {
 411                         compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec";
 412                         reg = <0x5b050000 0x10000>;
 413                         interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
 414                                         <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
 415                                         <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
 416                                         <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
 417                         clocks = <&conn_lpcg IMX_CONN_LPCG_ENET1_IPG_CLK>,
 418                                  <&conn_lpcg IMX_CONN_LPCG_ENET1_AHB_CLK>,
 419                                  <&conn_lpcg IMX_CONN_LPCG_ENET1_TX_CLK>,
 420                                  <&conn_lpcg IMX_CONN_LPCG_ENET1_ROOT_CLK>;
 421                         clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
 422                         fsl,num-tx-queues=<3>;
 423                         fsl,num-rx-queues=<3>;
 424                         power-domains = <&pd IMX_SC_R_ENET_1>;
 425                         status = "disabled";
 426                 };
 427         };
 428
 429         ddr_subsyss: bus@5c000000 {
 430                 compatible = "simple-bus";
 431                 #address-cells = <1>;
 432                 #size-cells = <1>;
 433                 ranges = <0x5c000000 0x0 0x5c000000 0x1000000>;
 434
 435                 ddr-pmu@5c020000 {
 436                         compatible = "fsl,imx8-ddr-pmu";
 437                         reg = <0x5c020000 0x10000>;
 438                         interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
 439                 };
 440         };
 441
 442         lsio_subsys: bus@5d000000 {
 443                 compatible = "simple-bus";
 444                 #address-cells = <1>;
 445                 #size-cells = <1>;
 446                 ranges = <0x5d000000 0x0 0x5d000000 0x1000000>;
 447
 448                 lsio_gpio0: gpio@5d080000 {
 449                         compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
 450                         reg = <0x5d080000 0x10000>;
 451                         interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
 452                         gpio-controller;
 453                         #gpio-cells = <2>;
 454                         interrupt-controller;
 455                         #interrupt-cells = <2>;
 456                         power-domains = <&pd IMX_SC_R_GPIO_0>;
 457                 };
 458
 459                 lsio_gpio1: gpio@5d090000 {
 460                         compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
 461                         reg = <0x5d090000 0x10000>;
 462                         interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
 463                         gpio-controller;
 464                         #gpio-cells = <2>;
 465                         interrupt-controller;
 466                         #interrupt-cells = <2>;
 467                         power-domains = <&pd IMX_SC_R_GPIO_1>;
 468                 };
 469
 470                 lsio_gpio2: gpio@5d0a0000 {
 471                         compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
 472                         reg = <0x5d0a0000 0x10000>;
 473                         interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
 474                         gpio-controller;
 475                         #gpio-cells = <2>;
 476                         interrupt-controller;
 477                         #interrupt-cells = <2>;
 478                         power-domains = <&pd IMX_SC_R_GPIO_2>;
 479                 };
 480
 481                 lsio_gpio3: gpio@5d0b0000 {
 482                         compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
 483                         reg = <0x5d0b0000 0x10000>;
 484                         interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
 485                         gpio-controller;
 486                         #gpio-cells = <2>;
 487                         interrupt-controller;
 488                         #interrupt-cells = <2>;
 489                         power-domains = <&pd IMX_SC_R_GPIO_3>;
 490                 };
 491
 492                 lsio_gpio4: gpio@5d0c0000 {
 493                         compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
 494                         reg = <0x5d0c0000 0x10000>;
 495                         interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
 496                         gpio-controller;
 497                         #gpio-cells = <2>;
 498                         interrupt-controller;
 499                         #interrupt-cells = <2>;
 500                         power-domains = <&pd IMX_SC_R_GPIO_4>;
 501                 };
 502
 503                 lsio_gpio5: gpio@5d0d0000 {
 504                         compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
 505                         reg = <0x5d0d0000 0x10000>;
 506                         interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
 507                         gpio-controller;
 508                         #gpio-cells = <2>;
 509                         interrupt-controller;
 510                         #interrupt-cells = <2>;
 511                         power-domains = <&pd IMX_SC_R_GPIO_5>;
 512                 };
 513
 514                 lsio_gpio6: gpio@5d0e0000 {
 515                         compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
 516                         reg = <0x5d0e0000 0x10000>;
 517                         interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
 518                         gpio-controller;
 519                         #gpio-cells = <2>;
 520                         interrupt-controller;
 521                         #interrupt-cells = <2>;
 522                         power-domains = <&pd IMX_SC_R_GPIO_6>;
 523                 };
 524
 525                 lsio_gpio7: gpio@5d0f0000 {
 526                         compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio";
 527                         reg = <0x5d0f0000 0x10000>;
 528                         interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 529                         gpio-controller;
 530                         #gpio-cells = <2>;
 531                         interrupt-controller;
 532                         #interrupt-cells = <2>;
 533                         power-domains = <&pd IMX_SC_R_GPIO_7>;
 534                 };
 535
 536                 lsio_mu0: mailbox@5d1b0000 {
 537                         compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
 538                         reg = <0x5d1b0000 0x10000>;
 539                         interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
 540                         #mbox-cells = <2>;
 541                         status = "disabled";
 542                 };
 543
 544                 lsio_mu1: mailbox@5d1c0000 {
 545                         compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
 546                         reg = <0x5d1c0000 0x10000>;
 547                         interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
 548                         #mbox-cells = <2>;
 549                 };
 550
 551                 lsio_mu2: mailbox@5d1d0000 {
 552                         compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
 553                         reg = <0x5d1d0000 0x10000>;
 554                         interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
 555                         #mbox-cells = <2>;
 556                         status = "disabled";
 557                 };
 558
 559                 lsio_mu3: mailbox@5d1e0000 {
 560                         compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
 561                         reg = <0x5d1e0000 0x10000>;
 562                         interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
 563                         #mbox-cells = <2>;
 564                         status = "disabled";
 565                 };
 566
 567                 lsio_mu4: mailbox@5d1f0000 {
 568                         compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
 569                         reg = <0x5d1f0000 0x10000>;
 570                         interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
 571                         #mbox-cells = <2>;
 572                         status = "disabled";
 573                 };
 574
 575                 lsio_mu13: mailbox@5d280000 {
 576                         compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
 577                         reg = <0x5d280000 0x10000>;
 578                         interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
 579                         #mbox-cells = <2>;
 580                         power-domains = <&pd IMX_SC_R_MU_13A>;
 581                 };
 582
 583                 lsio_lpcg: clock-controller@5d400000 {
 584                         compatible = "fsl,imx8qxp-lpcg-lsio";
 585                         reg = <0x5d400000 0x400000>;
 586                         #clock-cells = <1>;
 587                 };
 588         };
 589
 590         thermal_zones: thermal-zones {
 591                 cpu-thermal0 {
 592                         polling-delay-passive = <250>;
 593                         polling-delay = <2000>;
 594                         thermal-sensors = <&tsens IMX_SC_R_SYSTEM>;
 595
 596                         trips {
 597                                 cpu_alert0: trip0 {
 598                                         temperature = <107000>;
 599                                         hysteresis = <2000>;
 600                                         type = "passive";
 601                                 };
 602
 603                                 cpu_crit0: trip1 {
 604                                         temperature = <127000>;
 605                                         hysteresis = <2000>;
 606                                         type = "critical";
 607                                 };
 608                         };
 609
 610                         cooling-maps {
 611                                 map0 {
 612                                         trip = <&cpu_alert0>;
 613                                         cooling-device =
 614                                                 <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 615                                                 <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 616                                                 <&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 617                                                 <&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 618                                 };
 619                         };
 620                 };
 621         };
 622 };