1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019, Intel Corporation
5 #include "socfpga_agilex.dtsi"
8 model = "SoCFPGA Agilex SoCDK";
18 stdout-path = "serial0:115200n8";
22 compatible = "gpio-leds";
25 gpios = <&portb 20 GPIO_ACTIVE_HIGH>;
30 gpios = <&portb 19 GPIO_ACTIVE_HIGH>;
35 gpios = <&portb 21 GPIO_ACTIVE_HIGH>;
40 device_type = "memory";
41 /* We expect the bootloader to fill in the reg */
55 max-frame-size = <9000>;
60 compatible = "snps,dwmac-mdio";
61 phy0: ethernet-phy@0 {
64 txd0-skew-ps = <0>; /* -420ps */
65 txd1-skew-ps = <0>; /* -420ps */
66 txd2-skew-ps = <0>; /* -420ps */
67 txd3-skew-ps = <0>; /* -420ps */
68 rxd0-skew-ps = <420>; /* 0ps */
69 rxd1-skew-ps = <420>; /* 0ps */
70 rxd2-skew-ps = <420>; /* 0ps */
71 rxd3-skew-ps = <420>; /* 0ps */
72 txen-skew-ps = <0>; /* -420ps */
73 txc-skew-ps = <900>; /* 0ps */
74 rxdv-skew-ps = <420>; /* 0ps */
75 rxc-skew-ps = <1680>; /* 780ps */
103 #address-cells = <1>;
105 compatible = "mt25qu02g";
107 spi-max-frequency = <100000000>;
110 cdns,page-size = <256>;
111 cdns,block-size = <16>;
112 cdns,read-delay = <1>;
113 cdns,tshsl-ns = <50>;
114 cdns,tsd2d-ns = <50>;
119 compatible = "fixed-partitions";
120 #address-cells = <1>;
123 qspi_boot: partition@0 {
124 label = "Boot and fpga data";
125 reg = <0x0 0x03FE0000>;
128 qspi_rootfs: partition@3FE0000 {
129 label = "Root Filesystem - JFFS2";
130 reg = <0x03FE0000 0x0C020000>;