1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree file for Globalscale Marvell ESPRESSOBin Board
4 * Copyright (C) 2016 Marvell
6 * Romain Perier <romain.perier@free-electrons.com>
10 * Schematic available at http://espressobin.net/wp-content/uploads/2017/08/ESPRESSObin_V5_Schematics.pdf
15 #include <dt-bindings/gpio/gpio.h>
16 #include "armada-372x.dtsi"
19 model = "Globalscale Marvell ESPRESSOBin Board";
20 compatible = "globalscale,espressobin", "marvell,armada3720", "marvell,armada3710";
23 stdout-path = "serial0:115200n8";
27 device_type = "memory";
28 reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
31 vcc_sd_reg1: regulator {
32 compatible = "regulator-gpio";
33 regulator-name = "vcc_sd1";
34 regulator-min-microvolt = <1800000>;
35 regulator-max-microvolt = <3300000>;
38 gpios = <&gpionb 4 GPIO_ACTIVE_HIGH>;
50 pinctrl-names = "default";
51 pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
58 phy-names = "sata-phy";
65 cd-gpios = <&gpionb 3 GPIO_ACTIVE_LOW>;
66 marvell,pad-type = "sd";
67 vqmmc-supply = <&vcc_sd_reg1>;
69 pinctrl-names = "default";
70 pinctrl-0 = <&sdio_pins>;
81 marvell,xenon-tun-count = <9>;
82 marvell,pad-type = "fixed-1-8v";
84 pinctrl-names = "default";
85 pinctrl-0 = <&mmc_pins>;
87 * This eMMC is not populated on all boards, so disable it by
88 * default and let the bootloader enable it, if it is present
98 compatible = "jedec,spi-nor";
99 spi-max-frequency = <104000000>;
104 /* Exported on the micro USB connector J5 through an FTDI */
106 pinctrl-names = "default";
107 pinctrl-0 = <&uart1_pins>;
112 * Connector J17 and J18 expose a number of different features. Some pins are
113 * multiplexed. This is the case for instance for the following features:
114 * - UART1 (pin 24 = RX, pin 26 = TX). See armada-3720-db.dts for an example of
115 * how to enable it. Beware that the signals are 1.8V TTL.
133 compatible = "marvell,mv88e6085";
134 #address-cells = <1>;
141 #address-cells = <1>;
148 phy-mode = "rgmii-id";
158 phy-handle = <&switch0phy0>;
164 phy-handle = <&switch0phy1>;
170 phy-handle = <&switch0phy2>;
176 #address-cells = <1>;
179 switch0phy0: switch0phy0@11 {
182 switch0phy1: switch0phy1@12 {
185 switch0phy2: switch0phy2@13 {
193 pinctrl-names = "default";
194 pinctrl-0 = <&rgmii_pins>, <&smi_pins>;
195 phy-mode = "rgmii-id";