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MFV r353637: 10844 Serialize ZTHR operations to eliminate races
[FreeBSD/FreeBSD.git] / sys / gnu / dts / arm64 / marvell / armada-3720-espressobin.dts
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3  * Device Tree file for Globalscale Marvell ESPRESSOBin Board
4  * Copyright (C) 2016 Marvell
5  *
6  * Romain Perier <romain.perier@free-electrons.com>
7  *
8  */
9 /*
10  * Schematic available at http://espressobin.net/wp-content/uploads/2017/08/ESPRESSObin_V5_Schematics.pdf
11  */
12
13 /dts-v1/;
14
15 #include <dt-bindings/gpio/gpio.h>
16 #include "armada-372x.dtsi"
17
18 / {
19         model = "Globalscale Marvell ESPRESSOBin Board";
20         compatible = "globalscale,espressobin", "marvell,armada3720", "marvell,armada3710";
21
22         chosen {
23                 stdout-path = "serial0:115200n8";
24         };
25
26         memory@0 {
27                 device_type = "memory";
28                 reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
29         };
30
31         vcc_sd_reg1: regulator {
32                 compatible = "regulator-gpio";
33                 regulator-name = "vcc_sd1";
34                 regulator-min-microvolt = <1800000>;
35                 regulator-max-microvolt = <3300000>;
36                 regulator-boot-on;
37
38                 gpios = <&gpionb 4 GPIO_ACTIVE_HIGH>;
39                 gpios-states = <0>;
40                 states = <1800000 0x1
41                           3300000 0x0>;
42                 enable-active-high;
43         };
44 };
45
46 /* J9 */
47 &pcie0 {
48         status = "okay";
49         phys = <&comphy1 0>;
50         pinctrl-names = "default";
51         pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
52 };
53
54 /* J6 */
55 &sata {
56         status = "okay";
57         phys = <&comphy2 0>;
58         phy-names = "sata-phy";
59 };
60
61 /* J1 */
62 &sdhci1 {
63         wp-inverted;
64         bus-width = <4>;
65         cd-gpios = <&gpionb 3 GPIO_ACTIVE_LOW>;
66         marvell,pad-type = "sd";
67         vqmmc-supply = <&vcc_sd_reg1>;
68
69         pinctrl-names = "default";
70         pinctrl-0 = <&sdio_pins>;
71         status = "okay";
72 };
73
74 /* U11 */
75 &sdhci0 {
76         non-removable;
77         bus-width = <8>;
78         mmc-ddr-1_8v;
79         mmc-hs400-1_8v;
80         marvell,xenon-emmc;
81         marvell,xenon-tun-count = <9>;
82         marvell,pad-type = "fixed-1-8v";
83
84         pinctrl-names = "default";
85         pinctrl-0 = <&mmc_pins>;
86 /*
87  * This eMMC is not populated on all boards, so disable it by
88  * default and let the bootloader enable it, if it is present
89  */
90         status = "disabled";
91 };
92
93 &spi0 {
94         status = "okay";
95
96         flash@0 {
97                 reg = <0>;
98                 compatible = "jedec,spi-nor";
99                 spi-max-frequency = <104000000>;
100                 m25p,fast-read;
101         };
102 };
103
104 /* Exported on the micro USB connector J5 through an FTDI */
105 &uart0 {
106         pinctrl-names = "default";
107         pinctrl-0 = <&uart1_pins>;
108         status = "okay";
109 };
110
111 /*
112  * Connector J17 and J18 expose a number of different features. Some pins are
113  * multiplexed. This is the case for instance for the following features:
114  * - UART1 (pin 24 = RX, pin 26 = TX). See armada-3720-db.dts for an example of
115  *   how to enable it. Beware that the signals are 1.8V TTL.
116  * - I2C
117  * - SPI
118  * - MMC
119  */
120
121 /* J7 */
122 &usb3 {
123         status = "okay";
124 };
125
126 /* J8 */
127 &usb2 {
128         status = "okay";
129 };
130
131 &mdio {
132         switch0: switch0@1 {
133                 compatible = "marvell,mv88e6085";
134                 #address-cells = <1>;
135                 #size-cells = <0>;
136                 reg = <1>;
137
138                 dsa,member = <0 0>;
139
140                 ports {
141                         #address-cells = <1>;
142                         #size-cells = <0>;
143
144                         port@0 {
145                                 reg = <0>;
146                                 label = "cpu";
147                                 ethernet = <&eth0>;
148                                 phy-mode = "rgmii-id";
149                                 fixed-link {
150                                         speed = <1000>;
151                                         full-duplex;
152                                 };
153                         };
154
155                         port@1 {
156                                 reg = <1>;
157                                 label = "wan";
158                                 phy-handle = <&switch0phy0>;
159                         };
160
161                         port@2 {
162                                 reg = <2>;
163                                 label = "lan0";
164                                 phy-handle = <&switch0phy1>;
165                         };
166
167                         port@3 {
168                                 reg = <3>;
169                                 label = "lan1";
170                                 phy-handle = <&switch0phy2>;
171                         };
172
173                 };
174
175                 mdio {
176                         #address-cells = <1>;
177                         #size-cells = <0>;
178
179                         switch0phy0: switch0phy0@11 {
180                                 reg = <0x11>;
181                         };
182                         switch0phy1: switch0phy1@12 {
183                                 reg = <0x12>;
184                         };
185                         switch0phy2: switch0phy2@13 {
186                                 reg = <0x13>;
187                         };
188                 };
189         };
190 };
191
192 &eth0 {
193         pinctrl-names = "default";
194         pinctrl-0 = <&rgmii_pins>, <&smi_pins>;
195         phy-mode = "rgmii-id";
196         status = "okay";
197
198         fixed-link {
199                 speed = <1000>;
200                 full-duplex;
201         };
202 };