1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Marvell Armada 37xx family of SoCs.
5 * Copyright (C) 2016 Marvell
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 model = "Marvell Armada 37xx SoC";
15 compatible = "marvell,armada3700";
16 interrupt-parent = <&gic>;
31 * The PSCI firmware region depicted below is the default one
32 * and should be updated by the bootloader.
35 reg = <0 0x4000000 0 0x200000>;
45 compatible = "arm,cortex-a53", "arm,armv8";
47 clocks = <&nb_periph_clk 16>;
48 enable-method = "psci";
53 compatible = "arm,psci-0.2";
58 compatible = "arm,armv8-timer";
59 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
60 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
61 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
62 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
66 compatible = "arm,armv8-pmuv3";
67 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
71 compatible = "simple-bus";
76 internal-regs@d0000000 {
79 compatible = "simple-bus";
80 /* 32M internal register @ 0xd000_0000 */
81 ranges = <0x0 0x0 0xd0000000 0x2000000>;
84 compatible = "marvell,armada-3700-spi";
87 reg = <0x10600 0xA00>;
88 clocks = <&nb_periph_clk 7>;
89 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
95 compatible = "marvell,armada-3700-i2c";
99 clocks = <&nb_periph_clk 10>;
100 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
106 compatible = "marvell,armada-3700-i2c";
107 reg = <0x11080 0x24>;
108 #address-cells = <1>;
110 clocks = <&nb_periph_clk 9>;
111 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
117 compatible = "marvell,armada-3700-avs",
119 reg = <0x11500 0x40>;
122 uart0: serial@12000 {
123 compatible = "marvell,armada-3700-uart";
124 reg = <0x12000 0x200>;
127 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
128 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
129 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
130 interrupt-names = "uart-sum", "uart-tx", "uart-rx";
134 uart1: serial@12200 {
135 compatible = "marvell,armada-3700-uart-ext";
136 reg = <0x12200 0x30>;
139 <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
140 <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>;
141 interrupt-names = "uart-tx", "uart-rx";
145 nb_periph_clk: nb-periph-clk@13000 {
146 compatible = "marvell,armada-3700-periph-clock-nb";
147 reg = <0x13000 0x100>;
148 clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
149 <&tbg 3>, <&xtalclk>;
153 sb_periph_clk: sb-periph-clk@18000 {
154 compatible = "marvell,armada-3700-periph-clock-sb";
155 reg = <0x18000 0x100>;
156 clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
157 <&tbg 3>, <&xtalclk>;
162 compatible = "marvell,armada-3700-tbg-clock";
163 reg = <0x13200 0x100>;
168 pinctrl_nb: pinctrl@13800 {
169 compatible = "marvell,armada3710-nb-pinctrl",
170 "syscon", "simple-mfd";
171 reg = <0x13800 0x100>, <0x13C00 0x20>;
175 gpio-ranges = <&pinctrl_nb 0 0 36>;
177 interrupt-controller;
178 #interrupt-cells = <2>;
180 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
181 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
182 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
183 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
184 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
185 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
186 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
187 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
188 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
189 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
190 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
191 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
195 compatible = "marvell,armada-3700-xtal-clock";
196 clock-output-names = "xtal";
200 spi_quad_pins: spi-quad-pins {
205 i2c1_pins: i2c1-pins {
210 i2c2_pins: i2c2-pins {
215 uart1_pins: uart1-pins {
220 uart2_pins: uart2-pins {
226 nb_pm: syscon@14000 {
227 compatible = "marvell,armada-3700-nb-pm",
229 reg = <0x14000 0x60>;
232 pinctrl_sb: pinctrl@18800 {
233 compatible = "marvell,armada3710-sb-pinctrl",
234 "syscon", "simple-mfd";
235 reg = <0x18800 0x100>, <0x18C00 0x20>;
239 gpio-ranges = <&pinctrl_sb 0 0 30>;
241 interrupt-controller;
242 #interrupt-cells = <2>;
244 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
245 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
246 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
247 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
248 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
251 rgmii_pins: mii-pins {
258 eth0: ethernet@30000 {
259 compatible = "marvell,armada-3700-neta";
260 reg = <0x30000 0x4000>;
261 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
262 clocks = <&sb_periph_clk 8>;
267 #address-cells = <1>;
269 compatible = "marvell,orion-mdio";
273 eth1: ethernet@40000 {
274 compatible = "marvell,armada-3700-neta";
275 reg = <0x40000 0x4000>;
276 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
277 clocks = <&sb_periph_clk 7>;
282 compatible = "marvell,armada3700-xhci",
284 reg = <0x58000 0x4000>;
285 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
286 clocks = <&sb_periph_clk 12>;
291 compatible = "marvell,armada-3700-ehci";
292 reg = <0x5e000 0x2000>;
293 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
298 compatible = "marvell,armada-3700-xor";
299 reg = <0x60900 0x100>,
303 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
306 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
310 crypto: crypto@90000 {
311 compatible = "inside-secure,safexcel-eip97ies";
312 reg = <0x90000 0x20000>;
313 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
314 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
315 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
316 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
317 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
318 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
319 interrupt-names = "mem", "ring0", "ring1",
320 "ring2", "ring3", "eip";
321 clocks = <&nb_periph_clk 15>;
324 sdhci1: sdhci@d0000 {
325 compatible = "marvell,armada-3700-sdhci",
326 "marvell,sdhci-xenon";
327 reg = <0xd0000 0x300>,
329 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
330 clocks = <&nb_periph_clk 0>;
331 clock-names = "core";
335 sdhci0: sdhci@d8000 {
336 compatible = "marvell,armada-3700-sdhci",
337 "marvell,sdhci-xenon";
338 reg = <0xd8000 0x300>,
340 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
341 clocks = <&nb_periph_clk 0>;
342 clock-names = "core";
347 compatible = "marvell,armada-3700-ahci";
348 reg = <0xe0000 0x2000>;
349 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
353 gic: interrupt-controller@1d00000 {
354 compatible = "arm,gic-v3";
355 #interrupt-cells = <3>;
356 interrupt-controller;
357 reg = <0x1d00000 0x10000>, /* GICD */
358 <0x1d40000 0x40000>, /* GICR */
359 <0x1d80000 0x2000>, /* GICC */
360 <0x1d90000 0x2000>, /* GICH */
361 <0x1da0000 0x20000>; /* GICV */
362 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
366 pcie0: pcie@d0070000 {
367 compatible = "marvell,armada-3700-pcie";
370 reg = <0 0xd0070000 0 0x20000>;
371 #address-cells = <3>;
373 bus-range = <0x00 0xff>;
374 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
375 #interrupt-cells = <1>;
376 msi-parent = <&pcie0>;
378 ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x1000000 /* Port 0 MEM */
379 0x81000000 0 0xe9000000 0 0xe9000000 0 0x10000>; /* Port 0 IO*/
380 interrupt-map-mask = <0 0 0 7>;
381 interrupt-map = <0 0 0 1 &pcie_intc 0>,
382 <0 0 0 2 &pcie_intc 1>,
383 <0 0 0 3 &pcie_intc 2>,
384 <0 0 0 4 &pcie_intc 3>;
385 pcie_intc: interrupt-controller {
386 interrupt-controller;
387 #interrupt-cells = <1>;