1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Marvell Armada 37xx family of SoCs.
5 * Copyright (C) 2016 Marvell
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 model = "Marvell Armada 37xx SoC";
15 compatible = "marvell,armada3700";
16 interrupt-parent = <&gic>;
31 * The PSCI firmware region depicted below is the default one
32 * and should be updated by the bootloader.
35 reg = <0 0x4000000 0 0x200000>;
45 compatible = "arm,cortex-a53", "arm,armv8";
47 clocks = <&nb_periph_clk 16>;
48 enable-method = "psci";
53 compatible = "arm,psci-0.2";
58 compatible = "arm,armv8-timer";
59 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
60 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
61 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
62 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
66 compatible = "arm,armv8-pmuv3";
67 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
71 compatible = "simple-bus";
76 internal-regs@d0000000 {
79 compatible = "simple-bus";
80 /* 32M internal register @ 0xd000_0000 */
81 ranges = <0x0 0x0 0xd0000000 0x2000000>;
84 compatible = "marvell,armada-3700-wdt";
86 marvell,system-controller = <&cpu_misc>;
90 cpu_misc: system-controller@d000 {
91 compatible = "marvell,armada-3700-cpu-misc",
93 reg = <0xd000 0x1000>;
97 compatible = "marvell,armada-3700-spi";
100 reg = <0x10600 0xA00>;
101 clocks = <&nb_periph_clk 7>;
102 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
108 compatible = "marvell,armada-3700-i2c";
109 reg = <0x11000 0x24>;
110 #address-cells = <1>;
112 clocks = <&nb_periph_clk 10>;
113 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
119 compatible = "marvell,armada-3700-i2c";
120 reg = <0x11080 0x24>;
121 #address-cells = <1>;
123 clocks = <&nb_periph_clk 9>;
124 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
130 compatible = "marvell,armada-3700-avs",
132 reg = <0x11500 0x40>;
135 uart0: serial@12000 {
136 compatible = "marvell,armada-3700-uart";
137 reg = <0x12000 0x200>;
140 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
141 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
142 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
143 interrupt-names = "uart-sum", "uart-tx", "uart-rx";
147 uart1: serial@12200 {
148 compatible = "marvell,armada-3700-uart-ext";
149 reg = <0x12200 0x30>;
152 <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
153 <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>;
154 interrupt-names = "uart-tx", "uart-rx";
158 nb_periph_clk: nb-periph-clk@13000 {
159 compatible = "marvell,armada-3700-periph-clock-nb";
160 reg = <0x13000 0x100>;
161 clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
162 <&tbg 3>, <&xtalclk>;
166 sb_periph_clk: sb-periph-clk@18000 {
167 compatible = "marvell,armada-3700-periph-clock-sb";
168 reg = <0x18000 0x100>;
169 clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
170 <&tbg 3>, <&xtalclk>;
175 compatible = "marvell,armada-3700-tbg-clock";
176 reg = <0x13200 0x100>;
181 pinctrl_nb: pinctrl@13800 {
182 compatible = "marvell,armada3710-nb-pinctrl",
183 "syscon", "simple-mfd";
184 reg = <0x13800 0x100>, <0x13C00 0x20>;
188 gpio-ranges = <&pinctrl_nb 0 0 36>;
190 interrupt-controller;
191 #interrupt-cells = <2>;
193 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
194 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
195 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
196 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
197 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
198 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
199 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
200 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
201 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
202 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
203 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
204 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
208 compatible = "marvell,armada-3700-xtal-clock";
209 clock-output-names = "xtal";
213 spi_quad_pins: spi-quad-pins {
218 i2c1_pins: i2c1-pins {
223 i2c2_pins: i2c2-pins {
228 uart1_pins: uart1-pins {
233 uart2_pins: uart2-pins {
239 nb_pm: syscon@14000 {
240 compatible = "marvell,armada-3700-nb-pm",
242 reg = <0x14000 0x60>;
245 pinctrl_sb: pinctrl@18800 {
246 compatible = "marvell,armada3710-sb-pinctrl",
247 "syscon", "simple-mfd";
248 reg = <0x18800 0x100>, <0x18C00 0x20>;
252 gpio-ranges = <&pinctrl_sb 0 0 30>;
254 interrupt-controller;
255 #interrupt-cells = <2>;
257 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
258 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
259 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
260 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
261 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
264 rgmii_pins: mii-pins {
271 eth0: ethernet@30000 {
272 compatible = "marvell,armada-3700-neta";
273 reg = <0x30000 0x4000>;
274 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
275 clocks = <&sb_periph_clk 8>;
280 #address-cells = <1>;
282 compatible = "marvell,orion-mdio";
286 eth1: ethernet@40000 {
287 compatible = "marvell,armada-3700-neta";
288 reg = <0x40000 0x4000>;
289 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
290 clocks = <&sb_periph_clk 7>;
295 compatible = "marvell,armada3700-xhci",
297 reg = <0x58000 0x4000>;
298 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
299 clocks = <&sb_periph_clk 12>;
304 compatible = "marvell,armada-3700-ehci";
305 reg = <0x5e000 0x2000>;
306 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
311 compatible = "marvell,armada-3700-xor";
312 reg = <0x60900 0x100>,
316 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
319 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
323 crypto: crypto@90000 {
324 compatible = "inside-secure,safexcel-eip97ies";
325 reg = <0x90000 0x20000>;
326 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
327 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
328 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
329 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
330 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
331 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
332 interrupt-names = "mem", "ring0", "ring1",
333 "ring2", "ring3", "eip";
334 clocks = <&nb_periph_clk 15>;
337 sdhci1: sdhci@d0000 {
338 compatible = "marvell,armada-3700-sdhci",
339 "marvell,sdhci-xenon";
340 reg = <0xd0000 0x300>,
342 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
343 clocks = <&nb_periph_clk 0>;
344 clock-names = "core";
348 sdhci0: sdhci@d8000 {
349 compatible = "marvell,armada-3700-sdhci",
350 "marvell,sdhci-xenon";
351 reg = <0xd8000 0x300>,
353 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
354 clocks = <&nb_periph_clk 0>;
355 clock-names = "core";
360 compatible = "marvell,armada-3700-ahci";
361 reg = <0xe0000 0x2000>;
362 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
366 gic: interrupt-controller@1d00000 {
367 compatible = "arm,gic-v3";
368 #interrupt-cells = <3>;
369 interrupt-controller;
370 reg = <0x1d00000 0x10000>, /* GICD */
371 <0x1d40000 0x40000>, /* GICR */
372 <0x1d80000 0x2000>, /* GICC */
373 <0x1d90000 0x2000>, /* GICH */
374 <0x1da0000 0x20000>; /* GICV */
375 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
379 pcie0: pcie@d0070000 {
380 compatible = "marvell,armada-3700-pcie";
383 reg = <0 0xd0070000 0 0x20000>;
384 #address-cells = <3>;
386 bus-range = <0x00 0xff>;
387 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
388 #interrupt-cells = <1>;
389 msi-parent = <&pcie0>;
391 ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x1000000 /* Port 0 MEM */
392 0x81000000 0 0xe9000000 0 0xe9000000 0 0x10000>; /* Port 0 IO*/
393 interrupt-map-mask = <0 0 0 7>;
394 interrupt-map = <0 0 0 1 &pcie_intc 0>,
395 <0 0 0 2 &pcie_intc 1>,
396 <0 0 0 3 &pcie_intc 2>,
397 <0 0 0 4 &pcie_intc 3>;
398 pcie_intc: interrupt-controller {
399 interrupt-controller;
400 #interrupt-cells = <1>;