1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Copyright (c) 2018 MediaTek Inc.
4 * Author: Ben Ho <ben.ho@mediatek.com>
5 * Erin Lo <erin.lo@mediatek.com>
8 #include <dt-bindings/clock/mt8183-clk.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include "mt8183-pinfunc.h"
14 compatible = "mediatek,mt8183";
15 interrupt-parent = <&sysirq>;
72 compatible = "arm,cortex-a53";
74 enable-method = "psci";
75 capacity-dmips-mhz = <741>;
80 compatible = "arm,cortex-a53";
82 enable-method = "psci";
83 capacity-dmips-mhz = <741>;
88 compatible = "arm,cortex-a53";
90 enable-method = "psci";
91 capacity-dmips-mhz = <741>;
96 compatible = "arm,cortex-a53";
98 enable-method = "psci";
99 capacity-dmips-mhz = <741>;
104 compatible = "arm,cortex-a73";
106 enable-method = "psci";
107 capacity-dmips-mhz = <1024>;
112 compatible = "arm,cortex-a73";
114 enable-method = "psci";
115 capacity-dmips-mhz = <1024>;
120 compatible = "arm,cortex-a73";
122 enable-method = "psci";
123 capacity-dmips-mhz = <1024>;
128 compatible = "arm,cortex-a73";
130 enable-method = "psci";
131 capacity-dmips-mhz = <1024>;
136 compatible = "arm,cortex-a53-pmu";
137 interrupt-parent = <&gic>;
138 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
142 compatible = "arm,cortex-a73-pmu";
143 interrupt-parent = <&gic>;
144 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
148 compatible = "arm,psci-1.0";
153 compatible = "fixed-clock";
155 clock-frequency = <26000000>;
156 clock-output-names = "clk26m";
160 compatible = "arm,armv8-timer";
161 interrupt-parent = <&gic>;
162 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
163 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
164 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
165 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
169 #address-cells = <2>;
171 compatible = "simple-bus";
174 soc_data: soc_data@8000000 {
175 compatible = "mediatek,mt8183-efuse",
177 reg = <0 0x08000000 0 0x0010>;
178 #address-cells = <1>;
183 gic: interrupt-controller@c000000 {
184 compatible = "arm,gic-v3";
185 #interrupt-cells = <4>;
186 interrupt-parent = <&gic>;
187 interrupt-controller;
188 reg = <0 0x0c000000 0 0x40000>, /* GICD */
189 <0 0x0c100000 0 0x200000>, /* GICR */
190 <0 0x0c400000 0 0x2000>, /* GICC */
191 <0 0x0c410000 0 0x1000>, /* GICH */
192 <0 0x0c420000 0 0x2000>; /* GICV */
194 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
196 ppi_cluster0: interrupt-partition-0 {
197 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
199 ppi_cluster1: interrupt-partition-1 {
200 affinity = <&cpu4 &cpu5 &cpu6 &cpu7>;
205 mcucfg: syscon@c530000 {
206 compatible = "mediatek,mt8183-mcucfg", "syscon";
207 reg = <0 0x0c530000 0 0x1000>;
211 sysirq: interrupt-controller@c530a80 {
212 compatible = "mediatek,mt8183-sysirq",
213 "mediatek,mt6577-sysirq";
214 interrupt-controller;
215 #interrupt-cells = <3>;
216 interrupt-parent = <&gic>;
217 reg = <0 0x0c530a80 0 0x50>;
220 topckgen: syscon@10000000 {
221 compatible = "mediatek,mt8183-topckgen", "syscon";
222 reg = <0 0x10000000 0 0x1000>;
226 infracfg: syscon@10001000 {
227 compatible = "mediatek,mt8183-infracfg", "syscon";
228 reg = <0 0x10001000 0 0x1000>;
232 pio: pinctrl@10005000 {
233 compatible = "mediatek,mt8183-pinctrl";
234 reg = <0 0x10005000 0 0x1000>,
235 <0 0x11f20000 0 0x1000>,
236 <0 0x11e80000 0 0x1000>,
237 <0 0x11e70000 0 0x1000>,
238 <0 0x11e90000 0 0x1000>,
239 <0 0x11d30000 0 0x1000>,
240 <0 0x11d20000 0 0x1000>,
241 <0 0x11c50000 0 0x1000>,
242 <0 0x11f30000 0 0x1000>,
243 <0 0x1000b000 0 0x1000>;
244 reg-names = "iocfg0", "iocfg1", "iocfg2",
245 "iocfg3", "iocfg4", "iocfg5",
246 "iocfg6", "iocfg7", "iocfg8",
250 gpio-ranges = <&pio 0 0 192>;
251 interrupt-controller;
252 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
253 #interrupt-cells = <2>;
256 apmixedsys: syscon@1000c000 {
257 compatible = "mediatek,mt8183-apmixedsys", "syscon";
258 reg = <0 0x1000c000 0 0x1000>;
262 pwrap: pwrap@1000d000 {
263 compatible = "mediatek,mt8183-pwrap";
264 reg = <0 0x1000d000 0 0x1000>;
266 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
267 clocks = <&topckgen CLK_TOP_MUX_PMICSPI>,
268 <&infracfg CLK_INFRA_PMIC_AP>;
269 clock-names = "spi", "wrap";
272 systimer: timer@10017000 {
273 compatible = "mediatek,mt8183-timer",
274 "mediatek,mt6765-timer";
275 reg = <0 0x10017000 0 0x1000>;
276 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
277 clocks = <&topckgen CLK_TOP_CLK13M>;
278 clock-names = "clk13m";
281 auxadc: auxadc@11001000 {
282 compatible = "mediatek,mt8183-auxadc",
283 "mediatek,mt8173-auxadc";
284 reg = <0 0x11001000 0 0x1000>;
285 clocks = <&infracfg CLK_INFRA_AUXADC>;
286 clock-names = "main";
287 #io-channel-cells = <1>;
291 uart0: serial@11002000 {
292 compatible = "mediatek,mt8183-uart",
293 "mediatek,mt6577-uart";
294 reg = <0 0x11002000 0 0x1000>;
295 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
296 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>;
297 clock-names = "baud", "bus";
301 uart1: serial@11003000 {
302 compatible = "mediatek,mt8183-uart",
303 "mediatek,mt6577-uart";
304 reg = <0 0x11003000 0 0x1000>;
305 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
306 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>;
307 clock-names = "baud", "bus";
311 uart2: serial@11004000 {
312 compatible = "mediatek,mt8183-uart",
313 "mediatek,mt6577-uart";
314 reg = <0 0x11004000 0 0x1000>;
315 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
316 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>;
317 clock-names = "baud", "bus";
322 compatible = "mediatek,mt8183-i2c";
323 reg = <0 0x11005000 0 0x1000>,
324 <0 0x11000600 0 0x80>;
325 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
326 clocks = <&infracfg CLK_INFRA_I2C6>,
327 <&infracfg CLK_INFRA_AP_DMA>;
328 clock-names = "main", "dma";
330 #address-cells = <1>;
336 compatible = "mediatek,mt8183-i2c";
337 reg = <0 0x11007000 0 0x1000>,
338 <0 0x11000080 0 0x80>;
339 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
340 clocks = <&infracfg CLK_INFRA_I2C0>,
341 <&infracfg CLK_INFRA_AP_DMA>;
342 clock-names = "main", "dma";
344 #address-cells = <1>;
350 compatible = "mediatek,mt8183-i2c";
351 reg = <0 0x11008000 0 0x1000>,
352 <0 0x11000100 0 0x80>;
353 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>;
354 clocks = <&infracfg CLK_INFRA_I2C1>,
355 <&infracfg CLK_INFRA_AP_DMA>,
356 <&infracfg CLK_INFRA_I2C1_ARBITER>;
357 clock-names = "main", "dma","arb";
359 #address-cells = <1>;
365 compatible = "mediatek,mt8183-i2c";
366 reg = <0 0x11009000 0 0x1000>,
367 <0 0x11000280 0 0x80>;
368 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
369 clocks = <&infracfg CLK_INFRA_I2C2>,
370 <&infracfg CLK_INFRA_AP_DMA>,
371 <&infracfg CLK_INFRA_I2C2_ARBITER>;
372 clock-names = "main", "dma", "arb";
374 #address-cells = <1>;
380 compatible = "mediatek,mt8183-spi";
381 #address-cells = <1>;
383 reg = <0 0x1100a000 0 0x1000>;
384 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_LOW>;
385 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
386 <&topckgen CLK_TOP_MUX_SPI>,
387 <&infracfg CLK_INFRA_SPI0>;
388 clock-names = "parent-clk", "sel-clk", "spi-clk";
393 compatible = "mediatek,mt8183-i2c";
394 reg = <0 0x1100f000 0 0x1000>,
395 <0 0x11000400 0 0x80>;
396 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
397 clocks = <&infracfg CLK_INFRA_I2C3>,
398 <&infracfg CLK_INFRA_AP_DMA>;
399 clock-names = "main", "dma";
401 #address-cells = <1>;
407 compatible = "mediatek,mt8183-spi";
408 #address-cells = <1>;
410 reg = <0 0x11010000 0 0x1000>;
411 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_LOW>;
412 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
413 <&topckgen CLK_TOP_MUX_SPI>,
414 <&infracfg CLK_INFRA_SPI1>;
415 clock-names = "parent-clk", "sel-clk", "spi-clk";
420 compatible = "mediatek,mt8183-i2c";
421 reg = <0 0x11011000 0 0x1000>,
422 <0 0x11000480 0 0x80>;
423 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
424 clocks = <&infracfg CLK_INFRA_I2C4>,
425 <&infracfg CLK_INFRA_AP_DMA>;
426 clock-names = "main", "dma";
428 #address-cells = <1>;
434 compatible = "mediatek,mt8183-spi";
435 #address-cells = <1>;
437 reg = <0 0x11012000 0 0x1000>;
438 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>;
439 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
440 <&topckgen CLK_TOP_MUX_SPI>,
441 <&infracfg CLK_INFRA_SPI2>;
442 clock-names = "parent-clk", "sel-clk", "spi-clk";
447 compatible = "mediatek,mt8183-spi";
448 #address-cells = <1>;
450 reg = <0 0x11013000 0 0x1000>;
451 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_LOW>;
452 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
453 <&topckgen CLK_TOP_MUX_SPI>,
454 <&infracfg CLK_INFRA_SPI3>;
455 clock-names = "parent-clk", "sel-clk", "spi-clk";
460 compatible = "mediatek,mt8183-i2c";
461 reg = <0 0x11014000 0 0x1000>,
462 <0 0x11000180 0 0x80>;
463 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_LOW>;
464 clocks = <&infracfg CLK_INFRA_I2C1_IMM>,
465 <&infracfg CLK_INFRA_AP_DMA>,
466 <&infracfg CLK_INFRA_I2C1_ARBITER>;
467 clock-names = "main", "dma", "arb";
469 #address-cells = <1>;
474 i2c10: i2c@11015000 {
475 compatible = "mediatek,mt8183-i2c";
476 reg = <0 0x11015000 0 0x1000>,
477 <0 0x11000300 0 0x80>;
478 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
479 clocks = <&infracfg CLK_INFRA_I2C2_IMM>,
480 <&infracfg CLK_INFRA_AP_DMA>,
481 <&infracfg CLK_INFRA_I2C2_ARBITER>;
482 clock-names = "main", "dma", "arb";
484 #address-cells = <1>;
490 compatible = "mediatek,mt8183-i2c";
491 reg = <0 0x11016000 0 0x1000>,
492 <0 0x11000500 0 0x80>;
493 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
494 clocks = <&infracfg CLK_INFRA_I2C5>,
495 <&infracfg CLK_INFRA_AP_DMA>,
496 <&infracfg CLK_INFRA_I2C5_ARBITER>;
497 clock-names = "main", "dma", "arb";
499 #address-cells = <1>;
504 i2c11: i2c@11017000 {
505 compatible = "mediatek,mt8183-i2c";
506 reg = <0 0x11017000 0 0x1000>,
507 <0 0x11000580 0 0x80>;
508 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_LOW>;
509 clocks = <&infracfg CLK_INFRA_I2C5_IMM>,
510 <&infracfg CLK_INFRA_AP_DMA>,
511 <&infracfg CLK_INFRA_I2C5_ARBITER>;
512 clock-names = "main", "dma", "arb";
514 #address-cells = <1>;
520 compatible = "mediatek,mt8183-spi";
521 #address-cells = <1>;
523 reg = <0 0x11018000 0 0x1000>;
524 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_LOW>;
525 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
526 <&topckgen CLK_TOP_MUX_SPI>,
527 <&infracfg CLK_INFRA_SPI4>;
528 clock-names = "parent-clk", "sel-clk", "spi-clk";
533 compatible = "mediatek,mt8183-spi";
534 #address-cells = <1>;
536 reg = <0 0x11019000 0 0x1000>;
537 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>;
538 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
539 <&topckgen CLK_TOP_MUX_SPI>,
540 <&infracfg CLK_INFRA_SPI5>;
541 clock-names = "parent-clk", "sel-clk", "spi-clk";
546 compatible = "mediatek,mt8183-i2c";
547 reg = <0 0x1101a000 0 0x1000>,
548 <0 0x11000680 0 0x80>;
549 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>;
550 clocks = <&infracfg CLK_INFRA_I2C7>,
551 <&infracfg CLK_INFRA_AP_DMA>;
552 clock-names = "main", "dma";
554 #address-cells = <1>;
560 compatible = "mediatek,mt8183-i2c";
561 reg = <0 0x1101b000 0 0x1000>,
562 <0 0x11000700 0 0x80>;
563 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>;
564 clocks = <&infracfg CLK_INFRA_I2C8>,
565 <&infracfg CLK_INFRA_AP_DMA>;
566 clock-names = "main", "dma";
568 #address-cells = <1>;
573 audiosys: syscon@11220000 {
574 compatible = "mediatek,mt8183-audiosys", "syscon";
575 reg = <0 0x11220000 0 0x1000>;
579 efuse: efuse@11f10000 {
580 compatible = "mediatek,mt8183-efuse",
582 reg = <0 0x11f10000 0 0x1000>;
585 mfgcfg: syscon@13000000 {
586 compatible = "mediatek,mt8183-mfgcfg", "syscon";
587 reg = <0 0x13000000 0 0x1000>;
591 mmsys: syscon@14000000 {
592 compatible = "mediatek,mt8183-mmsys", "syscon";
593 reg = <0 0x14000000 0 0x1000>;
597 imgsys: syscon@15020000 {
598 compatible = "mediatek,mt8183-imgsys", "syscon";
599 reg = <0 0x15020000 0 0x1000>;
603 vdecsys: syscon@16000000 {
604 compatible = "mediatek,mt8183-vdecsys", "syscon";
605 reg = <0 0x16000000 0 0x1000>;
609 vencsys: syscon@17000000 {
610 compatible = "mediatek,mt8183-vencsys", "syscon";
611 reg = <0 0x17000000 0 0x1000>;
615 ipu_conn: syscon@19000000 {
616 compatible = "mediatek,mt8183-ipu_conn", "syscon";
617 reg = <0 0x19000000 0 0x1000>;
621 ipu_adl: syscon@19010000 {
622 compatible = "mediatek,mt8183-ipu_adl", "syscon";
623 reg = <0 0x19010000 0 0x1000>;
627 ipu_core0: syscon@19180000 {
628 compatible = "mediatek,mt8183-ipu_core0", "syscon";
629 reg = <0 0x19180000 0 0x1000>;
633 ipu_core1: syscon@19280000 {
634 compatible = "mediatek,mt8183-ipu_core1", "syscon";
635 reg = <0 0x19280000 0 0x1000>;
639 camsys: syscon@1a000000 {
640 compatible = "mediatek,mt8183-camsys", "syscon";
641 reg = <0 0x1a000000 0 0x1000>;