1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Copyright (c) 2018 MediaTek Inc.
4 * Author: Ben Ho <ben.ho@mediatek.com>
5 * Erin Lo <erin.lo@mediatek.com>
8 #include <dt-bindings/clock/mt8183-clk.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/reset-controller/mt8183-resets.h>
12 #include "mt8183-pinfunc.h"
15 compatible = "mediatek,mt8183";
16 interrupt-parent = <&sysirq>;
73 compatible = "arm,cortex-a53";
75 enable-method = "psci";
76 capacity-dmips-mhz = <741>;
81 compatible = "arm,cortex-a53";
83 enable-method = "psci";
84 capacity-dmips-mhz = <741>;
89 compatible = "arm,cortex-a53";
91 enable-method = "psci";
92 capacity-dmips-mhz = <741>;
97 compatible = "arm,cortex-a53";
99 enable-method = "psci";
100 capacity-dmips-mhz = <741>;
105 compatible = "arm,cortex-a73";
107 enable-method = "psci";
108 capacity-dmips-mhz = <1024>;
113 compatible = "arm,cortex-a73";
115 enable-method = "psci";
116 capacity-dmips-mhz = <1024>;
121 compatible = "arm,cortex-a73";
123 enable-method = "psci";
124 capacity-dmips-mhz = <1024>;
129 compatible = "arm,cortex-a73";
131 enable-method = "psci";
132 capacity-dmips-mhz = <1024>;
137 compatible = "arm,cortex-a53-pmu";
138 interrupt-parent = <&gic>;
139 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
143 compatible = "arm,cortex-a73-pmu";
144 interrupt-parent = <&gic>;
145 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
149 compatible = "arm,psci-1.0";
154 compatible = "fixed-clock";
156 clock-frequency = <26000000>;
157 clock-output-names = "clk26m";
161 compatible = "arm,armv8-timer";
162 interrupt-parent = <&gic>;
163 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
164 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
165 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
166 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
170 #address-cells = <2>;
172 compatible = "simple-bus";
175 soc_data: soc_data@8000000 {
176 compatible = "mediatek,mt8183-efuse",
178 reg = <0 0x08000000 0 0x0010>;
179 #address-cells = <1>;
184 gic: interrupt-controller@c000000 {
185 compatible = "arm,gic-v3";
186 #interrupt-cells = <4>;
187 interrupt-parent = <&gic>;
188 interrupt-controller;
189 reg = <0 0x0c000000 0 0x40000>, /* GICD */
190 <0 0x0c100000 0 0x200000>, /* GICR */
191 <0 0x0c400000 0 0x2000>, /* GICC */
192 <0 0x0c410000 0 0x1000>, /* GICH */
193 <0 0x0c420000 0 0x2000>; /* GICV */
195 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
197 ppi_cluster0: interrupt-partition-0 {
198 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
200 ppi_cluster1: interrupt-partition-1 {
201 affinity = <&cpu4 &cpu5 &cpu6 &cpu7>;
206 mcucfg: syscon@c530000 {
207 compatible = "mediatek,mt8183-mcucfg", "syscon";
208 reg = <0 0x0c530000 0 0x1000>;
212 sysirq: interrupt-controller@c530a80 {
213 compatible = "mediatek,mt8183-sysirq",
214 "mediatek,mt6577-sysirq";
215 interrupt-controller;
216 #interrupt-cells = <3>;
217 interrupt-parent = <&gic>;
218 reg = <0 0x0c530a80 0 0x50>;
221 topckgen: syscon@10000000 {
222 compatible = "mediatek,mt8183-topckgen", "syscon";
223 reg = <0 0x10000000 0 0x1000>;
227 infracfg: syscon@10001000 {
228 compatible = "mediatek,mt8183-infracfg", "syscon";
229 reg = <0 0x10001000 0 0x1000>;
234 pio: pinctrl@10005000 {
235 compatible = "mediatek,mt8183-pinctrl";
236 reg = <0 0x10005000 0 0x1000>,
237 <0 0x11f20000 0 0x1000>,
238 <0 0x11e80000 0 0x1000>,
239 <0 0x11e70000 0 0x1000>,
240 <0 0x11e90000 0 0x1000>,
241 <0 0x11d30000 0 0x1000>,
242 <0 0x11d20000 0 0x1000>,
243 <0 0x11c50000 0 0x1000>,
244 <0 0x11f30000 0 0x1000>,
245 <0 0x1000b000 0 0x1000>;
246 reg-names = "iocfg0", "iocfg1", "iocfg2",
247 "iocfg3", "iocfg4", "iocfg5",
248 "iocfg6", "iocfg7", "iocfg8",
252 gpio-ranges = <&pio 0 0 192>;
253 interrupt-controller;
254 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
255 #interrupt-cells = <2>;
258 apmixedsys: syscon@1000c000 {
259 compatible = "mediatek,mt8183-apmixedsys", "syscon";
260 reg = <0 0x1000c000 0 0x1000>;
264 pwrap: pwrap@1000d000 {
265 compatible = "mediatek,mt8183-pwrap";
266 reg = <0 0x1000d000 0 0x1000>;
268 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
269 clocks = <&topckgen CLK_TOP_MUX_PMICSPI>,
270 <&infracfg CLK_INFRA_PMIC_AP>;
271 clock-names = "spi", "wrap";
274 systimer: timer@10017000 {
275 compatible = "mediatek,mt8183-timer",
276 "mediatek,mt6765-timer";
277 reg = <0 0x10017000 0 0x1000>;
278 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
279 clocks = <&topckgen CLK_TOP_CLK13M>;
280 clock-names = "clk13m";
283 gce: mailbox@10238000 {
284 compatible = "mediatek,mt8183-gce";
285 reg = <0 0x10238000 0 0x4000>;
286 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_LOW>;
288 clocks = <&infracfg CLK_INFRA_GCE>;
292 auxadc: auxadc@11001000 {
293 compatible = "mediatek,mt8183-auxadc",
294 "mediatek,mt8173-auxadc";
295 reg = <0 0x11001000 0 0x1000>;
296 clocks = <&infracfg CLK_INFRA_AUXADC>;
297 clock-names = "main";
298 #io-channel-cells = <1>;
302 uart0: serial@11002000 {
303 compatible = "mediatek,mt8183-uart",
304 "mediatek,mt6577-uart";
305 reg = <0 0x11002000 0 0x1000>;
306 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
307 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>;
308 clock-names = "baud", "bus";
312 uart1: serial@11003000 {
313 compatible = "mediatek,mt8183-uart",
314 "mediatek,mt6577-uart";
315 reg = <0 0x11003000 0 0x1000>;
316 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
317 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>;
318 clock-names = "baud", "bus";
322 uart2: serial@11004000 {
323 compatible = "mediatek,mt8183-uart",
324 "mediatek,mt6577-uart";
325 reg = <0 0x11004000 0 0x1000>;
326 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
327 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>;
328 clock-names = "baud", "bus";
333 compatible = "mediatek,mt8183-i2c";
334 reg = <0 0x11005000 0 0x1000>,
335 <0 0x11000600 0 0x80>;
336 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
337 clocks = <&infracfg CLK_INFRA_I2C6>,
338 <&infracfg CLK_INFRA_AP_DMA>;
339 clock-names = "main", "dma";
341 #address-cells = <1>;
347 compatible = "mediatek,mt8183-i2c";
348 reg = <0 0x11007000 0 0x1000>,
349 <0 0x11000080 0 0x80>;
350 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
351 clocks = <&infracfg CLK_INFRA_I2C0>,
352 <&infracfg CLK_INFRA_AP_DMA>;
353 clock-names = "main", "dma";
355 #address-cells = <1>;
361 compatible = "mediatek,mt8183-i2c";
362 reg = <0 0x11008000 0 0x1000>,
363 <0 0x11000100 0 0x80>;
364 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>;
365 clocks = <&infracfg CLK_INFRA_I2C1>,
366 <&infracfg CLK_INFRA_AP_DMA>,
367 <&infracfg CLK_INFRA_I2C1_ARBITER>;
368 clock-names = "main", "dma","arb";
370 #address-cells = <1>;
376 compatible = "mediatek,mt8183-i2c";
377 reg = <0 0x11009000 0 0x1000>,
378 <0 0x11000280 0 0x80>;
379 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
380 clocks = <&infracfg CLK_INFRA_I2C2>,
381 <&infracfg CLK_INFRA_AP_DMA>,
382 <&infracfg CLK_INFRA_I2C2_ARBITER>;
383 clock-names = "main", "dma", "arb";
385 #address-cells = <1>;
391 compatible = "mediatek,mt8183-spi";
392 #address-cells = <1>;
394 reg = <0 0x1100a000 0 0x1000>;
395 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_LOW>;
396 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
397 <&topckgen CLK_TOP_MUX_SPI>,
398 <&infracfg CLK_INFRA_SPI0>;
399 clock-names = "parent-clk", "sel-clk", "spi-clk";
404 compatible = "mediatek,mt8183-i2c";
405 reg = <0 0x1100f000 0 0x1000>,
406 <0 0x11000400 0 0x80>;
407 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
408 clocks = <&infracfg CLK_INFRA_I2C3>,
409 <&infracfg CLK_INFRA_AP_DMA>;
410 clock-names = "main", "dma";
412 #address-cells = <1>;
418 compatible = "mediatek,mt8183-spi";
419 #address-cells = <1>;
421 reg = <0 0x11010000 0 0x1000>;
422 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_LOW>;
423 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
424 <&topckgen CLK_TOP_MUX_SPI>,
425 <&infracfg CLK_INFRA_SPI1>;
426 clock-names = "parent-clk", "sel-clk", "spi-clk";
431 compatible = "mediatek,mt8183-i2c";
432 reg = <0 0x11011000 0 0x1000>,
433 <0 0x11000480 0 0x80>;
434 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
435 clocks = <&infracfg CLK_INFRA_I2C4>,
436 <&infracfg CLK_INFRA_AP_DMA>;
437 clock-names = "main", "dma";
439 #address-cells = <1>;
445 compatible = "mediatek,mt8183-spi";
446 #address-cells = <1>;
448 reg = <0 0x11012000 0 0x1000>;
449 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>;
450 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
451 <&topckgen CLK_TOP_MUX_SPI>,
452 <&infracfg CLK_INFRA_SPI2>;
453 clock-names = "parent-clk", "sel-clk", "spi-clk";
458 compatible = "mediatek,mt8183-spi";
459 #address-cells = <1>;
461 reg = <0 0x11013000 0 0x1000>;
462 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_LOW>;
463 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
464 <&topckgen CLK_TOP_MUX_SPI>,
465 <&infracfg CLK_INFRA_SPI3>;
466 clock-names = "parent-clk", "sel-clk", "spi-clk";
471 compatible = "mediatek,mt8183-i2c";
472 reg = <0 0x11014000 0 0x1000>,
473 <0 0x11000180 0 0x80>;
474 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_LOW>;
475 clocks = <&infracfg CLK_INFRA_I2C1_IMM>,
476 <&infracfg CLK_INFRA_AP_DMA>,
477 <&infracfg CLK_INFRA_I2C1_ARBITER>;
478 clock-names = "main", "dma", "arb";
480 #address-cells = <1>;
485 i2c10: i2c@11015000 {
486 compatible = "mediatek,mt8183-i2c";
487 reg = <0 0x11015000 0 0x1000>,
488 <0 0x11000300 0 0x80>;
489 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
490 clocks = <&infracfg CLK_INFRA_I2C2_IMM>,
491 <&infracfg CLK_INFRA_AP_DMA>,
492 <&infracfg CLK_INFRA_I2C2_ARBITER>;
493 clock-names = "main", "dma", "arb";
495 #address-cells = <1>;
501 compatible = "mediatek,mt8183-i2c";
502 reg = <0 0x11016000 0 0x1000>,
503 <0 0x11000500 0 0x80>;
504 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
505 clocks = <&infracfg CLK_INFRA_I2C5>,
506 <&infracfg CLK_INFRA_AP_DMA>,
507 <&infracfg CLK_INFRA_I2C5_ARBITER>;
508 clock-names = "main", "dma", "arb";
510 #address-cells = <1>;
515 i2c11: i2c@11017000 {
516 compatible = "mediatek,mt8183-i2c";
517 reg = <0 0x11017000 0 0x1000>,
518 <0 0x11000580 0 0x80>;
519 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_LOW>;
520 clocks = <&infracfg CLK_INFRA_I2C5_IMM>,
521 <&infracfg CLK_INFRA_AP_DMA>,
522 <&infracfg CLK_INFRA_I2C5_ARBITER>;
523 clock-names = "main", "dma", "arb";
525 #address-cells = <1>;
531 compatible = "mediatek,mt8183-spi";
532 #address-cells = <1>;
534 reg = <0 0x11018000 0 0x1000>;
535 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_LOW>;
536 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
537 <&topckgen CLK_TOP_MUX_SPI>,
538 <&infracfg CLK_INFRA_SPI4>;
539 clock-names = "parent-clk", "sel-clk", "spi-clk";
544 compatible = "mediatek,mt8183-spi";
545 #address-cells = <1>;
547 reg = <0 0x11019000 0 0x1000>;
548 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>;
549 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
550 <&topckgen CLK_TOP_MUX_SPI>,
551 <&infracfg CLK_INFRA_SPI5>;
552 clock-names = "parent-clk", "sel-clk", "spi-clk";
557 compatible = "mediatek,mt8183-i2c";
558 reg = <0 0x1101a000 0 0x1000>,
559 <0 0x11000680 0 0x80>;
560 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>;
561 clocks = <&infracfg CLK_INFRA_I2C7>,
562 <&infracfg CLK_INFRA_AP_DMA>;
563 clock-names = "main", "dma";
565 #address-cells = <1>;
571 compatible = "mediatek,mt8183-i2c";
572 reg = <0 0x1101b000 0 0x1000>,
573 <0 0x11000700 0 0x80>;
574 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>;
575 clocks = <&infracfg CLK_INFRA_I2C8>,
576 <&infracfg CLK_INFRA_AP_DMA>;
577 clock-names = "main", "dma";
579 #address-cells = <1>;
584 audiosys: syscon@11220000 {
585 compatible = "mediatek,mt8183-audiosys", "syscon";
586 reg = <0 0x11220000 0 0x1000>;
590 efuse: efuse@11f10000 {
591 compatible = "mediatek,mt8183-efuse",
593 reg = <0 0x11f10000 0 0x1000>;
596 mfgcfg: syscon@13000000 {
597 compatible = "mediatek,mt8183-mfgcfg", "syscon";
598 reg = <0 0x13000000 0 0x1000>;
602 mmsys: syscon@14000000 {
603 compatible = "mediatek,mt8183-mmsys", "syscon";
604 reg = <0 0x14000000 0 0x1000>;
608 imgsys: syscon@15020000 {
609 compatible = "mediatek,mt8183-imgsys", "syscon";
610 reg = <0 0x15020000 0 0x1000>;
614 vdecsys: syscon@16000000 {
615 compatible = "mediatek,mt8183-vdecsys", "syscon";
616 reg = <0 0x16000000 0 0x1000>;
620 vencsys: syscon@17000000 {
621 compatible = "mediatek,mt8183-vencsys", "syscon";
622 reg = <0 0x17000000 0 0x1000>;
626 ipu_conn: syscon@19000000 {
627 compatible = "mediatek,mt8183-ipu_conn", "syscon";
628 reg = <0 0x19000000 0 0x1000>;
632 ipu_adl: syscon@19010000 {
633 compatible = "mediatek,mt8183-ipu_adl", "syscon";
634 reg = <0 0x19010000 0 0x1000>;
638 ipu_core0: syscon@19180000 {
639 compatible = "mediatek,mt8183-ipu_core0", "syscon";
640 reg = <0 0x19180000 0 0x1000>;
644 ipu_core1: syscon@19280000 {
645 compatible = "mediatek,mt8183-ipu_core1", "syscon";
646 reg = <0 0x19280000 0 0x1000>;
650 camsys: syscon@1a000000 {
651 compatible = "mediatek,mt8183-camsys", "syscon";
652 reg = <0 0x1a000000 0 0x1000>;