sys/gnu/dts/arm64/mediatek/mt8183.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Copyright (c) 2018 MediaTek Inc.
   4  * Author: Ben Ho <ben.ho@mediatek.com>
   5  *         Erin Lo <erin.lo@mediatek.com>
   6  */
   7
   8 #include <dt-bindings/clock/mt8183-clk.h>
   9 #include <dt-bindings/interrupt-controller/arm-gic.h>
  10 #include <dt-bindings/interrupt-controller/irq.h>
  11 #include <dt-bindings/reset-controller/mt8183-resets.h>
  12 #include "mt8183-pinfunc.h"
  13
  14 / {
  15         compatible = "mediatek,mt8183";
  16         interrupt-parent = <&sysirq>;
  17         #address-cells = <2>;
  18         #size-cells = <2>;
  19
  20         aliases {
  21                 i2c0 = &i2c0;
  22                 i2c1 = &i2c1;
  23                 i2c2 = &i2c2;
  24                 i2c3 = &i2c3;
  25                 i2c4 = &i2c4;
  26                 i2c5 = &i2c5;
  27                 i2c6 = &i2c6;
  28                 i2c7 = &i2c7;
  29                 i2c8 = &i2c8;
  30                 i2c9 = &i2c9;
  31                 i2c10 = &i2c10;
  32                 i2c11 = &i2c11;
  33         };
  34
  35         cpus {
  36                 #address-cells = <1>;
  37                 #size-cells = <0>;
  38
  39                 cpu-map {
  40                         cluster0 {
  41                                 core0 {
  42                                         cpu = <&cpu0>;
  43                                 };
  44                                 core1 {
  45                                         cpu = <&cpu1>;
  46                                 };
  47                                 core2 {
  48                                         cpu = <&cpu2>;
  49                                 };
  50                                 core3 {
  51                                         cpu = <&cpu3>;
  52                                 };
  53                         };
  54
  55                         cluster1 {
  56                                 core0 {
  57                                         cpu = <&cpu4>;
  58                                 };
  59                                 core1 {
  60                                         cpu = <&cpu5>;
  61                                 };
  62                                 core2 {
  63                                         cpu = <&cpu6>;
  64                                 };
  65                                 core3 {
  66                                         cpu = <&cpu7>;
  67                                 };
  68                         };
  69                 };
  70
  71                 cpu0: cpu@0 {
  72                         device_type = "cpu";
  73                         compatible = "arm,cortex-a53";
  74                         reg = <0x000>;
  75                         enable-method = "psci";
  76                         capacity-dmips-mhz = <741>;
  77                 };
  78
  79                 cpu1: cpu@1 {
  80                         device_type = "cpu";
  81                         compatible = "arm,cortex-a53";
  82                         reg = <0x001>;
  83                         enable-method = "psci";
  84                         capacity-dmips-mhz = <741>;
  85                 };
  86
  87                 cpu2: cpu@2 {
  88                         device_type = "cpu";
  89                         compatible = "arm,cortex-a53";
  90                         reg = <0x002>;
  91                         enable-method = "psci";
  92                         capacity-dmips-mhz = <741>;
  93                 };
  94
  95                 cpu3: cpu@3 {
  96                         device_type = "cpu";
  97                         compatible = "arm,cortex-a53";
  98                         reg = <0x003>;
  99                         enable-method = "psci";
 100                         capacity-dmips-mhz = <741>;
 101                 };
 102
 103                 cpu4: cpu@100 {
 104                         device_type = "cpu";
 105                         compatible = "arm,cortex-a73";
 106                         reg = <0x100>;
 107                         enable-method = "psci";
 108                         capacity-dmips-mhz = <1024>;
 109                 };
 110
 111                 cpu5: cpu@101 {
 112                         device_type = "cpu";
 113                         compatible = "arm,cortex-a73";
 114                         reg = <0x101>;
 115                         enable-method = "psci";
 116                         capacity-dmips-mhz = <1024>;
 117                 };
 118
 119                 cpu6: cpu@102 {
 120                         device_type = "cpu";
 121                         compatible = "arm,cortex-a73";
 122                         reg = <0x102>;
 123                         enable-method = "psci";
 124                         capacity-dmips-mhz = <1024>;
 125                 };
 126
 127                 cpu7: cpu@103 {
 128                         device_type = "cpu";
 129                         compatible = "arm,cortex-a73";
 130                         reg = <0x103>;
 131                         enable-method = "psci";
 132                         capacity-dmips-mhz = <1024>;
 133                 };
 134         };
 135
 136         pmu-a53 {
 137                 compatible = "arm,cortex-a53-pmu";
 138                 interrupt-parent = <&gic>;
 139                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
 140         };
 141
 142         pmu-a73 {
 143                 compatible = "arm,cortex-a73-pmu";
 144                 interrupt-parent = <&gic>;
 145                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
 146         };
 147
 148         psci {
 149                 compatible      = "arm,psci-1.0";
 150                 method          = "smc";
 151         };
 152
 153         clk26m: oscillator {
 154                 compatible = "fixed-clock";
 155                 #clock-cells = <0>;
 156                 clock-frequency = <26000000>;
 157                 clock-output-names = "clk26m";
 158         };
 159
 160         timer {
 161                 compatible = "arm,armv8-timer";
 162                 interrupt-parent = <&gic>;
 163                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
 164                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
 165                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
 166                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
 167         };
 168
 169         soc {
 170                 #address-cells = <2>;
 171                 #size-cells = <2>;
 172                 compatible = "simple-bus";
 173                 ranges;
 174
 175                 soc_data: soc_data@8000000 {
 176                         compatible = "mediatek,mt8183-efuse",
 177                                      "mediatek,efuse";
 178                         reg = <0 0x08000000 0 0x0010>;
 179                         #address-cells = <1>;
 180                         #size-cells = <1>;
 181                         status = "disabled";
 182                 };
 183
 184                 gic: interrupt-controller@c000000 {
 185                         compatible = "arm,gic-v3";
 186                         #interrupt-cells = <4>;
 187                         interrupt-parent = <&gic>;
 188                         interrupt-controller;
 189                         reg = <0 0x0c000000 0 0x40000>,  /* GICD */
 190                               <0 0x0c100000 0 0x200000>, /* GICR */
 191                               <0 0x0c400000 0 0x2000>,   /* GICC */
 192                               <0 0x0c410000 0 0x1000>,   /* GICH */
 193                               <0 0x0c420000 0 0x2000>;   /* GICV */
 194
 195                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
 196                         ppi-partitions {
 197                                 ppi_cluster0: interrupt-partition-0 {
 198                                         affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
 199                                 };
 200                                 ppi_cluster1: interrupt-partition-1 {
 201                                         affinity = <&cpu4 &cpu5 &cpu6 &cpu7>;
 202                                 };
 203                         };
 204                 };
 205
 206                 mcucfg: syscon@c530000 {
 207                         compatible = "mediatek,mt8183-mcucfg", "syscon";
 208                         reg = <0 0x0c530000 0 0x1000>;
 209                         #clock-cells = <1>;
 210                 };
 211
 212                 sysirq: interrupt-controller@c530a80 {
 213                         compatible = "mediatek,mt8183-sysirq",
 214                                      "mediatek,mt6577-sysirq";
 215                         interrupt-controller;
 216                         #interrupt-cells = <3>;
 217                         interrupt-parent = <&gic>;
 218                         reg = <0 0x0c530a80 0 0x50>;
 219                 };
 220
 221                 topckgen: syscon@10000000 {
 222                         compatible = "mediatek,mt8183-topckgen", "syscon";
 223                         reg = <0 0x10000000 0 0x1000>;
 224                         #clock-cells = <1>;
 225                 };
 226
 227                 infracfg: syscon@10001000 {
 228                         compatible = "mediatek,mt8183-infracfg", "syscon";
 229                         reg = <0 0x10001000 0 0x1000>;
 230                         #clock-cells = <1>;
 231                         #reset-cells = <1>;
 232                 };
 233
 234                 pio: pinctrl@10005000 {
 235                         compatible = "mediatek,mt8183-pinctrl";
 236                         reg = <0 0x10005000 0 0x1000>,
 237                               <0 0x11f20000 0 0x1000>,
 238                               <0 0x11e80000 0 0x1000>,
 239                               <0 0x11e70000 0 0x1000>,
 240                               <0 0x11e90000 0 0x1000>,
 241                               <0 0x11d30000 0 0x1000>,
 242                               <0 0x11d20000 0 0x1000>,
 243                               <0 0x11c50000 0 0x1000>,
 244                               <0 0x11f30000 0 0x1000>,
 245                               <0 0x1000b000 0 0x1000>;
 246                         reg-names = "iocfg0", "iocfg1", "iocfg2",
 247                                     "iocfg3", "iocfg4", "iocfg5",
 248                                     "iocfg6", "iocfg7", "iocfg8",
 249                                     "eint";
 250                         gpio-controller;
 251                         #gpio-cells = <2>;
 252                         gpio-ranges = <&pio 0 0 192>;
 253                         interrupt-controller;
 254                         interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
 255                         #interrupt-cells = <2>;
 256                 };
 257
 258                 apmixedsys: syscon@1000c000 {
 259                         compatible = "mediatek,mt8183-apmixedsys", "syscon";
 260                         reg = <0 0x1000c000 0 0x1000>;
 261                         #clock-cells = <1>;
 262                 };
 263
 264                 pwrap: pwrap@1000d000 {
 265                         compatible = "mediatek,mt8183-pwrap";
 266                         reg = <0 0x1000d000 0 0x1000>;
 267                         reg-names = "pwrap";
 268                         interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
 269                         clocks = <&topckgen CLK_TOP_MUX_PMICSPI>,
 270                                  <&infracfg CLK_INFRA_PMIC_AP>;
 271                         clock-names = "spi", "wrap";
 272                 };
 273
 274                 systimer: timer@10017000 {
 275                         compatible = "mediatek,mt8183-timer",
 276                                      "mediatek,mt6765-timer";
 277                         reg = <0 0x10017000 0 0x1000>;
 278                         interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
 279                         clocks = <&topckgen CLK_TOP_CLK13M>;
 280                         clock-names = "clk13m";
 281                 };
 282
 283                 gce: mailbox@10238000 {
 284                         compatible = "mediatek,mt8183-gce";
 285                         reg = <0 0x10238000 0 0x4000>;
 286                         interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_LOW>;
 287                         #mbox-cells = <3>;
 288                         clocks = <&infracfg CLK_INFRA_GCE>;
 289                         clock-names = "gce";
 290                 };
 291
 292                 auxadc: auxadc@11001000 {
 293                         compatible = "mediatek,mt8183-auxadc",
 294                                      "mediatek,mt8173-auxadc";
 295                         reg = <0 0x11001000 0 0x1000>;
 296                         clocks = <&infracfg CLK_INFRA_AUXADC>;
 297                         clock-names = "main";
 298                         #io-channel-cells = <1>;
 299                         status = "disabled";
 300                 };
 301
 302                 uart0: serial@11002000 {
 303                         compatible = "mediatek,mt8183-uart",
 304                                      "mediatek,mt6577-uart";
 305                         reg = <0 0x11002000 0 0x1000>;
 306                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
 307                         clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>;
 308                         clock-names = "baud", "bus";
 309                         status = "disabled";
 310                 };
 311
 312                 uart1: serial@11003000 {
 313                         compatible = "mediatek,mt8183-uart",
 314                                      "mediatek,mt6577-uart";
 315                         reg = <0 0x11003000 0 0x1000>;
 316                         interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
 317                         clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>;
 318                         clock-names = "baud", "bus";
 319                         status = "disabled";
 320                 };
 321
 322                 uart2: serial@11004000 {
 323                         compatible = "mediatek,mt8183-uart",
 324                                      "mediatek,mt6577-uart";
 325                         reg = <0 0x11004000 0 0x1000>;
 326                         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
 327                         clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>;
 328                         clock-names = "baud", "bus";
 329                         status = "disabled";
 330                 };
 331
 332                 i2c6: i2c@11005000 {
 333                         compatible = "mediatek,mt8183-i2c";
 334                         reg = <0 0x11005000 0 0x1000>,
 335                               <0 0x11000600 0 0x80>;
 336                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
 337                         clocks = <&infracfg CLK_INFRA_I2C6>,
 338                                  <&infracfg CLK_INFRA_AP_DMA>;
 339                         clock-names = "main", "dma";
 340                         clock-div = <1>;
 341                         #address-cells = <1>;
 342                         #size-cells = <0>;
 343                         status = "disabled";
 344                 };
 345
 346                 i2c0: i2c@11007000 {
 347                         compatible = "mediatek,mt8183-i2c";
 348                         reg = <0 0x11007000 0 0x1000>,
 349                               <0 0x11000080 0 0x80>;
 350                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
 351                         clocks = <&infracfg CLK_INFRA_I2C0>,
 352                                  <&infracfg CLK_INFRA_AP_DMA>;
 353                         clock-names = "main", "dma";
 354                         clock-div = <1>;
 355                         #address-cells = <1>;
 356                         #size-cells = <0>;
 357                         status = "disabled";
 358                 };
 359
 360                 i2c4: i2c@11008000 {
 361                         compatible = "mediatek,mt8183-i2c";
 362                         reg = <0 0x11008000 0 0x1000>,
 363                               <0 0x11000100 0 0x80>;
 364                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>;
 365                         clocks = <&infracfg CLK_INFRA_I2C1>,
 366                                  <&infracfg CLK_INFRA_AP_DMA>,
 367                                  <&infracfg CLK_INFRA_I2C1_ARBITER>;
 368                         clock-names = "main", "dma","arb";
 369                         clock-div = <1>;
 370                         #address-cells = <1>;
 371                         #size-cells = <0>;
 372                         status = "disabled";
 373                 };
 374
 375                 i2c2: i2c@11009000 {
 376                         compatible = "mediatek,mt8183-i2c";
 377                         reg = <0 0x11009000 0 0x1000>,
 378                               <0 0x11000280 0 0x80>;
 379                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
 380                         clocks = <&infracfg CLK_INFRA_I2C2>,
 381                                  <&infracfg CLK_INFRA_AP_DMA>,
 382                                  <&infracfg CLK_INFRA_I2C2_ARBITER>;
 383                         clock-names = "main", "dma", "arb";
 384                         clock-div = <1>;
 385                         #address-cells = <1>;
 386                         #size-cells = <0>;
 387                         status = "disabled";
 388                 };
 389
 390                 spi0: spi@1100a000 {
 391                         compatible = "mediatek,mt8183-spi";
 392                         #address-cells = <1>;
 393                         #size-cells = <0>;
 394                         reg = <0 0x1100a000 0 0x1000>;
 395                         interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_LOW>;
 396                         clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
 397                                  <&topckgen CLK_TOP_MUX_SPI>,
 398                                  <&infracfg CLK_INFRA_SPI0>;
 399                         clock-names = "parent-clk", "sel-clk", "spi-clk";
 400                         status = "disabled";
 401                 };
 402
 403                 i2c3: i2c@1100f000 {
 404                         compatible = "mediatek,mt8183-i2c";
 405                         reg = <0 0x1100f000 0 0x1000>,
 406                               <0 0x11000400 0 0x80>;
 407                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
 408                         clocks = <&infracfg CLK_INFRA_I2C3>,
 409                                  <&infracfg CLK_INFRA_AP_DMA>;
 410                         clock-names = "main", "dma";
 411                         clock-div = <1>;
 412                         #address-cells = <1>;
 413                         #size-cells = <0>;
 414                         status = "disabled";
 415                 };
 416
 417                 spi1: spi@11010000 {
 418                         compatible = "mediatek,mt8183-spi";
 419                         #address-cells = <1>;
 420                         #size-cells = <0>;
 421                         reg = <0 0x11010000 0 0x1000>;
 422                         interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_LOW>;
 423                         clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
 424                                  <&topckgen CLK_TOP_MUX_SPI>,
 425                                  <&infracfg CLK_INFRA_SPI1>;
 426                         clock-names = "parent-clk", "sel-clk", "spi-clk";
 427                         status = "disabled";
 428                 };
 429
 430                 i2c1: i2c@11011000 {
 431                         compatible = "mediatek,mt8183-i2c";
 432                         reg = <0 0x11011000 0 0x1000>,
 433                               <0 0x11000480 0 0x80>;
 434                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
 435                         clocks = <&infracfg CLK_INFRA_I2C4>,
 436                                  <&infracfg CLK_INFRA_AP_DMA>;
 437                         clock-names = "main", "dma";
 438                         clock-div = <1>;
 439                         #address-cells = <1>;
 440                         #size-cells = <0>;
 441                         status = "disabled";
 442                 };
 443
 444                 spi2: spi@11012000 {
 445                         compatible = "mediatek,mt8183-spi";
 446                         #address-cells = <1>;
 447                         #size-cells = <0>;
 448                         reg = <0 0x11012000 0 0x1000>;
 449                         interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>;
 450                         clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
 451                                  <&topckgen CLK_TOP_MUX_SPI>,
 452                                  <&infracfg CLK_INFRA_SPI2>;
 453                         clock-names = "parent-clk", "sel-clk", "spi-clk";
 454                         status = "disabled";
 455                 };
 456
 457                 spi3: spi@11013000 {
 458                         compatible = "mediatek,mt8183-spi";
 459                         #address-cells = <1>;
 460                         #size-cells = <0>;
 461                         reg = <0 0x11013000 0 0x1000>;
 462                         interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_LOW>;
 463                         clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
 464                                  <&topckgen CLK_TOP_MUX_SPI>,
 465                                  <&infracfg CLK_INFRA_SPI3>;
 466                         clock-names = "parent-clk", "sel-clk", "spi-clk";
 467                         status = "disabled";
 468                 };
 469
 470                 i2c9: i2c@11014000 {
 471                         compatible = "mediatek,mt8183-i2c";
 472                         reg = <0 0x11014000 0 0x1000>,
 473                               <0 0x11000180 0 0x80>;
 474                         interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_LOW>;
 475                         clocks = <&infracfg CLK_INFRA_I2C1_IMM>,
 476                                  <&infracfg CLK_INFRA_AP_DMA>,
 477                                  <&infracfg CLK_INFRA_I2C1_ARBITER>;
 478                         clock-names = "main", "dma", "arb";
 479                         clock-div = <1>;
 480                         #address-cells = <1>;
 481                         #size-cells = <0>;
 482                         status = "disabled";
 483                 };
 484
 485                 i2c10: i2c@11015000 {
 486                         compatible = "mediatek,mt8183-i2c";
 487                         reg = <0 0x11015000 0 0x1000>,
 488                               <0 0x11000300 0 0x80>;
 489                         interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
 490                         clocks = <&infracfg CLK_INFRA_I2C2_IMM>,
 491                                  <&infracfg CLK_INFRA_AP_DMA>,
 492                                  <&infracfg CLK_INFRA_I2C2_ARBITER>;
 493                         clock-names = "main", "dma", "arb";
 494                         clock-div = <1>;
 495                         #address-cells = <1>;
 496                         #size-cells = <0>;
 497                         status = "disabled";
 498                 };
 499
 500                 i2c5: i2c@11016000 {
 501                         compatible = "mediatek,mt8183-i2c";
 502                         reg = <0 0x11016000 0 0x1000>,
 503                               <0 0x11000500 0 0x80>;
 504                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
 505                         clocks = <&infracfg CLK_INFRA_I2C5>,
 506                                  <&infracfg CLK_INFRA_AP_DMA>,
 507                                  <&infracfg CLK_INFRA_I2C5_ARBITER>;
 508                         clock-names = "main", "dma", "arb";
 509                         clock-div = <1>;
 510                         #address-cells = <1>;
 511                         #size-cells = <0>;
 512                         status = "disabled";
 513                 };
 514
 515                 i2c11: i2c@11017000 {
 516                         compatible = "mediatek,mt8183-i2c";
 517                         reg = <0 0x11017000 0 0x1000>,
 518                               <0 0x11000580 0 0x80>;
 519                         interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_LOW>;
 520                         clocks = <&infracfg CLK_INFRA_I2C5_IMM>,
 521                                  <&infracfg CLK_INFRA_AP_DMA>,
 522                                  <&infracfg CLK_INFRA_I2C5_ARBITER>;
 523                         clock-names = "main", "dma", "arb";
 524                         clock-div = <1>;
 525                         #address-cells = <1>;
 526                         #size-cells = <0>;
 527                         status = "disabled";
 528                 };
 529
 530                 spi4: spi@11018000 {
 531                         compatible = "mediatek,mt8183-spi";
 532                         #address-cells = <1>;
 533                         #size-cells = <0>;
 534                         reg = <0 0x11018000 0 0x1000>;
 535                         interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_LOW>;
 536                         clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
 537                                  <&topckgen CLK_TOP_MUX_SPI>,
 538                                  <&infracfg CLK_INFRA_SPI4>;
 539                         clock-names = "parent-clk", "sel-clk", "spi-clk";
 540                         status = "disabled";
 541                 };
 542
 543                 spi5: spi@11019000 {
 544                         compatible = "mediatek,mt8183-spi";
 545                         #address-cells = <1>;
 546                         #size-cells = <0>;
 547                         reg = <0 0x11019000 0 0x1000>;
 548                         interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>;
 549                         clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>,
 550                                  <&topckgen CLK_TOP_MUX_SPI>,
 551                                  <&infracfg CLK_INFRA_SPI5>;
 552                         clock-names = "parent-clk", "sel-clk", "spi-clk";
 553                         status = "disabled";
 554                 };
 555
 556                 i2c7: i2c@1101a000 {
 557                         compatible = "mediatek,mt8183-i2c";
 558                         reg = <0 0x1101a000 0 0x1000>,
 559                               <0 0x11000680 0 0x80>;
 560                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>;
 561                         clocks = <&infracfg CLK_INFRA_I2C7>,
 562                                  <&infracfg CLK_INFRA_AP_DMA>;
 563                         clock-names = "main", "dma";
 564                         clock-div = <1>;
 565                         #address-cells = <1>;
 566                         #size-cells = <0>;
 567                         status = "disabled";
 568                 };
 569
 570                 i2c8: i2c@1101b000 {
 571                         compatible = "mediatek,mt8183-i2c";
 572                         reg = <0 0x1101b000 0 0x1000>,
 573                               <0 0x11000700 0 0x80>;
 574                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>;
 575                         clocks = <&infracfg CLK_INFRA_I2C8>,
 576                                  <&infracfg CLK_INFRA_AP_DMA>;
 577                         clock-names = "main", "dma";
 578                         clock-div = <1>;
 579                         #address-cells = <1>;
 580                         #size-cells = <0>;
 581                         status = "disabled";
 582                 };
 583
 584                 audiosys: syscon@11220000 {
 585                         compatible = "mediatek,mt8183-audiosys", "syscon";
 586                         reg = <0 0x11220000 0 0x1000>;
 587                         #clock-cells = <1>;
 588                 };
 589
 590                 efuse: efuse@11f10000 {
 591                         compatible = "mediatek,mt8183-efuse",
 592                                      "mediatek,efuse";
 593                         reg = <0 0x11f10000 0 0x1000>;
 594                 };
 595
 596                 mfgcfg: syscon@13000000 {
 597                         compatible = "mediatek,mt8183-mfgcfg", "syscon";
 598                         reg = <0 0x13000000 0 0x1000>;
 599                         #clock-cells = <1>;
 600                 };
 601
 602                 mmsys: syscon@14000000 {
 603                         compatible = "mediatek,mt8183-mmsys", "syscon";
 604                         reg = <0 0x14000000 0 0x1000>;
 605                         #clock-cells = <1>;
 606                 };
 607
 608                 imgsys: syscon@15020000 {
 609                         compatible = "mediatek,mt8183-imgsys", "syscon";
 610                         reg = <0 0x15020000 0 0x1000>;
 611                         #clock-cells = <1>;
 612                 };
 613
 614                 vdecsys: syscon@16000000 {
 615                         compatible = "mediatek,mt8183-vdecsys", "syscon";
 616                         reg = <0 0x16000000 0 0x1000>;
 617                         #clock-cells = <1>;
 618                 };
 619
 620                 vencsys: syscon@17000000 {
 621                         compatible = "mediatek,mt8183-vencsys", "syscon";
 622                         reg = <0 0x17000000 0 0x1000>;
 623                         #clock-cells = <1>;
 624                 };
 625
 626                 ipu_conn: syscon@19000000 {
 627                         compatible = "mediatek,mt8183-ipu_conn", "syscon";
 628                         reg = <0 0x19000000 0 0x1000>;
 629                         #clock-cells = <1>;
 630                 };
 631
 632                 ipu_adl: syscon@19010000 {
 633                         compatible = "mediatek,mt8183-ipu_adl", "syscon";
 634                         reg = <0 0x19010000 0 0x1000>;
 635                         #clock-cells = <1>;
 636                 };
 637
 638                 ipu_core0: syscon@19180000 {
 639                         compatible = "mediatek,mt8183-ipu_core0", "syscon";
 640                         reg = <0 0x19180000 0 0x1000>;
 641                         #clock-cells = <1>;
 642                 };
 643
 644                 ipu_core1: syscon@19280000 {
 645                         compatible = "mediatek,mt8183-ipu_core1", "syscon";
 646                         reg = <0 0x19280000 0 0x1000>;
 647                         #clock-cells = <1>;
 648                 };
 649
 650                 camsys: syscon@1a000000 {
 651                         compatible = "mediatek,mt8183-camsys", "syscon";
 652                         reg = <0 0x1a000000 0 0x1000>;
 653                         #clock-cells = <1>;
 654                 };
 655         };
 656 };