1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra124-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra124-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/thermal/tegra124-soctherm.h>
11 compatible = "nvidia,tegra132", "nvidia,tegra124";
12 interrupt-parent = <&lic>;
17 compatible = "nvidia,tegra124-pcie";
19 reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
20 0x0 0x01003800 0x0 0x00000800 /* AFI registers */
21 0x0 0x02000000 0x0 0x10000000>; /* configuration space */
22 reg-names = "pads", "afi", "cs";
23 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
24 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
25 interrupt-names = "intr", "msi";
27 #interrupt-cells = <1>;
28 interrupt-map-mask = <0 0 0 0>;
29 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
31 bus-range = <0x00 0xff>;
35 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */
36 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */
37 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */
38 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */
39 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
41 clocks = <&tegra_car TEGRA124_CLK_PCIE>,
42 <&tegra_car TEGRA124_CLK_AFI>,
43 <&tegra_car TEGRA124_CLK_PLL_E>,
44 <&tegra_car TEGRA124_CLK_CML0>;
45 clock-names = "pex", "afi", "pll_e", "cml";
46 resets = <&tegra_car 70>,
49 reset-names = "pex", "afi", "pcie_x";
52 phys = <&padctl TEGRA_XUSB_PADCTL_PCIE>;
57 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
58 reg = <0x000800 0 0 0 0>;
59 bus-range = <0x00 0xff>;
66 nvidia,num-lanes = <2>;
71 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
72 reg = <0x001000 0 0 0 0>;
73 bus-range = <0x00 0xff>;
80 nvidia,num-lanes = <1>;
85 compatible = "nvidia,tegra124-host1x", "simple-bus";
86 reg = <0x0 0x50000000 0x0 0x00034000>;
87 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
88 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
89 clocks = <&tegra_car TEGRA124_CLK_HOST1X>;
90 clock-names = "host1x";
91 resets = <&tegra_car 28>;
92 reset-names = "host1x";
97 ranges = <0 0x54000000 0 0x54000000 0 0x01000000>;
100 compatible = "nvidia,tegra124-dc";
101 reg = <0x0 0x54200000 0x0 0x00040000>;
102 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
103 clocks = <&tegra_car TEGRA124_CLK_DISP1>,
104 <&tegra_car TEGRA124_CLK_PLL_P>;
105 clock-names = "dc", "parent";
106 resets = <&tegra_car 27>;
109 iommus = <&mc TEGRA_SWGROUP_DC>;
115 compatible = "nvidia,tegra124-dc";
116 reg = <0x0 0x54240000 0x0 0x00040000>;
117 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
118 clocks = <&tegra_car TEGRA124_CLK_DISP2>,
119 <&tegra_car TEGRA124_CLK_PLL_P>;
120 clock-names = "dc", "parent";
121 resets = <&tegra_car 26>;
124 iommus = <&mc TEGRA_SWGROUP_DCB>;
130 compatible = "nvidia,tegra124-hdmi";
131 reg = <0x0 0x54280000 0x0 0x00040000>;
132 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
133 clocks = <&tegra_car TEGRA124_CLK_HDMI>,
134 <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>;
135 clock-names = "hdmi", "parent";
136 resets = <&tegra_car 51>;
137 reset-names = "hdmi";
142 compatible = "nvidia,tegra124-sor";
143 reg = <0x0 0x54540000 0x0 0x00040000>;
144 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
145 clocks = <&tegra_car TEGRA124_CLK_SOR0>,
146 <&tegra_car TEGRA124_CLK_PLL_D_OUT0>,
147 <&tegra_car TEGRA124_CLK_PLL_DP>,
148 <&tegra_car TEGRA124_CLK_CLK_M>;
149 clock-names = "sor", "parent", "dp", "safe";
150 resets = <&tegra_car 182>;
155 dpaux: dpaux@545c0000 {
156 compatible = "nvidia,tegra124-dpaux";
157 reg = <0x0 0x545c0000 0x0 0x00040000>;
158 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
159 clocks = <&tegra_car TEGRA124_CLK_DPAUX>,
160 <&tegra_car TEGRA124_CLK_PLL_DP>;
161 clock-names = "dpaux", "parent";
162 resets = <&tegra_car 181>;
163 reset-names = "dpaux";
168 gic: interrupt-controller@50041000 {
169 compatible = "arm,cortex-a15-gic";
170 #interrupt-cells = <3>;
171 interrupt-controller;
172 reg = <0x0 0x50041000 0x0 0x1000>,
173 <0x0 0x50042000 0x0 0x2000>,
174 <0x0 0x50044000 0x0 0x2000>,
175 <0x0 0x50046000 0x0 0x2000>;
176 interrupts = <GIC_PPI 9
177 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
178 interrupt-parent = <&gic>;
182 compatible = "nvidia,gk20a";
183 reg = <0x0 0x57000000 0x0 0x01000000>,
184 <0x0 0x58000000 0x0 0x01000000>;
185 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
186 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
187 interrupt-names = "stall", "nonstall";
188 clocks = <&tegra_car TEGRA124_CLK_GPU>,
189 <&tegra_car TEGRA124_CLK_PLL_P_OUT5>;
190 clock-names = "gpu", "pwr";
191 resets = <&tegra_car 184>;
196 lic: interrupt-controller@60004000 {
197 compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr";
198 reg = <0x0 0x60004000 0x0 0x100>,
199 <0x0 0x60004100 0x0 0x100>,
200 <0x0 0x60004200 0x0 0x100>,
201 <0x0 0x60004300 0x0 0x100>,
202 <0x0 0x60004400 0x0 0x100>;
203 interrupt-controller;
204 #interrupt-cells = <3>;
205 interrupt-parent = <&gic>;
209 compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer";
210 reg = <0x0 0x60005000 0x0 0x400>;
211 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
212 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
213 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
214 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
215 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
216 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
217 clocks = <&tegra_car TEGRA124_CLK_TIMER>;
218 clock-names = "timer";
221 tegra_car: clock@60006000 {
222 compatible = "nvidia,tegra132-car";
223 reg = <0x0 0x60006000 0x0 0x1000>;
226 nvidia,external-memory-controller = <&emc>;
229 flow-controller@60007000 {
230 compatible = "nvidia,tegra132-flowctrl", "nvidia,tegra124-flowctrl";
231 reg = <0x0 0x60007000 0x0 0x1000>;
235 compatible = "nvidia,tegra124-actmon";
236 reg = <0x0 0x6000c800 0x0 0x400>;
237 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
238 clocks = <&tegra_car TEGRA124_CLK_ACTMON>,
239 <&tegra_car TEGRA124_CLK_EMC>;
240 clock-names = "actmon", "emc";
241 resets = <&tegra_car 119>;
242 reset-names = "actmon";
245 gpio: gpio@6000d000 {
246 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
247 reg = <0x0 0x6000d000 0x0 0x1000>;
248 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
249 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
250 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
251 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
252 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
253 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
254 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
255 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
258 #interrupt-cells = <2>;
259 interrupt-controller;
262 apbdma: dma@60020000 {
263 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
264 reg = <0x0 0x60020000 0x0 0x1400>;
265 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
266 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
267 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
268 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
269 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
270 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
271 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
272 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
273 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
274 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
275 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
276 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
277 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
278 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
279 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
280 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
281 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
282 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
283 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
284 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
285 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
286 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
287 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
288 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
289 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
290 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
291 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
292 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
293 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
294 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
295 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
296 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
297 clocks = <&tegra_car TEGRA124_CLK_APBDMA>;
299 resets = <&tegra_car 34>;
305 compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc";
306 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */
307 <0x0 0x7000e864 0x0 0x04>; /* Strapping options */
310 pinmux: pinmux@70000868 {
311 compatible = "nvidia,tegra124-pinmux";
312 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
313 <0x0 0x70003000 0x0 0x434>, /* Mux registers */
314 <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */
318 * There are two serial driver i.e. 8250 based simple serial
319 * driver and APB DMA based serial driver for higher baudrate
320 * and performance. To enable the 8250 based driver, the compatible
321 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
322 * the APB DMA based serial driver, the compatible is
323 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
325 uarta: serial@70006000 {
326 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
327 reg = <0x0 0x70006000 0x0 0x40>;
329 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
330 clocks = <&tegra_car TEGRA124_CLK_UARTA>;
331 clock-names = "serial";
332 resets = <&tegra_car 6>;
333 reset-names = "serial";
334 dmas = <&apbdma 8>, <&apbdma 8>;
335 dma-names = "rx", "tx";
339 uartb: serial@70006040 {
340 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
341 reg = <0x0 0x70006040 0x0 0x40>;
343 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
344 clocks = <&tegra_car TEGRA124_CLK_UARTB>;
345 clock-names = "serial";
346 resets = <&tegra_car 7>;
347 reset-names = "serial";
348 dmas = <&apbdma 9>, <&apbdma 9>;
349 dma-names = "rx", "tx";
353 uartc: serial@70006200 {
354 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
355 reg = <0x0 0x70006200 0x0 0x40>;
357 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
358 clocks = <&tegra_car TEGRA124_CLK_UARTC>;
359 clock-names = "serial";
360 resets = <&tegra_car 55>;
361 reset-names = "serial";
362 dmas = <&apbdma 10>, <&apbdma 10>;
363 dma-names = "rx", "tx";
367 uartd: serial@70006300 {
368 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
369 reg = <0x0 0x70006300 0x0 0x40>;
371 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
372 clocks = <&tegra_car TEGRA124_CLK_UARTD>;
373 clock-names = "serial";
374 resets = <&tegra_car 65>;
375 reset-names = "serial";
376 dmas = <&apbdma 19>, <&apbdma 19>;
377 dma-names = "rx", "tx";
382 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
383 reg = <0x0 0x7000a000 0x0 0x100>;
385 clocks = <&tegra_car TEGRA124_CLK_PWM>;
387 resets = <&tegra_car 17>;
393 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
394 reg = <0x0 0x7000c000 0x0 0x100>;
395 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
396 #address-cells = <1>;
398 clocks = <&tegra_car TEGRA124_CLK_I2C1>;
399 clock-names = "div-clk";
400 resets = <&tegra_car 12>;
402 dmas = <&apbdma 21>, <&apbdma 21>;
403 dma-names = "rx", "tx";
408 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
409 reg = <0x0 0x7000c400 0x0 0x100>;
410 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
411 #address-cells = <1>;
413 clocks = <&tegra_car TEGRA124_CLK_I2C2>;
414 clock-names = "div-clk";
415 resets = <&tegra_car 54>;
417 dmas = <&apbdma 22>, <&apbdma 22>;
418 dma-names = "rx", "tx";
423 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
424 reg = <0x0 0x7000c500 0x0 0x100>;
425 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
426 #address-cells = <1>;
428 clocks = <&tegra_car TEGRA124_CLK_I2C3>;
429 clock-names = "div-clk";
430 resets = <&tegra_car 67>;
432 dmas = <&apbdma 23>, <&apbdma 23>;
433 dma-names = "rx", "tx";
438 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
439 reg = <0x0 0x7000c700 0x0 0x100>;
440 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
441 #address-cells = <1>;
443 clocks = <&tegra_car TEGRA124_CLK_I2C4>;
444 clock-names = "div-clk";
445 resets = <&tegra_car 103>;
447 dmas = <&apbdma 26>, <&apbdma 26>;
448 dma-names = "rx", "tx";
453 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
454 reg = <0x0 0x7000d000 0x0 0x100>;
455 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
456 #address-cells = <1>;
458 clocks = <&tegra_car TEGRA124_CLK_I2C5>;
459 clock-names = "div-clk";
460 resets = <&tegra_car 47>;
462 dmas = <&apbdma 24>, <&apbdma 24>;
463 dma-names = "rx", "tx";
468 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
469 reg = <0x0 0x7000d100 0x0 0x100>;
470 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
471 #address-cells = <1>;
473 clocks = <&tegra_car TEGRA124_CLK_I2C6>;
474 clock-names = "div-clk";
475 resets = <&tegra_car 166>;
477 dmas = <&apbdma 30>, <&apbdma 30>;
478 dma-names = "rx", "tx";
483 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
484 reg = <0x0 0x7000d400 0x0 0x200>;
485 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
486 #address-cells = <1>;
488 clocks = <&tegra_car TEGRA124_CLK_SBC1>;
490 resets = <&tegra_car 41>;
492 dmas = <&apbdma 15>, <&apbdma 15>;
493 dma-names = "rx", "tx";
498 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
499 reg = <0x0 0x7000d600 0x0 0x200>;
500 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
501 #address-cells = <1>;
503 clocks = <&tegra_car TEGRA124_CLK_SBC2>;
505 resets = <&tegra_car 44>;
507 dmas = <&apbdma 16>, <&apbdma 16>;
508 dma-names = "rx", "tx";
513 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
514 reg = <0x0 0x7000d800 0x0 0x200>;
515 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
516 #address-cells = <1>;
518 clocks = <&tegra_car TEGRA124_CLK_SBC3>;
520 resets = <&tegra_car 46>;
522 dmas = <&apbdma 17>, <&apbdma 17>;
523 dma-names = "rx", "tx";
528 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
529 reg = <0x0 0x7000da00 0x0 0x200>;
530 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
531 #address-cells = <1>;
533 clocks = <&tegra_car TEGRA124_CLK_SBC4>;
535 resets = <&tegra_car 68>;
537 dmas = <&apbdma 18>, <&apbdma 18>;
538 dma-names = "rx", "tx";
543 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
544 reg = <0x0 0x7000dc00 0x0 0x200>;
545 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
546 #address-cells = <1>;
548 clocks = <&tegra_car TEGRA124_CLK_SBC5>;
550 resets = <&tegra_car 104>;
552 dmas = <&apbdma 27>, <&apbdma 27>;
553 dma-names = "rx", "tx";
558 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
559 reg = <0x0 0x7000de00 0x0 0x200>;
560 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
561 #address-cells = <1>;
563 clocks = <&tegra_car TEGRA124_CLK_SBC6>;
565 resets = <&tegra_car 105>;
567 dmas = <&apbdma 28>, <&apbdma 28>;
568 dma-names = "rx", "tx";
573 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
574 reg = <0x0 0x7000e000 0x0 0x100>;
575 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
576 clocks = <&tegra_car TEGRA124_CLK_RTC>;
581 compatible = "nvidia,tegra124-pmc";
582 reg = <0x0 0x7000e400 0x0 0x400>;
583 clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
584 clock-names = "pclk", "clk32k_in";
588 compatible = "nvidia,tegra124-efuse";
589 reg = <0x0 0x7000f800 0x0 0x400>;
590 clocks = <&tegra_car TEGRA124_CLK_FUSE>;
591 clock-names = "fuse";
592 resets = <&tegra_car 39>;
593 reset-names = "fuse";
596 mc: memory-controller@70019000 {
597 compatible = "nvidia,tegra132-mc";
598 reg = <0x0 0x70019000 0x0 0x1000>;
599 clocks = <&tegra_car TEGRA124_CLK_MC>;
602 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
607 emc: external-memory-controller@7001b000 {
608 compatible = "nvidia,tegra132-emc", "nvidia,tegra124-emc";
609 reg = <0x0 0x7001b000 0x0 0x1000>;
610 clocks = <&tegra_car TEGRA124_CLK_EMC>;
613 nvidia,memory-controller = <&mc>;
617 compatible = "nvidia,tegra124-ahci";
618 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
619 <0x0 0x70020000 0x0 0x7000>; /* SATA */
620 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
621 clocks = <&tegra_car TEGRA124_CLK_SATA>,
622 <&tegra_car TEGRA124_CLK_SATA_OOB>,
623 <&tegra_car TEGRA124_CLK_CML1>,
624 <&tegra_car TEGRA124_CLK_PLL_E>;
625 clock-names = "sata", "sata-oob", "cml1", "pll_e";
626 resets = <&tegra_car 124>,
629 reset-names = "sata", "sata-oob", "sata-cold";
630 phys = <&padctl TEGRA_XUSB_PADCTL_SATA>;
631 phy-names = "sata-phy";
636 compatible = "nvidia,tegra132-hda", "nvidia,tegra124-hda",
637 "nvidia,tegra30-hda";
638 reg = <0x0 0x70030000 0x0 0x10000>;
639 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
640 clocks = <&tegra_car TEGRA124_CLK_HDA>,
641 <&tegra_car TEGRA124_CLK_HDA2HDMI>,
642 <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>;
643 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
644 resets = <&tegra_car 125>, /* hda */
645 <&tegra_car 128>, /* hda2hdmi */
646 <&tegra_car 111>; /* hda2codec_2x */
647 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
651 padctl: padctl@7009f000 {
652 compatible = "nvidia,tegra132-xusb-padctl",
653 "nvidia,tegra124-xusb-padctl";
654 reg = <0x0 0x7009f000 0x0 0x1000>;
655 resets = <&tegra_car 142>;
656 reset-names = "padctl";
692 compatible = "nvidia,tegra124-sdhci";
693 reg = <0x0 0x700b0000 0x0 0x200>;
694 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
695 clocks = <&tegra_car TEGRA124_CLK_SDMMC1>;
696 clock-names = "sdhci";
697 resets = <&tegra_car 14>;
698 reset-names = "sdhci";
703 compatible = "nvidia,tegra124-sdhci";
704 reg = <0x0 0x700b0200 0x0 0x200>;
705 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
706 clocks = <&tegra_car TEGRA124_CLK_SDMMC2>;
707 clock-names = "sdhci";
708 resets = <&tegra_car 9>;
709 reset-names = "sdhci";
714 compatible = "nvidia,tegra124-sdhci";
715 reg = <0x0 0x700b0400 0x0 0x200>;
716 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
717 clocks = <&tegra_car TEGRA124_CLK_SDMMC3>;
718 clock-names = "sdhci";
719 resets = <&tegra_car 69>;
720 reset-names = "sdhci";
725 compatible = "nvidia,tegra124-sdhci";
726 reg = <0x0 0x700b0600 0x0 0x200>;
727 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
728 clocks = <&tegra_car TEGRA124_CLK_SDMMC4>;
729 clock-names = "sdhci";
730 resets = <&tegra_car 15>;
731 reset-names = "sdhci";
735 soctherm: thermal-sensor@700e2000 {
736 compatible = "nvidia,tegra132-soctherm";
737 reg = <0x0 0x700e2000 0x0 0x600 /* 0: SOC_THERM reg_base */
738 0x0 0x70040000 0x0 0x200>; /* 2: CCROC reg_base */
739 reg-names = "soctherm-reg", "ccroc-reg";
740 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
741 clocks = <&tegra_car TEGRA124_CLK_TSENSOR>,
742 <&tegra_car TEGRA124_CLK_SOC_THERM>;
743 clock-names = "tsensor", "soctherm";
744 resets = <&tegra_car 78>;
745 reset-names = "soctherm";
746 #thermal-sensor-cells = <1>;
749 throttle_heavy: heavy {
750 nvidia,priority = <100>;
751 nvidia,cpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>;
753 #cooling-cells = <2>;
760 polling-delay-passive = <1000>;
764 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
768 temperature = <105000>;
773 cpu_throttle_trip: throttle-trip {
774 temperature = <102000>;
782 trip = <&cpu_throttle_trip>;
783 cooling-device = <&throttle_heavy 1 1>;
788 polling-delay-passive = <0>;
792 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>;
796 temperature = <101000>;
804 * There are currently no cooling maps,
805 * because there are no cooling devices.
810 polling-delay-passive = <1000>;
814 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>;
818 temperature = <101000>;
823 gpu_throttle_trip: throttle-trip {
824 temperature = <99000>;
832 trip = <&gpu_throttle_trip>;
833 cooling-device = <&throttle_heavy 1 1>;
838 polling-delay-passive = <0>;
842 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>;
846 temperature = <105000>;
854 * There are currently no cooling maps,
855 * because there are no cooling devices.
862 compatible = "nvidia,tegra124-ahub";
863 reg = <0x0 0x70300000 0x0 0x200>,
864 <0x0 0x70300800 0x0 0x800>,
865 <0x0 0x70300200 0x0 0x600>;
866 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
867 clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>,
868 <&tegra_car TEGRA124_CLK_APBIF>;
869 clock-names = "d_audio", "apbif";
870 resets = <&tegra_car 106>, /* d_audio */
871 <&tegra_car 107>, /* apbif */
872 <&tegra_car 30>, /* i2s0 */
873 <&tegra_car 11>, /* i2s1 */
874 <&tegra_car 18>, /* i2s2 */
875 <&tegra_car 101>, /* i2s3 */
876 <&tegra_car 102>, /* i2s4 */
877 <&tegra_car 108>, /* dam0 */
878 <&tegra_car 109>, /* dam1 */
879 <&tegra_car 110>, /* dam2 */
880 <&tegra_car 10>, /* spdif */
881 <&tegra_car 153>, /* amx */
882 <&tegra_car 185>, /* amx1 */
883 <&tegra_car 154>, /* adx */
884 <&tegra_car 180>, /* adx1 */
885 <&tegra_car 186>, /* afc0 */
886 <&tegra_car 187>, /* afc1 */
887 <&tegra_car 188>, /* afc2 */
888 <&tegra_car 189>, /* afc3 */
889 <&tegra_car 190>, /* afc4 */
890 <&tegra_car 191>; /* afc5 */
891 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
892 "i2s3", "i2s4", "dam0", "dam1", "dam2",
893 "spdif", "amx", "amx1", "adx", "adx1",
894 "afc0", "afc1", "afc2", "afc3", "afc4", "afc5";
895 dmas = <&apbdma 1>, <&apbdma 1>,
896 <&apbdma 2>, <&apbdma 2>,
897 <&apbdma 3>, <&apbdma 3>,
898 <&apbdma 4>, <&apbdma 4>,
899 <&apbdma 6>, <&apbdma 6>,
900 <&apbdma 7>, <&apbdma 7>,
901 <&apbdma 12>, <&apbdma 12>,
902 <&apbdma 13>, <&apbdma 13>,
903 <&apbdma 14>, <&apbdma 14>,
904 <&apbdma 29>, <&apbdma 29>;
905 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
906 "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
907 "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
910 #address-cells = <2>;
913 tegra_i2s0: i2s@70301000 {
914 compatible = "nvidia,tegra124-i2s";
915 reg = <0x0 0x70301000 0x0 0x100>;
916 nvidia,ahub-cif-ids = <4 4>;
917 clocks = <&tegra_car TEGRA124_CLK_I2S0>;
919 resets = <&tegra_car 30>;
924 tegra_i2s1: i2s@70301100 {
925 compatible = "nvidia,tegra124-i2s";
926 reg = <0x0 0x70301100 0x0 0x100>;
927 nvidia,ahub-cif-ids = <5 5>;
928 clocks = <&tegra_car TEGRA124_CLK_I2S1>;
930 resets = <&tegra_car 11>;
935 tegra_i2s2: i2s@70301200 {
936 compatible = "nvidia,tegra124-i2s";
937 reg = <0x0 0x70301200 0x0 0x100>;
938 nvidia,ahub-cif-ids = <6 6>;
939 clocks = <&tegra_car TEGRA124_CLK_I2S2>;
941 resets = <&tegra_car 18>;
946 tegra_i2s3: i2s@70301300 {
947 compatible = "nvidia,tegra124-i2s";
948 reg = <0x0 0x70301300 0x0 0x100>;
949 nvidia,ahub-cif-ids = <7 7>;
950 clocks = <&tegra_car TEGRA124_CLK_I2S3>;
952 resets = <&tegra_car 101>;
957 tegra_i2s4: i2s@70301400 {
958 compatible = "nvidia,tegra124-i2s";
959 reg = <0x0 0x70301400 0x0 0x100>;
960 nvidia,ahub-cif-ids = <8 8>;
961 clocks = <&tegra_car TEGRA124_CLK_I2S4>;
963 resets = <&tegra_car 102>;
970 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
971 reg = <0x0 0x7d000000 0x0 0x4000>;
972 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
974 clocks = <&tegra_car TEGRA124_CLK_USBD>;
976 resets = <&tegra_car 22>;
978 nvidia,phy = <&phy1>;
982 phy1: usb-phy@7d000000 {
983 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
984 reg = <0x0 0x7d000000 0x0 0x4000>,
985 <0x0 0x7d000000 0x0 0x4000>;
987 clocks = <&tegra_car TEGRA124_CLK_USBD>,
988 <&tegra_car TEGRA124_CLK_PLL_U>,
989 <&tegra_car TEGRA124_CLK_USBD>;
990 clock-names = "reg", "pll_u", "utmi-pads";
991 resets = <&tegra_car 22>, <&tegra_car 22>;
992 reset-names = "usb", "utmi-pads";
993 nvidia,hssync-start-delay = <0>;
994 nvidia,idle-wait-delay = <17>;
995 nvidia,elastic-limit = <16>;
996 nvidia,term-range-adj = <6>;
997 nvidia,xcvr-setup = <9>;
998 nvidia,xcvr-lsfslew = <0>;
999 nvidia,xcvr-lsrslew = <3>;
1000 nvidia,hssquelch-level = <2>;
1001 nvidia,hsdiscon-level = <5>;
1002 nvidia,xcvr-hsslew = <12>;
1003 nvidia,has-utmi-pad-registers;
1004 status = "disabled";
1008 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1009 reg = <0x0 0x7d004000 0x0 0x4000>;
1010 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1012 clocks = <&tegra_car TEGRA124_CLK_USB2>;
1013 clock-names = "usb";
1014 resets = <&tegra_car 58>;
1015 reset-names = "usb";
1016 nvidia,phy = <&phy2>;
1017 status = "disabled";
1020 phy2: usb-phy@7d004000 {
1021 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
1022 reg = <0x0 0x7d004000 0x0 0x4000>,
1023 <0x0 0x7d000000 0x0 0x4000>;
1025 clocks = <&tegra_car TEGRA124_CLK_USB2>,
1026 <&tegra_car TEGRA124_CLK_PLL_U>,
1027 <&tegra_car TEGRA124_CLK_USBD>;
1028 clock-names = "reg", "pll_u", "utmi-pads";
1029 resets = <&tegra_car 58>, <&tegra_car 22>;
1030 reset-names = "usb", "utmi-pads";
1031 nvidia,hssync-start-delay = <0>;
1032 nvidia,idle-wait-delay = <17>;
1033 nvidia,elastic-limit = <16>;
1034 nvidia,term-range-adj = <6>;
1035 nvidia,xcvr-setup = <9>;
1036 nvidia,xcvr-lsfslew = <0>;
1037 nvidia,xcvr-lsrslew = <3>;
1038 nvidia,hssquelch-level = <2>;
1039 nvidia,hsdiscon-level = <5>;
1040 nvidia,xcvr-hsslew = <12>;
1041 status = "disabled";
1045 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1046 reg = <0x0 0x7d008000 0x0 0x4000>;
1047 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1049 clocks = <&tegra_car TEGRA124_CLK_USB3>;
1050 clock-names = "usb";
1051 resets = <&tegra_car 59>;
1052 reset-names = "usb";
1053 nvidia,phy = <&phy3>;
1054 status = "disabled";
1057 phy3: usb-phy@7d008000 {
1058 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
1059 reg = <0x0 0x7d008000 0x0 0x4000>,
1060 <0x0 0x7d000000 0x0 0x4000>;
1062 clocks = <&tegra_car TEGRA124_CLK_USB3>,
1063 <&tegra_car TEGRA124_CLK_PLL_U>,
1064 <&tegra_car TEGRA124_CLK_USBD>;
1065 clock-names = "reg", "pll_u", "utmi-pads";
1066 resets = <&tegra_car 59>, <&tegra_car 22>;
1067 reset-names = "usb", "utmi-pads";
1068 nvidia,hssync-start-delay = <0>;
1069 nvidia,idle-wait-delay = <17>;
1070 nvidia,elastic-limit = <16>;
1071 nvidia,term-range-adj = <6>;
1072 nvidia,xcvr-setup = <9>;
1073 nvidia,xcvr-lsfslew = <0>;
1074 nvidia,xcvr-lsrslew = <3>;
1075 nvidia,hssquelch-level = <2>;
1076 nvidia,hsdiscon-level = <5>;
1077 nvidia,xcvr-hsslew = <12>;
1078 status = "disabled";
1082 #address-cells = <1>;
1086 device_type = "cpu";
1087 compatible = "nvidia,denver";
1092 device_type = "cpu";
1093 compatible = "nvidia,denver";
1099 compatible = "arm,armv7-timer";
1100 interrupts = <GIC_PPI 13
1101 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1103 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1105 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1107 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1108 interrupt-parent = <&gic>;