sys/gnu/dts/arm64/nvidia/tegra186.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include <dt-bindings/clock/tegra186-clock.h>
   3 #include <dt-bindings/gpio/tegra186-gpio.h>
   4 #include <dt-bindings/interrupt-controller/arm-gic.h>
   5 #include <dt-bindings/mailbox/tegra186-hsp.h>
   6 #include <dt-bindings/memory/tegra186-mc.h>
   7 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
   8 #include <dt-bindings/power/tegra186-powergate.h>
   9 #include <dt-bindings/reset/tegra186-reset.h>
  10 #include <dt-bindings/thermal/tegra186-bpmp-thermal.h>
  11
  12 / {
  13         compatible = "nvidia,tegra186";
  14         interrupt-parent = <&gic>;
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         misc@100000 {
  19                 compatible = "nvidia,tegra186-misc";
  20                 reg = <0x0 0x00100000 0x0 0xf000>,
  21                       <0x0 0x0010f000 0x0 0x1000>;
  22         };
  23
  24         gpio: gpio@2200000 {
  25                 compatible = "nvidia,tegra186-gpio";
  26                 reg-names = "security", "gpio";
  27                 reg = <0x0 0x2200000 0x0 0x10000>,
  28                       <0x0 0x2210000 0x0 0x10000>;
  29                 interrupts = <GIC_SPI  47 IRQ_TYPE_LEVEL_HIGH>,
  30                              <GIC_SPI  50 IRQ_TYPE_LEVEL_HIGH>,
  31                              <GIC_SPI  53 IRQ_TYPE_LEVEL_HIGH>,
  32                              <GIC_SPI  56 IRQ_TYPE_LEVEL_HIGH>,
  33                              <GIC_SPI  59 IRQ_TYPE_LEVEL_HIGH>,
  34                              <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
  35                 #interrupt-cells = <2>;
  36                 interrupt-controller;
  37                 #gpio-cells = <2>;
  38                 gpio-controller;
  39         };
  40
  41         ethernet@2490000 {
  42                 compatible = "nvidia,tegra186-eqos",
  43                              "snps,dwc-qos-ethernet-4.10";
  44                 reg = <0x0 0x02490000 0x0 0x10000>;
  45                 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */
  46                              <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */
  47                              <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */
  48                              <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */
  49                              <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */
  50                              <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */
  51                              <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */
  52                              <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */
  53                              <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */
  54                              <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */
  55                 clocks = <&bpmp TEGRA186_CLK_AXI_CBB>,
  56                          <&bpmp TEGRA186_CLK_EQOS_AXI>,
  57                          <&bpmp TEGRA186_CLK_EQOS_RX>,
  58                          <&bpmp TEGRA186_CLK_EQOS_TX>,
  59                          <&bpmp TEGRA186_CLK_EQOS_PTP_REF>;
  60                 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
  61                 resets = <&bpmp TEGRA186_RESET_EQOS>;
  62                 reset-names = "eqos";
  63                 iommus = <&smmu TEGRA186_SID_EQOS>;
  64                 status = "disabled";
  65
  66                 snps,write-requests = <1>;
  67                 snps,read-requests = <3>;
  68                 snps,burst-map = <0x7>;
  69                 snps,txpbl = <32>;
  70                 snps,rxpbl = <8>;
  71         };
  72
  73         aconnect {
  74                 compatible = "nvidia,tegra186-aconnect",
  75                              "nvidia,tegra210-aconnect";
  76                 clocks = <&bpmp TEGRA186_CLK_APE>,
  77                          <&bpmp TEGRA186_CLK_APB2APE>;
  78                 clock-names = "ape", "apb2ape";
  79                 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_AUD>;
  80                 #address-cells = <1>;
  81                 #size-cells = <1>;
  82                 ranges = <0x02900000 0x0 0x02900000 0x200000>;
  83                 status = "disabled";
  84
  85                 dma-controller@2930000 {
  86                         compatible = "nvidia,tegra186-adma";
  87                         reg = <0x02930000 0x20000>;
  88                         interrupt-parent = <&agic>;
  89                         interrupts =  <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
  90                                       <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
  91                                       <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
  92                                       <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
  93                                       <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
  94                                       <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
  95                                       <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
  96                                       <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
  97                                       <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
  98                                       <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
  99                                       <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
 100                                       <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 101                                       <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 102                                       <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 103                                       <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 104                                       <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 105                                       <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 106                                       <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
 107                                       <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 108                                       <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 109                                       <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
 110                                       <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
 111                                       <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
 112                                       <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
 113                                       <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
 114                                       <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
 115                                       <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
 116                                       <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
 117                                       <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
 118                                       <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
 119                                       <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
 120                                       <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 121                         #dma-cells = <1>;
 122                         clocks = <&bpmp TEGRA186_CLK_AHUB>;
 123                         clock-names = "d_audio";
 124                         status = "disabled";
 125                 };
 126
 127                 agic: interrupt-controller@2a40000 {
 128                         compatible = "nvidia,tegra186-agic",
 129                                      "nvidia,tegra210-agic";
 130                         #interrupt-cells = <3>;
 131                         interrupt-controller;
 132                         reg = <0x02a41000 0x1000>,
 133                               <0x02a42000 0x2000>;
 134                         interrupts = <GIC_SPI 145
 135                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 136                         clocks = <&bpmp TEGRA186_CLK_APE>;
 137                         clock-names = "clk";
 138                         status = "disabled";
 139                 };
 140         };
 141
 142         memory-controller@2c00000 {
 143                 compatible = "nvidia,tegra186-mc";
 144                 reg = <0x0 0x02c00000 0x0 0xb0000>;
 145                 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
 146                 status = "disabled";
 147
 148                 #address-cells = <2>;
 149                 #size-cells = <2>;
 150
 151                 ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>;
 152
 153                 /*
 154                  * Memory clients have access to all 40 bits that the memory
 155                  * controller can address.
 156                  */
 157                 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
 158
 159                 emc: external-memory-controller@2c60000 {
 160                         compatible = "nvidia,tegra186-emc";
 161                         reg = <0x0 0x02c60000 0x0 0x50000>;
 162                         interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
 163                         clocks = <&bpmp TEGRA186_CLK_EMC>;
 164                         clock-names = "emc";
 165
 166                         nvidia,bpmp = <&bpmp>;
 167                 };
 168         };
 169
 170         uarta: serial@3100000 {
 171                 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
 172                 reg = <0x0 0x03100000 0x0 0x40>;
 173                 reg-shift = <2>;
 174                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 175                 clocks = <&bpmp TEGRA186_CLK_UARTA>;
 176                 clock-names = "serial";
 177                 resets = <&bpmp TEGRA186_RESET_UARTA>;
 178                 reset-names = "serial";
 179                 status = "disabled";
 180         };
 181
 182         uartb: serial@3110000 {
 183                 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
 184                 reg = <0x0 0x03110000 0x0 0x40>;
 185                 reg-shift = <2>;
 186                 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 187                 clocks = <&bpmp TEGRA186_CLK_UARTB>;
 188                 clock-names = "serial";
 189                 resets = <&bpmp TEGRA186_RESET_UARTB>;
 190                 reset-names = "serial";
 191                 status = "disabled";
 192         };
 193
 194         uartd: serial@3130000 {
 195                 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
 196                 reg = <0x0 0x03130000 0x0 0x40>;
 197                 reg-shift = <2>;
 198                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 199                 clocks = <&bpmp TEGRA186_CLK_UARTD>;
 200                 clock-names = "serial";
 201                 resets = <&bpmp TEGRA186_RESET_UARTD>;
 202                 reset-names = "serial";
 203                 status = "disabled";
 204         };
 205
 206         uarte: serial@3140000 {
 207                 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
 208                 reg = <0x0 0x03140000 0x0 0x40>;
 209                 reg-shift = <2>;
 210                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 211                 clocks = <&bpmp TEGRA186_CLK_UARTE>;
 212                 clock-names = "serial";
 213                 resets = <&bpmp TEGRA186_RESET_UARTE>;
 214                 reset-names = "serial";
 215                 status = "disabled";
 216         };
 217
 218         uartf: serial@3150000 {
 219                 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
 220                 reg = <0x0 0x03150000 0x0 0x40>;
 221                 reg-shift = <2>;
 222                 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 223                 clocks = <&bpmp TEGRA186_CLK_UARTF>;
 224                 clock-names = "serial";
 225                 resets = <&bpmp TEGRA186_RESET_UARTF>;
 226                 reset-names = "serial";
 227                 status = "disabled";
 228         };
 229
 230         gen1_i2c: i2c@3160000 {
 231                 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
 232                 reg = <0x0 0x03160000 0x0 0x10000>;
 233                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 234                 #address-cells = <1>;
 235                 #size-cells = <0>;
 236                 clocks = <&bpmp TEGRA186_CLK_I2C1>;
 237                 clock-names = "div-clk";
 238                 resets = <&bpmp TEGRA186_RESET_I2C1>;
 239                 reset-names = "i2c";
 240                 status = "disabled";
 241         };
 242
 243         cam_i2c: i2c@3180000 {
 244                 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
 245                 reg = <0x0 0x03180000 0x0 0x10000>;
 246                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 247                 #address-cells = <1>;
 248                 #size-cells = <0>;
 249                 clocks = <&bpmp TEGRA186_CLK_I2C3>;
 250                 clock-names = "div-clk";
 251                 resets = <&bpmp TEGRA186_RESET_I2C3>;
 252                 reset-names = "i2c";
 253                 status = "disabled";
 254         };
 255
 256         /* shares pads with dpaux1 */
 257         dp_aux_ch1_i2c: i2c@3190000 {
 258                 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
 259                 reg = <0x0 0x03190000 0x0 0x10000>;
 260                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 261                 #address-cells = <1>;
 262                 #size-cells = <0>;
 263                 clocks = <&bpmp TEGRA186_CLK_I2C4>;
 264                 clock-names = "div-clk";
 265                 resets = <&bpmp TEGRA186_RESET_I2C4>;
 266                 reset-names = "i2c";
 267                 pinctrl-names = "default", "idle";
 268                 pinctrl-0 = <&state_dpaux1_i2c>;
 269                 pinctrl-1 = <&state_dpaux1_off>;
 270                 status = "disabled";
 271         };
 272
 273         /* controlled by BPMP, should not be enabled */
 274         pwr_i2c: i2c@31a0000 {
 275                 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
 276                 reg = <0x0 0x031a0000 0x0 0x10000>;
 277                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 278                 #address-cells = <1>;
 279                 #size-cells = <0>;
 280                 clocks = <&bpmp TEGRA186_CLK_I2C5>;
 281                 clock-names = "div-clk";
 282                 resets = <&bpmp TEGRA186_RESET_I2C5>;
 283                 reset-names = "i2c";
 284                 status = "disabled";
 285         };
 286
 287         /* shares pads with dpaux0 */
 288         dp_aux_ch0_i2c: i2c@31b0000 {
 289                 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
 290                 reg = <0x0 0x031b0000 0x0 0x10000>;
 291                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 292                 #address-cells = <1>;
 293                 #size-cells = <0>;
 294                 clocks = <&bpmp TEGRA186_CLK_I2C6>;
 295                 clock-names = "div-clk";
 296                 resets = <&bpmp TEGRA186_RESET_I2C6>;
 297                 reset-names = "i2c";
 298                 pinctrl-names = "default", "idle";
 299                 pinctrl-0 = <&state_dpaux_i2c>;
 300                 pinctrl-1 = <&state_dpaux_off>;
 301                 status = "disabled";
 302         };
 303
 304         gen7_i2c: i2c@31c0000 {
 305                 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
 306                 reg = <0x0 0x031c0000 0x0 0x10000>;
 307                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 308                 #address-cells = <1>;
 309                 #size-cells = <0>;
 310                 clocks = <&bpmp TEGRA186_CLK_I2C7>;
 311                 clock-names = "div-clk";
 312                 resets = <&bpmp TEGRA186_RESET_I2C7>;
 313                 reset-names = "i2c";
 314                 status = "disabled";
 315         };
 316
 317         gen9_i2c: i2c@31e0000 {
 318                 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
 319                 reg = <0x0 0x031e0000 0x0 0x10000>;
 320                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 321                 #address-cells = <1>;
 322                 #size-cells = <0>;
 323                 clocks = <&bpmp TEGRA186_CLK_I2C9>;
 324                 clock-names = "div-clk";
 325                 resets = <&bpmp TEGRA186_RESET_I2C9>;
 326                 reset-names = "i2c";
 327                 status = "disabled";
 328         };
 329
 330         sdmmc1: sdhci@3400000 {
 331                 compatible = "nvidia,tegra186-sdhci";
 332                 reg = <0x0 0x03400000 0x0 0x10000>;
 333                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 334                 clocks = <&bpmp TEGRA186_CLK_SDMMC1>;
 335                 clock-names = "sdhci";
 336                 resets = <&bpmp TEGRA186_RESET_SDMMC1>;
 337                 reset-names = "sdhci";
 338                 iommus = <&smmu TEGRA186_SID_SDMMC1>;
 339                 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
 340                 pinctrl-0 = <&sdmmc1_3v3>;
 341                 pinctrl-1 = <&sdmmc1_1v8>;
 342                 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
 343                 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
 344                 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
 345                 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
 346                 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x03>;
 347                 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x05>;
 348                 nvidia,default-tap = <0x5>;
 349                 nvidia,default-trim = <0xb>;
 350                 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC1>,
 351                                   <&bpmp TEGRA186_CLK_PLLP_OUT0>;
 352                 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>;
 353                 status = "disabled";
 354         };
 355
 356         sdmmc2: sdhci@3420000 {
 357                 compatible = "nvidia,tegra186-sdhci";
 358                 reg = <0x0 0x03420000 0x0 0x10000>;
 359                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 360                 clocks = <&bpmp TEGRA186_CLK_SDMMC2>;
 361                 clock-names = "sdhci";
 362                 resets = <&bpmp TEGRA186_RESET_SDMMC2>;
 363                 reset-names = "sdhci";
 364                 iommus = <&smmu TEGRA186_SID_SDMMC2>;
 365                 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
 366                 pinctrl-0 = <&sdmmc2_3v3>;
 367                 pinctrl-1 = <&sdmmc2_1v8>;
 368                 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
 369                 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
 370                 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
 371                 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
 372                 nvidia,default-tap = <0x5>;
 373                 nvidia,default-trim = <0xb>;
 374                 status = "disabled";
 375         };
 376
 377         sdmmc3: sdhci@3440000 {
 378                 compatible = "nvidia,tegra186-sdhci";
 379                 reg = <0x0 0x03440000 0x0 0x10000>;
 380                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 381                 clocks = <&bpmp TEGRA186_CLK_SDMMC3>;
 382                 clock-names = "sdhci";
 383                 resets = <&bpmp TEGRA186_RESET_SDMMC3>;
 384                 reset-names = "sdhci";
 385                 iommus = <&smmu TEGRA186_SID_SDMMC3>;
 386                 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
 387                 pinctrl-0 = <&sdmmc3_3v3>;
 388                 pinctrl-1 = <&sdmmc3_1v8>;
 389                 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
 390                 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
 391                 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
 392                 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x06>;
 393                 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x07>;
 394                 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
 395                 nvidia,default-tap = <0x5>;
 396                 nvidia,default-trim = <0xb>;
 397                 status = "disabled";
 398         };
 399
 400         sdmmc4: sdhci@3460000 {
 401                 compatible = "nvidia,tegra186-sdhci";
 402                 reg = <0x0 0x03460000 0x0 0x10000>;
 403                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 404                 clocks = <&bpmp TEGRA186_CLK_SDMMC4>;
 405                 clock-names = "sdhci";
 406                 assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>,
 407                                   <&bpmp TEGRA186_CLK_PLLC4_VCO>;
 408                 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLC4_VCO>;
 409                 resets = <&bpmp TEGRA186_RESET_SDMMC4>;
 410                 reset-names = "sdhci";
 411                 iommus = <&smmu TEGRA186_SID_SDMMC4>;
 412                 nvidia,pad-autocal-pull-up-offset-hs400 = <0x05>;
 413                 nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>;
 414                 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
 415                 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>;
 416                 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
 417                 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>;
 418                 nvidia,default-tap = <0x9>;
 419                 nvidia,default-trim = <0x5>;
 420                 nvidia,dqs-trim = <63>;
 421                 mmc-hs400-1_8v;
 422                 supports-cqe;
 423                 status = "disabled";
 424         };
 425
 426         hda@3510000 {
 427                 compatible = "nvidia,tegra186-hda", "nvidia,tegra30-hda";
 428                 reg = <0x0 0x03510000 0x0 0x10000>;
 429                 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
 430                 clocks = <&bpmp TEGRA186_CLK_HDA>,
 431                          <&bpmp TEGRA186_CLK_HDA2HDMICODEC>,
 432                          <&bpmp TEGRA186_CLK_HDA2CODEC_2X>;
 433                 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
 434                 resets = <&bpmp TEGRA186_RESET_HDA>,
 435                          <&bpmp TEGRA186_RESET_HDA2HDMICODEC>,
 436                          <&bpmp TEGRA186_RESET_HDA2CODEC_2X>;
 437                 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
 438                 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
 439                 iommus = <&smmu TEGRA186_SID_HDA>;
 440                 status = "disabled";
 441         };
 442
 443         padctl: padctl@3520000 {
 444                 compatible = "nvidia,tegra186-xusb-padctl";
 445                 reg = <0x0 0x03520000 0x0 0x1000>,
 446                       <0x0 0x03540000 0x0 0x1000>;
 447                 reg-names = "padctl", "ao";
 448
 449                 resets = <&bpmp TEGRA186_RESET_XUSB_PADCTL>;
 450                 reset-names = "padctl";
 451
 452                 status = "disabled";
 453
 454                 pads {
 455                         usb2 {
 456                                 clocks = <&bpmp TEGRA186_CLK_USB2_TRK>;
 457                                 clock-names = "trk";
 458                                 status = "disabled";
 459
 460                                 lanes {
 461                                         usb2-0 {
 462                                                 status = "disabled";
 463                                                 #phy-cells = <0>;
 464                                         };
 465
 466                                         usb2-1 {
 467                                                 status = "disabled";
 468                                                 #phy-cells = <0>;
 469                                         };
 470
 471                                         usb2-2 {
 472                                                 status = "disabled";
 473                                                 #phy-cells = <0>;
 474                                         };
 475                                 };
 476                         };
 477
 478                         hsic {
 479                                 clocks = <&bpmp TEGRA186_CLK_HSIC_TRK>;
 480                                 clock-names = "trk";
 481                                 status = "disabled";
 482
 483                                 lanes {
 484                                         hsic-0 {
 485                                                 status = "disabled";
 486                                                 #phy-cells = <0>;
 487                                         };
 488                                 };
 489                         };
 490
 491                         usb3 {
 492                                 status = "disabled";
 493
 494                                 lanes {
 495                                         usb3-0 {
 496                                                 status = "disabled";
 497                                                 #phy-cells = <0>;
 498                                         };
 499
 500                                         usb3-1 {
 501                                                 status = "disabled";
 502                                                 #phy-cells = <0>;
 503                                         };
 504
 505                                         usb3-2 {
 506                                                 status = "disabled";
 507                                                 #phy-cells = <0>;
 508                                         };
 509                                 };
 510                         };
 511                 };
 512
 513                 ports {
 514                         usb2-0 {
 515                                 status = "disabled";
 516                         };
 517
 518                         usb2-1 {
 519                                 status = "disabled";
 520                         };
 521
 522                         usb2-2 {
 523                                 status = "disabled";
 524                         };
 525
 526                         hsic-0 {
 527                                 status = "disabled";
 528                         };
 529
 530                         usb3-0 {
 531                                 status = "disabled";
 532                         };
 533
 534                         usb3-1 {
 535                                 status = "disabled";
 536                         };
 537
 538                         usb3-2 {
 539                                 status = "disabled";
 540                         };
 541                 };
 542         };
 543
 544         usb@3530000 {
 545                 compatible = "nvidia,tegra186-xusb";
 546                 reg = <0x0 0x03530000 0x0 0x8000>,
 547                       <0x0 0x03538000 0x0 0x1000>;
 548                 reg-names = "hcd", "fpci";
 549                 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
 550                              <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
 551                              <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
 552                 clocks = <&bpmp TEGRA186_CLK_XUSB_HOST>,
 553                          <&bpmp TEGRA186_CLK_XUSB_FALCON>,
 554                          <&bpmp TEGRA186_CLK_XUSB_SS>,
 555                          <&bpmp TEGRA186_CLK_XUSB_CORE_SS>,
 556                          <&bpmp TEGRA186_CLK_CLK_M>,
 557                          <&bpmp TEGRA186_CLK_XUSB_FS>,
 558                          <&bpmp TEGRA186_CLK_PLLU>,
 559                          <&bpmp TEGRA186_CLK_CLK_M>,
 560                          <&bpmp TEGRA186_CLK_PLLE>;
 561                 clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss",
 562                               "xusb_ss_src", "xusb_hs_src", "xusb_fs_src",
 563                               "pll_u_480m", "clk_m", "pll_e";
 564                 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>,
 565                                 <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>;
 566                 power-domain-names = "xusb_host", "xusb_ss";
 567                 iommus = <&smmu TEGRA186_SID_XUSB_HOST>;
 568                 #address-cells = <1>;
 569                 #size-cells = <0>;
 570                 status = "disabled";
 571
 572                 nvidia,xusb-padctl = <&padctl>;
 573         };
 574
 575         fuse@3820000 {
 576                 compatible = "nvidia,tegra186-efuse";
 577                 reg = <0x0 0x03820000 0x0 0x10000>;
 578                 clocks = <&bpmp TEGRA186_CLK_FUSE>;
 579                 clock-names = "fuse";
 580         };
 581
 582         gic: interrupt-controller@3881000 {
 583                 compatible = "arm,gic-400";
 584                 #interrupt-cells = <3>;
 585                 interrupt-controller;
 586                 reg = <0x0 0x03881000 0x0 0x1000>,
 587                       <0x0 0x03882000 0x0 0x2000>;
 588                 interrupts = <GIC_PPI 9
 589                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 590                 interrupt-parent = <&gic>;
 591         };
 592
 593         cec@3960000 {
 594                 compatible = "nvidia,tegra186-cec";
 595                 reg = <0x0 0x03960000 0x0 0x10000>;
 596                 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
 597                 clocks = <&bpmp TEGRA186_CLK_CEC>;
 598                 clock-names = "cec";
 599                 status = "disabled";
 600         };
 601
 602         hsp_top0: hsp@3c00000 {
 603                 compatible = "nvidia,tegra186-hsp";
 604                 reg = <0x0 0x03c00000 0x0 0xa0000>;
 605                 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
 606                 interrupt-names = "doorbell";
 607                 #mbox-cells = <2>;
 608                 status = "disabled";
 609         };
 610
 611         gen2_i2c: i2c@c240000 {
 612                 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
 613                 reg = <0x0 0x0c240000 0x0 0x10000>;
 614                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 615                 #address-cells = <1>;
 616                 #size-cells = <0>;
 617                 clocks = <&bpmp TEGRA186_CLK_I2C2>;
 618                 clock-names = "div-clk";
 619                 resets = <&bpmp TEGRA186_RESET_I2C2>;
 620                 reset-names = "i2c";
 621                 status = "disabled";
 622         };
 623
 624         gen8_i2c: i2c@c250000 {
 625                 compatible = "nvidia,tegra186-i2c", "nvidia,tegra210-i2c";
 626                 reg = <0x0 0x0c250000 0x0 0x10000>;
 627                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 628                 #address-cells = <1>;
 629                 #size-cells = <0>;
 630                 clocks = <&bpmp TEGRA186_CLK_I2C8>;
 631                 clock-names = "div-clk";
 632                 resets = <&bpmp TEGRA186_RESET_I2C8>;
 633                 reset-names = "i2c";
 634                 status = "disabled";
 635         };
 636
 637         uartc: serial@c280000 {
 638                 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
 639                 reg = <0x0 0x0c280000 0x0 0x40>;
 640                 reg-shift = <2>;
 641                 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 642                 clocks = <&bpmp TEGRA186_CLK_UARTC>;
 643                 clock-names = "serial";
 644                 resets = <&bpmp TEGRA186_RESET_UARTC>;
 645                 reset-names = "serial";
 646                 status = "disabled";
 647         };
 648
 649         uartg: serial@c290000 {
 650                 compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
 651                 reg = <0x0 0x0c290000 0x0 0x40>;
 652                 reg-shift = <2>;
 653                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
 654                 clocks = <&bpmp TEGRA186_CLK_UARTG>;
 655                 clock-names = "serial";
 656                 resets = <&bpmp TEGRA186_RESET_UARTG>;
 657                 reset-names = "serial";
 658                 status = "disabled";
 659         };
 660
 661         rtc: rtc@c2a0000 {
 662                 compatible = "nvidia,tegra186-rtc", "nvidia,tegra20-rtc";
 663                 reg = <0 0x0c2a0000 0 0x10000>;
 664                 interrupt-parent = <&pmc>;
 665                 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>;
 666                 clocks = <&bpmp TEGRA186_CLK_CLK_32K>;
 667                 clock-names = "rtc";
 668                 status = "disabled";
 669         };
 670
 671         gpio_aon: gpio@c2f0000 {
 672                 compatible = "nvidia,tegra186-gpio-aon";
 673                 reg-names = "security", "gpio";
 674                 reg = <0x0 0xc2f0000 0x0 0x1000>,
 675                       <0x0 0xc2f1000 0x0 0x1000>;
 676                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 677                 gpio-controller;
 678                 #gpio-cells = <2>;
 679                 interrupt-controller;
 680                 #interrupt-cells = <2>;
 681         };
 682
 683         pmc: pmc@c360000 {
 684                 compatible = "nvidia,tegra186-pmc";
 685                 reg = <0 0x0c360000 0 0x10000>,
 686                       <0 0x0c370000 0 0x10000>,
 687                       <0 0x0c380000 0 0x10000>,
 688                       <0 0x0c390000 0 0x10000>;
 689                 reg-names = "pmc", "wake", "aotag", "scratch";
 690
 691                 #interrupt-cells = <2>;
 692                 interrupt-controller;
 693
 694                 sdmmc1_3v3: sdmmc1-3v3 {
 695                         pins = "sdmmc1-hv";
 696                         power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
 697                 };
 698
 699                 sdmmc1_1v8: sdmmc1-1v8 {
 700                         pins = "sdmmc1-hv";
 701                         power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
 702                 };
 703
 704                 sdmmc2_3v3: sdmmc2-3v3 {
 705                         pins = "sdmmc2-hv";
 706                         power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
 707                 };
 708
 709                 sdmmc2_1v8: sdmmc2-1v8 {
 710                         pins = "sdmmc2-hv";
 711                         power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
 712                 };
 713
 714                 sdmmc3_3v3: sdmmc3-3v3 {
 715                         pins = "sdmmc3-hv";
 716                         power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
 717                 };
 718
 719                 sdmmc3_1v8: sdmmc3-1v8 {
 720                         pins = "sdmmc3-hv";
 721                         power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
 722                 };
 723         };
 724
 725         ccplex@e000000 {
 726                 compatible = "nvidia,tegra186-ccplex-cluster";
 727                 reg = <0x0 0x0e000000 0x0 0x3fffff>;
 728
 729                 nvidia,bpmp = <&bpmp>;
 730         };
 731
 732         pcie@10003000 {
 733                 compatible = "nvidia,tegra186-pcie";
 734                 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>;
 735                 device_type = "pci";
 736                 reg = <0x0 0x10003000 0x0 0x00000800   /* PADS registers */
 737                        0x0 0x10003800 0x0 0x00000800   /* AFI registers */
 738                        0x0 0x40000000 0x0 0x10000000>; /* configuration space */
 739                 reg-names = "pads", "afi", "cs";
 740
 741                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
 742                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
 743                 interrupt-names = "intr", "msi";
 744
 745                 #interrupt-cells = <1>;
 746                 interrupt-map-mask = <0 0 0 0>;
 747                 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 748
 749                 bus-range = <0x00 0xff>;
 750                 #address-cells = <3>;
 751                 #size-cells = <2>;
 752
 753                 ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000   /* port 0 configuration space */
 754                           0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000   /* port 1 configuration space */
 755                           0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000   /* port 2 configuration space */
 756                           0x81000000 0 0x0        0x0 0x50000000 0 0x00010000   /* downstream I/O (64 KiB) */
 757                           0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000   /* non-prefetchable memory (127 MiB) */
 758                           0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */
 759
 760                 clocks = <&bpmp TEGRA186_CLK_AFI>,
 761                          <&bpmp TEGRA186_CLK_PCIE>,
 762                          <&bpmp TEGRA186_CLK_PLLE>;
 763                 clock-names = "afi", "pex", "pll_e";
 764
 765                 resets = <&bpmp TEGRA186_RESET_AFI>,
 766                          <&bpmp TEGRA186_RESET_PCIE>,
 767                          <&bpmp TEGRA186_RESET_PCIEXCLK>;
 768                 reset-names = "afi", "pex", "pcie_x";
 769
 770                 iommus = <&smmu TEGRA186_SID_AFI>;
 771                 iommu-map = <0x0 &smmu TEGRA186_SID_AFI 0x1000>;
 772                 iommu-map-mask = <0x0>;
 773
 774                 status = "disabled";
 775
 776                 pci@1,0 {
 777                         device_type = "pci";
 778                         assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>;
 779                         reg = <0x000800 0 0 0 0>;
 780                         status = "disabled";
 781
 782                         #address-cells = <3>;
 783                         #size-cells = <2>;
 784                         ranges;
 785
 786                         nvidia,num-lanes = <2>;
 787                 };
 788
 789                 pci@2,0 {
 790                         device_type = "pci";
 791                         assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>;
 792                         reg = <0x001000 0 0 0 0>;
 793                         status = "disabled";
 794
 795                         #address-cells = <3>;
 796                         #size-cells = <2>;
 797                         ranges;
 798
 799                         nvidia,num-lanes = <1>;
 800                 };
 801
 802                 pci@3,0 {
 803                         device_type = "pci";
 804                         assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>;
 805                         reg = <0x001800 0 0 0 0>;
 806                         status = "disabled";
 807
 808                         #address-cells = <3>;
 809                         #size-cells = <2>;
 810                         ranges;
 811
 812                         nvidia,num-lanes = <1>;
 813                 };
 814         };
 815
 816         smmu: iommu@12000000 {
 817                 compatible = "arm,mmu-500";
 818                 reg = <0 0x12000000 0 0x800000>;
 819                 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 820                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 821                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 822                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 823                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 824                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 825                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 826                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 827                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 828                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 829                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 830                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 831                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 832                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 833                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 834                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 835                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 836                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 837                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 838                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 839                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 840                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 841                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 842                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 843                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 844                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 845                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 846                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 847                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 848                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 849                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 850                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 851                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 852                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 853                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 854                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 855                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 856                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 857                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 858                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 859                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 860                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 861                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 862                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 863                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 864                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 865                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 866                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 867                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 868                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 869                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 870                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 871                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 872                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 873                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 874                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 875                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 876                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 877                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 878                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 879                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 880                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 881                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 882                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
 883                              <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
 884                 stream-match-mask = <0x7f80>;
 885                 #global-interrupts = <1>;
 886                 #iommu-cells = <1>;
 887         };
 888
 889         host1x@13e00000 {
 890                 compatible = "nvidia,tegra186-host1x", "simple-bus";
 891                 reg = <0x0 0x13e00000 0x0 0x10000>,
 892                       <0x0 0x13e10000 0x0 0x10000>;
 893                 reg-names = "hypervisor", "vm";
 894                 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
 895                              <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
 896                 clocks = <&bpmp TEGRA186_CLK_HOST1X>;
 897                 clock-names = "host1x";
 898                 resets = <&bpmp TEGRA186_RESET_HOST1X>;
 899                 reset-names = "host1x";
 900
 901                 #address-cells = <1>;
 902                 #size-cells = <1>;
 903
 904                 ranges = <0x15000000 0x0 0x15000000 0x01000000>;
 905                 iommus = <&smmu TEGRA186_SID_HOST1X>;
 906
 907                 dpaux1: dpaux@15040000 {
 908                         compatible = "nvidia,tegra186-dpaux";
 909                         reg = <0x15040000 0x10000>;
 910                         interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
 911                         clocks = <&bpmp TEGRA186_CLK_DPAUX1>,
 912                                  <&bpmp TEGRA186_CLK_PLLDP>;
 913                         clock-names = "dpaux", "parent";
 914                         resets = <&bpmp TEGRA186_RESET_DPAUX1>;
 915                         reset-names = "dpaux";
 916                         status = "disabled";
 917
 918                         power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
 919
 920                         state_dpaux1_aux: pinmux-aux {
 921                                 groups = "dpaux-io";
 922                                 function = "aux";
 923                         };
 924
 925                         state_dpaux1_i2c: pinmux-i2c {
 926                                 groups = "dpaux-io";
 927                                 function = "i2c";
 928                         };
 929
 930                         state_dpaux1_off: pinmux-off {
 931                                 groups = "dpaux-io";
 932                                 function = "off";
 933                         };
 934
 935                         i2c-bus {
 936                                 #address-cells = <1>;
 937                                 #size-cells = <0>;
 938                         };
 939                 };
 940
 941                 display-hub@15200000 {
 942                         compatible = "nvidia,tegra186-display", "simple-bus";
 943                         reg = <0x15200000 0x00040000>;
 944                         resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>,
 945                                  <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>,
 946                                  <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>,
 947                                  <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>,
 948                                  <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>,
 949                                  <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>,
 950                                  <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>;
 951                         reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
 952                                       "wgrp3", "wgrp4", "wgrp5";
 953                         clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>,
 954                                  <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>,
 955                                  <&bpmp TEGRA186_CLK_NVDISPLAYHUB>;
 956                         clock-names = "disp", "dsc", "hub";
 957                         status = "disabled";
 958
 959                         power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
 960
 961                         #address-cells = <1>;
 962                         #size-cells = <1>;
 963
 964                         ranges = <0x15200000 0x15200000 0x40000>;
 965
 966                         display@15200000 {
 967                                 compatible = "nvidia,tegra186-dc";
 968                                 reg = <0x15200000 0x10000>;
 969                                 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 970                                 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>;
 971                                 clock-names = "dc";
 972                                 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>;
 973                                 reset-names = "dc";
 974
 975                                 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
 976                                 iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
 977
 978                                 nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
 979                                 nvidia,head = <0>;
 980                         };
 981
 982                         display@15210000 {
 983                                 compatible = "nvidia,tegra186-dc";
 984                                 reg = <0x15210000 0x10000>;
 985                                 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 986                                 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>;
 987                                 clock-names = "dc";
 988                                 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>;
 989                                 reset-names = "dc";
 990
 991                                 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>;
 992                                 iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
 993
 994                                 nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
 995                                 nvidia,head = <1>;
 996                         };
 997
 998                         display@15220000 {
 999                                 compatible = "nvidia,tegra186-dc";
1000                                 reg = <0x15220000 0x10000>;
1001                                 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
1002                                 clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>;
1003                                 clock-names = "dc";
1004                                 resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>;
1005                                 reset-names = "dc";
1006
1007                                 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>;
1008                                 iommus = <&smmu TEGRA186_SID_NVDISPLAY>;
1009
1010                                 nvidia,outputs = <&sor0 &sor1>;
1011                                 nvidia,head = <2>;
1012                         };
1013                 };
1014
1015                 dsia: dsi@15300000 {
1016                         compatible = "nvidia,tegra186-dsi";
1017                         reg = <0x15300000 0x10000>;
1018                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1019                         clocks = <&bpmp TEGRA186_CLK_DSI>,
1020                                  <&bpmp TEGRA186_CLK_DSIA_LP>,
1021                                  <&bpmp TEGRA186_CLK_PLLD>;
1022                         clock-names = "dsi", "lp", "parent";
1023                         resets = <&bpmp TEGRA186_RESET_DSI>;
1024                         reset-names = "dsi";
1025                         status = "disabled";
1026
1027                         power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1028                 };
1029
1030                 vic@15340000 {
1031                         compatible = "nvidia,tegra186-vic";
1032                         reg = <0x15340000 0x40000>;
1033                         interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
1034                         clocks = <&bpmp TEGRA186_CLK_VIC>;
1035                         clock-names = "vic";
1036                         resets = <&bpmp TEGRA186_RESET_VIC>;
1037                         reset-names = "vic";
1038
1039                         power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>;
1040                         iommus = <&smmu TEGRA186_SID_VIC>;
1041                 };
1042
1043                 dsib: dsi@15400000 {
1044                         compatible = "nvidia,tegra186-dsi";
1045                         reg = <0x15400000 0x10000>;
1046                         interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1047                         clocks = <&bpmp TEGRA186_CLK_DSIB>,
1048                                  <&bpmp TEGRA186_CLK_DSIB_LP>,
1049                                  <&bpmp TEGRA186_CLK_PLLD>;
1050                         clock-names = "dsi", "lp", "parent";
1051                         resets = <&bpmp TEGRA186_RESET_DSIB>;
1052                         reset-names = "dsi";
1053                         status = "disabled";
1054
1055                         power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1056                 };
1057
1058                 sor0: sor@15540000 {
1059                         compatible = "nvidia,tegra186-sor";
1060                         reg = <0x15540000 0x10000>;
1061                         interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1062                         clocks = <&bpmp TEGRA186_CLK_SOR0>,
1063                                  <&bpmp TEGRA186_CLK_SOR0_OUT>,
1064                                  <&bpmp TEGRA186_CLK_PLLD2>,
1065                                  <&bpmp TEGRA186_CLK_PLLDP>,
1066                                  <&bpmp TEGRA186_CLK_SOR_SAFE>,
1067                                  <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>;
1068                         clock-names = "sor", "out", "parent", "dp", "safe",
1069                                       "pad";
1070                         resets = <&bpmp TEGRA186_RESET_SOR0>;
1071                         reset-names = "sor";
1072                         pinctrl-0 = <&state_dpaux_aux>;
1073                         pinctrl-1 = <&state_dpaux_i2c>;
1074                         pinctrl-2 = <&state_dpaux_off>;
1075                         pinctrl-names = "aux", "i2c", "off";
1076                         status = "disabled";
1077
1078                         power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1079                         nvidia,interface = <0>;
1080                 };
1081
1082                 sor1: sor@15580000 {
1083                         compatible = "nvidia,tegra186-sor";
1084                         reg = <0x15580000 0x10000>;
1085                         interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1086                         clocks = <&bpmp TEGRA186_CLK_SOR1>,
1087                                  <&bpmp TEGRA186_CLK_SOR1_OUT>,
1088                                  <&bpmp TEGRA186_CLK_PLLD3>,
1089                                  <&bpmp TEGRA186_CLK_PLLDP>,
1090                                  <&bpmp TEGRA186_CLK_SOR_SAFE>,
1091                                  <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>;
1092                         clock-names = "sor", "out", "parent", "dp", "safe",
1093                                       "pad";
1094                         resets = <&bpmp TEGRA186_RESET_SOR1>;
1095                         reset-names = "sor";
1096                         pinctrl-0 = <&state_dpaux1_aux>;
1097                         pinctrl-1 = <&state_dpaux1_i2c>;
1098                         pinctrl-2 = <&state_dpaux1_off>;
1099                         pinctrl-names = "aux", "i2c", "off";
1100                         status = "disabled";
1101
1102                         power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1103                         nvidia,interface = <1>;
1104                 };
1105
1106                 dpaux: dpaux@155c0000 {
1107                         compatible = "nvidia,tegra186-dpaux";
1108                         reg = <0x155c0000 0x10000>;
1109                         interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1110                         clocks = <&bpmp TEGRA186_CLK_DPAUX>,
1111                                  <&bpmp TEGRA186_CLK_PLLDP>;
1112                         clock-names = "dpaux", "parent";
1113                         resets = <&bpmp TEGRA186_RESET_DPAUX>;
1114                         reset-names = "dpaux";
1115                         status = "disabled";
1116
1117                         power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1118
1119                         state_dpaux_aux: pinmux-aux {
1120                                 groups = "dpaux-io";
1121                                 function = "aux";
1122                         };
1123
1124                         state_dpaux_i2c: pinmux-i2c {
1125                                 groups = "dpaux-io";
1126                                 function = "i2c";
1127                         };
1128
1129                         state_dpaux_off: pinmux-off {
1130                                 groups = "dpaux-io";
1131                                 function = "off";
1132                         };
1133
1134                         i2c-bus {
1135                                 #address-cells = <1>;
1136                                 #size-cells = <0>;
1137                         };
1138                 };
1139
1140                 padctl@15880000 {
1141                         compatible = "nvidia,tegra186-dsi-padctl";
1142                         reg = <0x15880000 0x10000>;
1143                         resets = <&bpmp TEGRA186_RESET_DSI>;
1144                         reset-names = "dsi";
1145                         status = "disabled";
1146                 };
1147
1148                 dsic: dsi@15900000 {
1149                         compatible = "nvidia,tegra186-dsi";
1150                         reg = <0x15900000 0x10000>;
1151                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
1152                         clocks = <&bpmp TEGRA186_CLK_DSIC>,
1153                                  <&bpmp TEGRA186_CLK_DSIC_LP>,
1154                                  <&bpmp TEGRA186_CLK_PLLD>;
1155                         clock-names = "dsi", "lp", "parent";
1156                         resets = <&bpmp TEGRA186_RESET_DSIC>;
1157                         reset-names = "dsi";
1158                         status = "disabled";
1159
1160                         power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1161                 };
1162
1163                 dsid: dsi@15940000 {
1164                         compatible = "nvidia,tegra186-dsi";
1165                         reg = <0x15940000 0x10000>;
1166                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1167                         clocks = <&bpmp TEGRA186_CLK_DSID>,
1168                                  <&bpmp TEGRA186_CLK_DSID_LP>,
1169                                  <&bpmp TEGRA186_CLK_PLLD>;
1170                         clock-names = "dsi", "lp", "parent";
1171                         resets = <&bpmp TEGRA186_RESET_DSID>;
1172                         reset-names = "dsi";
1173                         status = "disabled";
1174
1175                         power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
1176                 };
1177         };
1178
1179         gpu@17000000 {
1180                 compatible = "nvidia,gp10b";
1181                 reg = <0x0 0x17000000 0x0 0x1000000>,
1182                       <0x0 0x18000000 0x0 0x1000000>;
1183                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH
1184                               GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
1185                 interrupt-names = "stall", "nonstall";
1186
1187                 clocks = <&bpmp TEGRA186_CLK_GPCCLK>,
1188                          <&bpmp TEGRA186_CLK_GPU>;
1189                 clock-names = "gpu", "pwr";
1190                 resets = <&bpmp TEGRA186_RESET_GPU>;
1191                 reset-names = "gpu";
1192                 status = "disabled";
1193
1194                 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>;
1195         };
1196
1197         sysram@30000000 {
1198                 compatible = "nvidia,tegra186-sysram", "mmio-sram";
1199                 reg = <0x0 0x30000000 0x0 0x50000>;
1200                 #address-cells = <2>;
1201                 #size-cells = <2>;
1202                 ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>;
1203
1204                 cpu_bpmp_tx: shmem@4e000 {
1205                         compatible = "nvidia,tegra186-bpmp-shmem";
1206                         reg = <0x0 0x4e000 0x0 0x1000>;
1207                         label = "cpu-bpmp-tx";
1208                         pool;
1209                 };
1210
1211                 cpu_bpmp_rx: shmem@4f000 {
1212                         compatible = "nvidia,tegra186-bpmp-shmem";
1213                         reg = <0x0 0x4f000 0x0 0x1000>;
1214                         label = "cpu-bpmp-rx";
1215                         pool;
1216                 };
1217         };
1218
1219         bpmp: bpmp {
1220                 compatible = "nvidia,tegra186-bpmp";
1221                 iommus = <&smmu TEGRA186_SID_BPMP>;
1222                 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
1223                                     TEGRA_HSP_DB_MASTER_BPMP>;
1224                 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
1225                 #clock-cells = <1>;
1226                 #reset-cells = <1>;
1227                 #power-domain-cells = <1>;
1228
1229                 bpmp_i2c: i2c {
1230                         compatible = "nvidia,tegra186-bpmp-i2c";
1231                         nvidia,bpmp-bus-id = <5>;
1232                         #address-cells = <1>;
1233                         #size-cells = <0>;
1234                         status = "disabled";
1235                 };
1236
1237                 bpmp_thermal: thermal {
1238                         compatible = "nvidia,tegra186-bpmp-thermal";
1239                         #thermal-sensor-cells = <1>;
1240                 };
1241         };
1242
1243         cpus {
1244                 #address-cells = <1>;
1245                 #size-cells = <0>;
1246
1247                 cpu@0 {
1248                         compatible = "nvidia,tegra186-denver";
1249                         device_type = "cpu";
1250                         i-cache-size = <0x20000>;
1251                         i-cache-line-size = <64>;
1252                         i-cache-sets = <512>;
1253                         d-cache-size = <0x10000>;
1254                         d-cache-line-size = <64>;
1255                         d-cache-sets = <256>;
1256                         next-level-cache = <&L2_DENVER>;
1257                         reg = <0x000>;
1258                 };
1259
1260                 cpu@1 {
1261                         compatible = "nvidia,tegra186-denver";
1262                         device_type = "cpu";
1263                         i-cache-size = <0x20000>;
1264                         i-cache-line-size = <64>;
1265                         i-cache-sets = <512>;
1266                         d-cache-size = <0x10000>;
1267                         d-cache-line-size = <64>;
1268                         d-cache-sets = <256>;
1269                         next-level-cache = <&L2_DENVER>;
1270                         reg = <0x001>;
1271                 };
1272
1273                 cpu@2 {
1274                         compatible = "arm,cortex-a57";
1275                         device_type = "cpu";
1276                         i-cache-size = <0xC000>;
1277                         i-cache-line-size = <64>;
1278                         i-cache-sets = <256>;
1279                         d-cache-size = <0x8000>;
1280                         d-cache-line-size = <64>;
1281                         d-cache-sets = <256>;
1282                         next-level-cache = <&L2_A57>;
1283                         reg = <0x100>;
1284                 };
1285
1286                 cpu@3 {
1287                         compatible = "arm,cortex-a57";
1288                         device_type = "cpu";
1289                         i-cache-size = <0xC000>;
1290                         i-cache-line-size = <64>;
1291                         i-cache-sets = <256>;
1292                         d-cache-size = <0x8000>;
1293                         d-cache-line-size = <64>;
1294                         d-cache-sets = <256>;
1295                         next-level-cache = <&L2_A57>;
1296                         reg = <0x101>;
1297                 };
1298
1299                 cpu@4 {
1300                         compatible = "arm,cortex-a57";
1301                         device_type = "cpu";
1302                         i-cache-size = <0xC000>;
1303                         i-cache-line-size = <64>;
1304                         i-cache-sets = <256>;
1305                         d-cache-size = <0x8000>;
1306                         d-cache-line-size = <64>;
1307                         d-cache-sets = <256>;
1308                         next-level-cache = <&L2_A57>;
1309                         reg = <0x102>;
1310                 };
1311
1312                 cpu@5 {
1313                         compatible = "arm,cortex-a57";
1314                         device_type = "cpu";
1315                         i-cache-size = <0xC000>;
1316                         i-cache-line-size = <64>;
1317                         i-cache-sets = <256>;
1318                         d-cache-size = <0x8000>;
1319                         d-cache-line-size = <64>;
1320                         d-cache-sets = <256>;
1321                         next-level-cache = <&L2_A57>;
1322                         reg = <0x103>;
1323                 };
1324
1325                 L2_DENVER: l2-cache0 {
1326                         compatible = "cache";
1327                         cache-unified;
1328                         cache-level = <2>;
1329                         cache-size = <0x200000>;
1330                         cache-line-size = <64>;
1331                         cache-sets = <2048>;
1332                 };
1333
1334                 L2_A57: l2-cache1 {
1335                         compatible = "cache";
1336                         cache-unified;
1337                         cache-level = <2>;
1338                         cache-size = <0x200000>;
1339                         cache-line-size = <64>;
1340                         cache-sets = <2048>;
1341                 };
1342         };
1343
1344         thermal-zones {
1345                 a57 {
1346                         polling-delay = <0>;
1347                         polling-delay-passive = <1000>;
1348
1349                         thermal-sensors =
1350                                 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>;
1351
1352                         trips {
1353                                 critical {
1354                                         temperature = <101000>;
1355                                         hysteresis = <0>;
1356                                         type = "critical";
1357                                 };
1358                         };
1359
1360                         cooling-maps {
1361                         };
1362                 };
1363
1364                 denver {
1365                         polling-delay = <0>;
1366                         polling-delay-passive = <1000>;
1367
1368                         thermal-sensors =
1369                                 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>;
1370
1371                         trips {
1372                                 critical {
1373                                         temperature = <101000>;
1374                                         hysteresis = <0>;
1375                                         type = "critical";
1376                                 };
1377                         };
1378
1379                         cooling-maps {
1380                         };
1381                 };
1382
1383                 gpu {
1384                         polling-delay = <0>;
1385                         polling-delay-passive = <1000>;
1386
1387                         thermal-sensors =
1388                                 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>;
1389
1390                         trips {
1391                                 critical {
1392                                         temperature = <101000>;
1393                                         hysteresis = <0>;
1394                                         type = "critical";
1395                                 };
1396                         };
1397
1398                         cooling-maps {
1399                         };
1400                 };
1401
1402                 pll {
1403                         polling-delay = <0>;
1404                         polling-delay-passive = <1000>;
1405
1406                         thermal-sensors =
1407                                 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>;
1408
1409                         trips {
1410                                 critical {
1411                                         temperature = <101000>;
1412                                         hysteresis = <0>;
1413                                         type = "critical";
1414                                 };
1415                         };
1416
1417                         cooling-maps {
1418                         };
1419                 };
1420
1421                 always_on {
1422                         polling-delay = <0>;
1423                         polling-delay-passive = <1000>;
1424
1425                         thermal-sensors =
1426                                 <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>;
1427
1428                         trips {
1429                                 critical {
1430                                         temperature = <101000>;
1431                                         hysteresis = <0>;
1432                                         type = "critical";
1433                                 };
1434                         };
1435
1436                         cooling-maps {
1437                         };
1438                 };
1439         };
1440
1441         timer {
1442                 compatible = "arm,armv8-timer";
1443                 interrupts = <GIC_PPI 13
1444                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1445                              <GIC_PPI 14
1446                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1447                              <GIC_PPI 11
1448                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1449                              <GIC_PPI 10
1450                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1451                 interrupt-parent = <&gic>;
1452                 always-on;
1453         };
1454 };