1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra194-clock.h>
3 #include <dt-bindings/gpio/tegra194-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
7 #include <dt-bindings/power/tegra194-powergate.h>
8 #include <dt-bindings/reset/tegra194-reset.h>
9 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
10 #include <dt-bindings/memory/tegra194-mc.h>
13 compatible = "nvidia,tegra194";
14 interrupt-parent = <&gic>;
18 /* control backbone */
20 compatible = "simple-bus";
23 ranges = <0x0 0x0 0x0 0x40000000>;
26 compatible = "nvidia,tegra194-misc";
27 reg = <0x00100000 0xf000>,
32 compatible = "nvidia,tegra194-gpio";
33 reg-names = "security", "gpio";
34 reg = <0x2200000 0x10000>,
36 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
37 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
38 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
39 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
40 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
41 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
42 #interrupt-cells = <2>;
49 compatible = "nvidia,tegra194-eqos",
50 "nvidia,tegra186-eqos",
51 "snps,dwc-qos-ethernet-4.10";
52 reg = <0x02490000 0x10000>;
53 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
54 clocks = <&bpmp TEGRA194_CLK_AXI_CBB>,
55 <&bpmp TEGRA194_CLK_EQOS_AXI>,
56 <&bpmp TEGRA194_CLK_EQOS_RX>,
57 <&bpmp TEGRA194_CLK_EQOS_TX>,
58 <&bpmp TEGRA194_CLK_EQOS_PTP_REF>;
59 clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
60 resets = <&bpmp TEGRA194_RESET_EQOS>;
64 snps,write-requests = <1>;
65 snps,read-requests = <3>;
66 snps,burst-map = <0x7>;
72 compatible = "nvidia,tegra194-aconnect",
73 "nvidia,tegra210-aconnect";
74 clocks = <&bpmp TEGRA194_CLK_APE>,
75 <&bpmp TEGRA194_CLK_APB2APE>;
76 clock-names = "ape", "apb2ape";
77 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>;
80 ranges = <0x02900000 0x02900000 0x200000>;
83 dma-controller@2930000 {
84 compatible = "nvidia,tegra194-adma",
85 "nvidia,tegra186-adma";
86 reg = <0x02930000 0x20000>;
87 interrupt-parent = <&agic>;
88 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
89 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
90 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
91 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
92 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
93 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
94 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
95 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
96 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
97 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
98 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
99 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
100 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
101 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
102 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
103 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
104 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
105 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
106 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
107 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
108 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
109 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
110 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
111 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
112 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
113 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
114 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
115 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
116 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
117 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
118 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
119 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
121 clocks = <&bpmp TEGRA194_CLK_AHUB>;
122 clock-names = "d_audio";
126 agic: interrupt-controller@2a40000 {
127 compatible = "nvidia,tegra194-agic",
128 "nvidia,tegra210-agic";
129 #interrupt-cells = <3>;
130 interrupt-controller;
131 reg = <0x02a41000 0x1000>,
133 interrupts = <GIC_SPI 145
134 (GIC_CPU_MASK_SIMPLE(4) |
135 IRQ_TYPE_LEVEL_HIGH)>;
136 clocks = <&bpmp TEGRA194_CLK_APE>;
142 pinmux: pinmux@2430000 {
143 compatible = "nvidia,tegra194-pinmux";
144 reg = <0x2430000 0x17000
149 pex_rst_c5_out_state: pex_rst_c5_out {
151 nvidia,pins = "pex_l5_rst_n_pgg1";
152 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
153 nvidia,lpdr = <TEGRA_PIN_ENABLE>;
154 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
155 nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
156 nvidia,tristate = <TEGRA_PIN_DISABLE>;
157 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
161 clkreq_c5_bi_dir_state: clkreq_c5_bi_dir {
163 nvidia,pins = "pex_l5_clkreq_n_pgg0";
164 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
165 nvidia,lpdr = <TEGRA_PIN_ENABLE>;
166 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
167 nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
168 nvidia,tristate = <TEGRA_PIN_DISABLE>;
169 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
174 mc: memory-controller@2c00000 {
175 compatible = "nvidia,tegra194-mc";
176 reg = <0x02c00000 0x100000>,
177 <0x02b80000 0x040000>,
178 <0x01700000 0x100000>;
181 #address-cells = <2>;
184 ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>,
185 <0x02b80000 0x0 0x02b80000 0x0 0x040000>,
186 <0x02c00000 0x0 0x02c00000 0x0 0x100000>;
189 * Bit 39 of addresses passing through the memory
190 * controller selects the XBAR format used when memory
191 * is accessed. This is used to transparently access
192 * memory in the XBAR format used by the discrete GPU
193 * (bit 39 set) or Tegra (bit 39 clear).
195 * As a consequence, the operating system must ensure
196 * that bit 39 is never used implicitly, for example
197 * via an I/O virtual address mapping of an IOMMU. If
198 * devices require access to the XBAR switch, their
199 * drivers must set this bit explicitly.
201 * Limit the DMA range for memory clients to [38:0].
203 dma-ranges = <0x0 0x0 0x0 0x80 0x0>;
205 emc: external-memory-controller@2c60000 {
206 compatible = "nvidia,tegra194-emc";
207 reg = <0x0 0x02c60000 0x0 0x90000>,
208 <0x0 0x01780000 0x0 0x80000>;
209 clocks = <&bpmp TEGRA194_CLK_EMC>;
212 nvidia,bpmp = <&bpmp>;
216 uarta: serial@3100000 {
217 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
218 reg = <0x03100000 0x40>;
220 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
221 clocks = <&bpmp TEGRA194_CLK_UARTA>;
222 clock-names = "serial";
223 resets = <&bpmp TEGRA194_RESET_UARTA>;
224 reset-names = "serial";
228 uartb: serial@3110000 {
229 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
230 reg = <0x03110000 0x40>;
232 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
233 clocks = <&bpmp TEGRA194_CLK_UARTB>;
234 clock-names = "serial";
235 resets = <&bpmp TEGRA194_RESET_UARTB>;
236 reset-names = "serial";
240 uartd: serial@3130000 {
241 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
242 reg = <0x03130000 0x40>;
244 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
245 clocks = <&bpmp TEGRA194_CLK_UARTD>;
246 clock-names = "serial";
247 resets = <&bpmp TEGRA194_RESET_UARTD>;
248 reset-names = "serial";
252 uarte: serial@3140000 {
253 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
254 reg = <0x03140000 0x40>;
256 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
257 clocks = <&bpmp TEGRA194_CLK_UARTE>;
258 clock-names = "serial";
259 resets = <&bpmp TEGRA194_RESET_UARTE>;
260 reset-names = "serial";
264 uartf: serial@3150000 {
265 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
266 reg = <0x03150000 0x40>;
268 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
269 clocks = <&bpmp TEGRA194_CLK_UARTF>;
270 clock-names = "serial";
271 resets = <&bpmp TEGRA194_RESET_UARTF>;
272 reset-names = "serial";
276 gen1_i2c: i2c@3160000 {
277 compatible = "nvidia,tegra194-i2c";
278 reg = <0x03160000 0x10000>;
279 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
280 #address-cells = <1>;
282 clocks = <&bpmp TEGRA194_CLK_I2C1>;
283 clock-names = "div-clk";
284 resets = <&bpmp TEGRA194_RESET_I2C1>;
289 uarth: serial@3170000 {
290 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
291 reg = <0x03170000 0x40>;
293 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
294 clocks = <&bpmp TEGRA194_CLK_UARTH>;
295 clock-names = "serial";
296 resets = <&bpmp TEGRA194_RESET_UARTH>;
297 reset-names = "serial";
301 cam_i2c: i2c@3180000 {
302 compatible = "nvidia,tegra194-i2c";
303 reg = <0x03180000 0x10000>;
304 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
305 #address-cells = <1>;
307 clocks = <&bpmp TEGRA194_CLK_I2C3>;
308 clock-names = "div-clk";
309 resets = <&bpmp TEGRA194_RESET_I2C3>;
314 /* shares pads with dpaux1 */
315 dp_aux_ch1_i2c: i2c@3190000 {
316 compatible = "nvidia,tegra194-i2c";
317 reg = <0x03190000 0x10000>;
318 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
319 #address-cells = <1>;
321 clocks = <&bpmp TEGRA194_CLK_I2C4>;
322 clock-names = "div-clk";
323 resets = <&bpmp TEGRA194_RESET_I2C4>;
328 /* shares pads with dpaux0 */
329 dp_aux_ch0_i2c: i2c@31b0000 {
330 compatible = "nvidia,tegra194-i2c";
331 reg = <0x031b0000 0x10000>;
332 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
333 #address-cells = <1>;
335 clocks = <&bpmp TEGRA194_CLK_I2C6>;
336 clock-names = "div-clk";
337 resets = <&bpmp TEGRA194_RESET_I2C6>;
342 gen7_i2c: i2c@31c0000 {
343 compatible = "nvidia,tegra194-i2c";
344 reg = <0x031c0000 0x10000>;
345 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
346 #address-cells = <1>;
348 clocks = <&bpmp TEGRA194_CLK_I2C7>;
349 clock-names = "div-clk";
350 resets = <&bpmp TEGRA194_RESET_I2C7>;
355 gen9_i2c: i2c@31e0000 {
356 compatible = "nvidia,tegra194-i2c";
357 reg = <0x031e0000 0x10000>;
358 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
359 #address-cells = <1>;
361 clocks = <&bpmp TEGRA194_CLK_I2C9>;
362 clock-names = "div-clk";
363 resets = <&bpmp TEGRA194_RESET_I2C9>;
369 compatible = "nvidia,tegra194-pwm",
370 "nvidia,tegra186-pwm";
371 reg = <0x3280000 0x10000>;
372 clocks = <&bpmp TEGRA194_CLK_PWM1>;
374 resets = <&bpmp TEGRA194_RESET_PWM1>;
381 compatible = "nvidia,tegra194-pwm",
382 "nvidia,tegra186-pwm";
383 reg = <0x3290000 0x10000>;
384 clocks = <&bpmp TEGRA194_CLK_PWM2>;
386 resets = <&bpmp TEGRA194_RESET_PWM2>;
393 compatible = "nvidia,tegra194-pwm",
394 "nvidia,tegra186-pwm";
395 reg = <0x32a0000 0x10000>;
396 clocks = <&bpmp TEGRA194_CLK_PWM3>;
398 resets = <&bpmp TEGRA194_RESET_PWM3>;
405 compatible = "nvidia,tegra194-pwm",
406 "nvidia,tegra186-pwm";
407 reg = <0x32c0000 0x10000>;
408 clocks = <&bpmp TEGRA194_CLK_PWM5>;
410 resets = <&bpmp TEGRA194_RESET_PWM5>;
417 compatible = "nvidia,tegra194-pwm",
418 "nvidia,tegra186-pwm";
419 reg = <0x32d0000 0x10000>;
420 clocks = <&bpmp TEGRA194_CLK_PWM6>;
422 resets = <&bpmp TEGRA194_RESET_PWM6>;
429 compatible = "nvidia,tegra194-pwm",
430 "nvidia,tegra186-pwm";
431 reg = <0x32e0000 0x10000>;
432 clocks = <&bpmp TEGRA194_CLK_PWM7>;
434 resets = <&bpmp TEGRA194_RESET_PWM7>;
441 compatible = "nvidia,tegra194-pwm",
442 "nvidia,tegra186-pwm";
443 reg = <0x32f0000 0x10000>;
444 clocks = <&bpmp TEGRA194_CLK_PWM8>;
446 resets = <&bpmp TEGRA194_RESET_PWM8>;
452 sdmmc1: sdhci@3400000 {
453 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci";
454 reg = <0x03400000 0x10000>;
455 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
456 clocks = <&bpmp TEGRA194_CLK_SDMMC1>;
457 clock-names = "sdhci";
458 resets = <&bpmp TEGRA194_RESET_SDMMC1>;
459 reset-names = "sdhci";
460 nvidia,pad-autocal-pull-up-offset-3v3-timeout =
462 nvidia,pad-autocal-pull-down-offset-3v3-timeout =
464 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
465 nvidia,pad-autocal-pull-down-offset-1v8-timeout =
467 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
468 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
469 nvidia,default-tap = <0x9>;
470 nvidia,default-trim = <0x5>;
474 sdmmc3: sdhci@3440000 {
475 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci";
476 reg = <0x03440000 0x10000>;
477 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
478 clocks = <&bpmp TEGRA194_CLK_SDMMC3>;
479 clock-names = "sdhci";
480 resets = <&bpmp TEGRA194_RESET_SDMMC3>;
481 reset-names = "sdhci";
482 nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
483 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
484 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
485 nvidia,pad-autocal-pull-down-offset-3v3-timeout =
487 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
488 nvidia,pad-autocal-pull-down-offset-1v8-timeout =
490 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
491 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
492 nvidia,default-tap = <0x9>;
493 nvidia,default-trim = <0x5>;
497 sdmmc4: sdhci@3460000 {
498 compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci";
499 reg = <0x03460000 0x10000>;
500 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
501 clocks = <&bpmp TEGRA194_CLK_SDMMC4>;
502 clock-names = "sdhci";
503 assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>,
504 <&bpmp TEGRA194_CLK_PLLC4>;
505 assigned-clock-parents =
506 <&bpmp TEGRA194_CLK_PLLC4>;
507 resets = <&bpmp TEGRA194_RESET_SDMMC4>;
508 reset-names = "sdhci";
509 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>;
510 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>;
511 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
512 nvidia,pad-autocal-pull-down-offset-1v8-timeout =
514 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
515 nvidia,pad-autocal-pull-down-offset-3v3-timeout =
517 nvidia,default-tap = <0x8>;
518 nvidia,default-trim = <0x14>;
519 nvidia,dqs-trim = <40>;
525 compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda";
526 reg = <0x3510000 0x10000>;
527 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
528 clocks = <&bpmp TEGRA194_CLK_HDA>,
529 <&bpmp TEGRA194_CLK_HDA2CODEC_2X>,
530 <&bpmp TEGRA194_CLK_HDA2HDMICODEC>;
531 clock-names = "hda", "hda2codec_2x", "hda2hdmi";
532 resets = <&bpmp TEGRA194_RESET_HDA>,
533 <&bpmp TEGRA194_RESET_HDA2CODEC_2X>,
534 <&bpmp TEGRA194_RESET_HDA2HDMICODEC>;
535 reset-names = "hda", "hda2codec_2x", "hda2hdmi";
536 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
540 xusb_padctl: padctl@3520000 {
541 compatible = "nvidia,tegra194-xusb-padctl";
542 reg = <0x03520000 0x1000>,
544 reg-names = "padctl", "ao";
546 resets = <&bpmp TEGRA194_RESET_XUSB_PADCTL>;
547 reset-names = "padctl";
553 clocks = <&bpmp TEGRA194_CLK_USB2_TRK>;
558 nvidia,function = "xusb";
564 nvidia,function = "xusb";
570 nvidia,function = "xusb";
576 nvidia,function = "xusb";
586 nvidia,function = "xusb";
592 nvidia,function = "xusb";
598 nvidia,function = "xusb";
604 nvidia,function = "xusb";
648 compatible = "nvidia,tegra194-xudc";
649 reg = <0x03550000 0x8000>,
651 reg-names = "base", "fpci";
652 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
653 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_DEV>,
654 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>,
655 <&bpmp TEGRA194_CLK_XUSB_SS>,
656 <&bpmp TEGRA194_CLK_XUSB_FS>;
657 clock-names = "dev", "ss", "ss_src", "fs_src";
658 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBB>,
659 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>;
660 power-domain-names = "dev", "ss";
661 nvidia,xusb-padctl = <&xusb_padctl>;
666 compatible = "nvidia,tegra194-xusb";
667 reg = <0x03610000 0x40000>,
668 <0x03600000 0x10000>;
669 reg-names = "hcd", "fpci";
671 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
672 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
673 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
675 clocks = <&bpmp TEGRA194_CLK_XUSB_CORE_HOST>,
676 <&bpmp TEGRA194_CLK_XUSB_FALCON>,
677 <&bpmp TEGRA194_CLK_XUSB_CORE_SS>,
678 <&bpmp TEGRA194_CLK_XUSB_SS>,
679 <&bpmp TEGRA194_CLK_CLK_M>,
680 <&bpmp TEGRA194_CLK_XUSB_FS>,
681 <&bpmp TEGRA194_CLK_UTMIPLL>,
682 <&bpmp TEGRA194_CLK_CLK_M>,
683 <&bpmp TEGRA194_CLK_PLLE>;
684 clock-names = "xusb_host", "xusb_falcon_src",
685 "xusb_ss", "xusb_ss_src", "xusb_hs_src",
686 "xusb_fs_src", "pll_u_480m", "clk_m",
689 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_XUSBC>,
690 <&bpmp TEGRA194_POWER_DOMAIN_XUSBA>;
691 power-domain-names = "xusb_host", "xusb_ss";
693 nvidia,xusb-padctl = <&xusb_padctl>;
698 compatible = "nvidia,tegra194-efuse";
699 reg = <0x03820000 0x10000>;
700 clocks = <&bpmp TEGRA194_CLK_FUSE>;
701 clock-names = "fuse";
704 gic: interrupt-controller@3881000 {
705 compatible = "arm,gic-400";
706 #interrupt-cells = <3>;
707 interrupt-controller;
708 reg = <0x03881000 0x1000>,
712 interrupts = <GIC_PPI 9
713 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
714 interrupt-parent = <&gic>;
718 compatible = "nvidia,tegra194-cec";
719 reg = <0x03960000 0x10000>;
720 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
721 clocks = <&bpmp TEGRA194_CLK_CEC>;
726 hsp_top0: hsp@3c00000 {
727 compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp";
728 reg = <0x03c00000 0xa0000>;
729 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
730 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
731 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
732 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
733 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
734 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
735 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
736 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
737 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
738 interrupt-names = "doorbell", "shared0", "shared1", "shared2",
739 "shared3", "shared4", "shared5", "shared6",
744 p2u_hsio_0: phy@3e10000 {
745 compatible = "nvidia,tegra194-p2u";
746 reg = <0x03e10000 0x10000>;
752 p2u_hsio_1: phy@3e20000 {
753 compatible = "nvidia,tegra194-p2u";
754 reg = <0x03e20000 0x10000>;
760 p2u_hsio_2: phy@3e30000 {
761 compatible = "nvidia,tegra194-p2u";
762 reg = <0x03e30000 0x10000>;
768 p2u_hsio_3: phy@3e40000 {
769 compatible = "nvidia,tegra194-p2u";
770 reg = <0x03e40000 0x10000>;
776 p2u_hsio_4: phy@3e50000 {
777 compatible = "nvidia,tegra194-p2u";
778 reg = <0x03e50000 0x10000>;
784 p2u_hsio_5: phy@3e60000 {
785 compatible = "nvidia,tegra194-p2u";
786 reg = <0x03e60000 0x10000>;
792 p2u_hsio_6: phy@3e70000 {
793 compatible = "nvidia,tegra194-p2u";
794 reg = <0x03e70000 0x10000>;
800 p2u_hsio_7: phy@3e80000 {
801 compatible = "nvidia,tegra194-p2u";
802 reg = <0x03e80000 0x10000>;
808 p2u_hsio_8: phy@3e90000 {
809 compatible = "nvidia,tegra194-p2u";
810 reg = <0x03e90000 0x10000>;
816 p2u_hsio_9: phy@3ea0000 {
817 compatible = "nvidia,tegra194-p2u";
818 reg = <0x03ea0000 0x10000>;
824 p2u_nvhs_0: phy@3eb0000 {
825 compatible = "nvidia,tegra194-p2u";
826 reg = <0x03eb0000 0x10000>;
832 p2u_nvhs_1: phy@3ec0000 {
833 compatible = "nvidia,tegra194-p2u";
834 reg = <0x03ec0000 0x10000>;
840 p2u_nvhs_2: phy@3ed0000 {
841 compatible = "nvidia,tegra194-p2u";
842 reg = <0x03ed0000 0x10000>;
848 p2u_nvhs_3: phy@3ee0000 {
849 compatible = "nvidia,tegra194-p2u";
850 reg = <0x03ee0000 0x10000>;
856 p2u_nvhs_4: phy@3ef0000 {
857 compatible = "nvidia,tegra194-p2u";
858 reg = <0x03ef0000 0x10000>;
864 p2u_nvhs_5: phy@3f00000 {
865 compatible = "nvidia,tegra194-p2u";
866 reg = <0x03f00000 0x10000>;
872 p2u_nvhs_6: phy@3f10000 {
873 compatible = "nvidia,tegra194-p2u";
874 reg = <0x03f10000 0x10000>;
880 p2u_nvhs_7: phy@3f20000 {
881 compatible = "nvidia,tegra194-p2u";
882 reg = <0x03f20000 0x10000>;
888 p2u_hsio_10: phy@3f30000 {
889 compatible = "nvidia,tegra194-p2u";
890 reg = <0x03f30000 0x10000>;
896 p2u_hsio_11: phy@3f40000 {
897 compatible = "nvidia,tegra194-p2u";
898 reg = <0x03f40000 0x10000>;
904 hsp_aon: hsp@c150000 {
905 compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp";
906 reg = <0x0c150000 0xa0000>;
907 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
908 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
909 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
910 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
912 * Shared interrupt 0 is routed only to AON/SPE, so
913 * we only have 4 shared interrupts for the CCPLEX.
915 interrupt-names = "shared1", "shared2", "shared3", "shared4";
919 gen2_i2c: i2c@c240000 {
920 compatible = "nvidia,tegra194-i2c";
921 reg = <0x0c240000 0x10000>;
922 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
923 #address-cells = <1>;
925 clocks = <&bpmp TEGRA194_CLK_I2C2>;
926 clock-names = "div-clk";
927 resets = <&bpmp TEGRA194_RESET_I2C2>;
932 gen8_i2c: i2c@c250000 {
933 compatible = "nvidia,tegra194-i2c";
934 reg = <0x0c250000 0x10000>;
935 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
936 #address-cells = <1>;
938 clocks = <&bpmp TEGRA194_CLK_I2C8>;
939 clock-names = "div-clk";
940 resets = <&bpmp TEGRA194_RESET_I2C8>;
945 uartc: serial@c280000 {
946 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
947 reg = <0x0c280000 0x40>;
949 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
950 clocks = <&bpmp TEGRA194_CLK_UARTC>;
951 clock-names = "serial";
952 resets = <&bpmp TEGRA194_RESET_UARTC>;
953 reset-names = "serial";
957 uartg: serial@c290000 {
958 compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
959 reg = <0x0c290000 0x40>;
961 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
962 clocks = <&bpmp TEGRA194_CLK_UARTG>;
963 clock-names = "serial";
964 resets = <&bpmp TEGRA194_RESET_UARTG>;
965 reset-names = "serial";
970 compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc";
971 reg = <0x0c2a0000 0x10000>;
972 interrupt-parent = <&pmc>;
973 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>;
974 clocks = <&bpmp TEGRA194_CLK_CLK_32K>;
979 gpio_aon: gpio@c2f0000 {
980 compatible = "nvidia,tegra194-gpio-aon";
981 reg-names = "security", "gpio";
982 reg = <0xc2f0000 0x1000>,
984 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
985 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
986 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
987 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
990 interrupt-controller;
991 #interrupt-cells = <2>;
995 compatible = "nvidia,tegra194-pwm",
996 "nvidia,tegra186-pwm";
997 reg = <0xc340000 0x10000>;
998 clocks = <&bpmp TEGRA194_CLK_PWM4>;
1000 resets = <&bpmp TEGRA194_RESET_PWM4>;
1001 reset-names = "pwm";
1002 status = "disabled";
1007 compatible = "nvidia,tegra194-pmc";
1008 reg = <0x0c360000 0x10000>,
1009 <0x0c370000 0x10000>,
1010 <0x0c380000 0x10000>,
1011 <0x0c390000 0x10000>,
1012 <0x0c3a0000 0x10000>;
1013 reg-names = "pmc", "wake", "aotag", "scratch", "misc";
1015 #interrupt-cells = <2>;
1016 interrupt-controller;
1020 compatible = "nvidia,tegra194-host1x", "simple-bus";
1021 reg = <0x13e00000 0x10000>,
1022 <0x13e10000 0x10000>;
1023 reg-names = "hypervisor", "vm";
1024 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
1025 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
1026 clocks = <&bpmp TEGRA194_CLK_HOST1X>;
1027 clock-names = "host1x";
1028 resets = <&bpmp TEGRA194_RESET_HOST1X>;
1029 reset-names = "host1x";
1031 #address-cells = <1>;
1034 ranges = <0x15000000 0x15000000 0x01000000>;
1036 display-hub@15200000 {
1037 compatible = "nvidia,tegra194-display", "simple-bus";
1038 reg = <0x15200000 0x00040000>;
1039 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>,
1040 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>,
1041 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>,
1042 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>,
1043 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>,
1044 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>,
1045 <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>;
1046 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
1047 "wgrp3", "wgrp4", "wgrp5";
1048 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>,
1049 <&bpmp TEGRA194_CLK_NVDISPLAYHUB>;
1050 clock-names = "disp", "hub";
1051 status = "disabled";
1053 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1055 #address-cells = <1>;
1058 ranges = <0x15200000 0x15200000 0x40000>;
1061 compatible = "nvidia,tegra194-dc";
1062 reg = <0x15200000 0x10000>;
1063 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
1064 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>;
1066 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>;
1069 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1071 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
1076 compatible = "nvidia,tegra194-dc";
1077 reg = <0x15210000 0x10000>;
1078 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
1079 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>;
1081 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>;
1084 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>;
1086 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
1091 compatible = "nvidia,tegra194-dc";
1092 reg = <0x15220000 0x10000>;
1093 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
1094 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>;
1096 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>;
1099 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
1101 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
1106 compatible = "nvidia,tegra194-dc";
1107 reg = <0x15230000 0x10000>;
1108 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
1109 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>;
1111 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>;
1114 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
1116 nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
1122 compatible = "nvidia,tegra194-vic";
1123 reg = <0x15340000 0x00040000>;
1124 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
1125 clocks = <&bpmp TEGRA194_CLK_VIC>;
1126 clock-names = "vic";
1127 resets = <&bpmp TEGRA194_RESET_VIC>;
1128 reset-names = "vic";
1130 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>;
1133 dpaux0: dpaux@155c0000 {
1134 compatible = "nvidia,tegra194-dpaux";
1135 reg = <0x155c0000 0x10000>;
1136 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1137 clocks = <&bpmp TEGRA194_CLK_DPAUX>,
1138 <&bpmp TEGRA194_CLK_PLLDP>;
1139 clock-names = "dpaux", "parent";
1140 resets = <&bpmp TEGRA194_RESET_DPAUX>;
1141 reset-names = "dpaux";
1142 status = "disabled";
1144 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1146 state_dpaux0_aux: pinmux-aux {
1147 groups = "dpaux-io";
1151 state_dpaux0_i2c: pinmux-i2c {
1152 groups = "dpaux-io";
1156 state_dpaux0_off: pinmux-off {
1157 groups = "dpaux-io";
1162 #address-cells = <1>;
1167 dpaux1: dpaux@155d0000 {
1168 compatible = "nvidia,tegra194-dpaux";
1169 reg = <0x155d0000 0x10000>;
1170 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
1171 clocks = <&bpmp TEGRA194_CLK_DPAUX1>,
1172 <&bpmp TEGRA194_CLK_PLLDP>;
1173 clock-names = "dpaux", "parent";
1174 resets = <&bpmp TEGRA194_RESET_DPAUX1>;
1175 reset-names = "dpaux";
1176 status = "disabled";
1178 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1180 state_dpaux1_aux: pinmux-aux {
1181 groups = "dpaux-io";
1185 state_dpaux1_i2c: pinmux-i2c {
1186 groups = "dpaux-io";
1190 state_dpaux1_off: pinmux-off {
1191 groups = "dpaux-io";
1196 #address-cells = <1>;
1201 dpaux2: dpaux@155e0000 {
1202 compatible = "nvidia,tegra194-dpaux";
1203 reg = <0x155e0000 0x10000>;
1204 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
1205 clocks = <&bpmp TEGRA194_CLK_DPAUX2>,
1206 <&bpmp TEGRA194_CLK_PLLDP>;
1207 clock-names = "dpaux", "parent";
1208 resets = <&bpmp TEGRA194_RESET_DPAUX2>;
1209 reset-names = "dpaux";
1210 status = "disabled";
1212 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1214 state_dpaux2_aux: pinmux-aux {
1215 groups = "dpaux-io";
1219 state_dpaux2_i2c: pinmux-i2c {
1220 groups = "dpaux-io";
1224 state_dpaux2_off: pinmux-off {
1225 groups = "dpaux-io";
1230 #address-cells = <1>;
1235 dpaux3: dpaux@155f0000 {
1236 compatible = "nvidia,tegra194-dpaux";
1237 reg = <0x155f0000 0x10000>;
1238 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
1239 clocks = <&bpmp TEGRA194_CLK_DPAUX3>,
1240 <&bpmp TEGRA194_CLK_PLLDP>;
1241 clock-names = "dpaux", "parent";
1242 resets = <&bpmp TEGRA194_RESET_DPAUX3>;
1243 reset-names = "dpaux";
1244 status = "disabled";
1246 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1248 state_dpaux3_aux: pinmux-aux {
1249 groups = "dpaux-io";
1253 state_dpaux3_i2c: pinmux-i2c {
1254 groups = "dpaux-io";
1258 state_dpaux3_off: pinmux-off {
1259 groups = "dpaux-io";
1264 #address-cells = <1>;
1269 sor0: sor@15b00000 {
1270 compatible = "nvidia,tegra194-sor";
1271 reg = <0x15b00000 0x40000>;
1272 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1273 clocks = <&bpmp TEGRA194_CLK_SOR0_REF>,
1274 <&bpmp TEGRA194_CLK_SOR0_OUT>,
1275 <&bpmp TEGRA194_CLK_PLLD>,
1276 <&bpmp TEGRA194_CLK_PLLDP>,
1277 <&bpmp TEGRA194_CLK_SOR_SAFE>,
1278 <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>;
1279 clock-names = "sor", "out", "parent", "dp", "safe",
1281 resets = <&bpmp TEGRA194_RESET_SOR0>;
1282 reset-names = "sor";
1283 pinctrl-0 = <&state_dpaux0_aux>;
1284 pinctrl-1 = <&state_dpaux0_i2c>;
1285 pinctrl-2 = <&state_dpaux0_off>;
1286 pinctrl-names = "aux", "i2c", "off";
1287 status = "disabled";
1289 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1290 nvidia,interface = <0>;
1293 sor1: sor@15b40000 {
1294 compatible = "nvidia,tegra194-sor";
1295 reg = <0x15b40000 0x40000>;
1296 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1297 clocks = <&bpmp TEGRA194_CLK_SOR1_REF>,
1298 <&bpmp TEGRA194_CLK_SOR1_OUT>,
1299 <&bpmp TEGRA194_CLK_PLLD2>,
1300 <&bpmp TEGRA194_CLK_PLLDP>,
1301 <&bpmp TEGRA194_CLK_SOR_SAFE>,
1302 <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>;
1303 clock-names = "sor", "out", "parent", "dp", "safe",
1305 resets = <&bpmp TEGRA194_RESET_SOR1>;
1306 reset-names = "sor";
1307 pinctrl-0 = <&state_dpaux1_aux>;
1308 pinctrl-1 = <&state_dpaux1_i2c>;
1309 pinctrl-2 = <&state_dpaux1_off>;
1310 pinctrl-names = "aux", "i2c", "off";
1311 status = "disabled";
1313 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1314 nvidia,interface = <1>;
1317 sor2: sor@15b80000 {
1318 compatible = "nvidia,tegra194-sor";
1319 reg = <0x15b80000 0x40000>;
1320 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
1321 clocks = <&bpmp TEGRA194_CLK_SOR2_REF>,
1322 <&bpmp TEGRA194_CLK_SOR2_OUT>,
1323 <&bpmp TEGRA194_CLK_PLLD3>,
1324 <&bpmp TEGRA194_CLK_PLLDP>,
1325 <&bpmp TEGRA194_CLK_SOR_SAFE>,
1326 <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>;
1327 clock-names = "sor", "out", "parent", "dp", "safe",
1329 resets = <&bpmp TEGRA194_RESET_SOR2>;
1330 reset-names = "sor";
1331 pinctrl-0 = <&state_dpaux2_aux>;
1332 pinctrl-1 = <&state_dpaux2_i2c>;
1333 pinctrl-2 = <&state_dpaux2_off>;
1334 pinctrl-names = "aux", "i2c", "off";
1335 status = "disabled";
1337 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1338 nvidia,interface = <2>;
1341 sor3: sor@15bc0000 {
1342 compatible = "nvidia,tegra194-sor";
1343 reg = <0x15bc0000 0x40000>;
1344 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
1345 clocks = <&bpmp TEGRA194_CLK_SOR3_REF>,
1346 <&bpmp TEGRA194_CLK_SOR3_OUT>,
1347 <&bpmp TEGRA194_CLK_PLLD4>,
1348 <&bpmp TEGRA194_CLK_PLLDP>,
1349 <&bpmp TEGRA194_CLK_SOR_SAFE>,
1350 <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>;
1351 clock-names = "sor", "out", "parent", "dp", "safe",
1353 resets = <&bpmp TEGRA194_RESET_SOR3>;
1354 reset-names = "sor";
1355 pinctrl-0 = <&state_dpaux3_aux>;
1356 pinctrl-1 = <&state_dpaux3_i2c>;
1357 pinctrl-2 = <&state_dpaux3_off>;
1358 pinctrl-names = "aux", "i2c", "off";
1359 status = "disabled";
1361 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1362 nvidia,interface = <3>;
1368 compatible = "nvidia,tegra194-pcie";
1369 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
1370 reg = <0x00 0x14100000 0x0 0x00020000 /* appl registers (128K) */
1371 0x00 0x30000000 0x0 0x00040000 /* configuration space (256K) */
1372 0x00 0x30040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
1373 0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */
1374 reg-names = "appl", "config", "atu_dma", "dbi";
1376 status = "disabled";
1378 #address-cells = <3>;
1380 device_type = "pci";
1383 linux,pci-domain = <1>;
1385 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>;
1386 clock-names = "core";
1388 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>,
1389 <&bpmp TEGRA194_RESET_PEX0_CORE_1>;
1390 reset-names = "apb", "core";
1392 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
1393 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
1394 interrupt-names = "intr", "msi";
1396 #interrupt-cells = <1>;
1397 interrupt-map-mask = <0 0 0 0>;
1398 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1400 nvidia,bpmp = <&bpmp 1>;
1402 nvidia,aspm-cmrt-us = <60>;
1403 nvidia,aspm-pwr-on-t-us = <20>;
1404 nvidia,aspm-l0s-entrance-latency-us = <3>;
1406 bus-range = <0x0 0xff>;
1407 ranges = <0x81000000 0x0 0x30100000 0x0 0x30100000 0x0 0x00100000 /* downstream I/O (1MB) */
1408 0xc3000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000 /* prefetchable memory (768MB) */
1409 0x82000000 0x0 0x40000000 0x12 0x30000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */
1413 compatible = "nvidia,tegra194-pcie";
1414 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
1415 reg = <0x00 0x14120000 0x0 0x00020000 /* appl registers (128K) */
1416 0x00 0x32000000 0x0 0x00040000 /* configuration space (256K) */
1417 0x00 0x32040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
1418 0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */
1419 reg-names = "appl", "config", "atu_dma", "dbi";
1421 status = "disabled";
1423 #address-cells = <3>;
1425 device_type = "pci";
1428 linux,pci-domain = <2>;
1430 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>;
1431 clock-names = "core";
1433 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>,
1434 <&bpmp TEGRA194_RESET_PEX0_CORE_2>;
1435 reset-names = "apb", "core";
1437 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
1438 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
1439 interrupt-names = "intr", "msi";
1441 #interrupt-cells = <1>;
1442 interrupt-map-mask = <0 0 0 0>;
1443 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1445 nvidia,bpmp = <&bpmp 2>;
1447 nvidia,aspm-cmrt-us = <60>;
1448 nvidia,aspm-pwr-on-t-us = <20>;
1449 nvidia,aspm-l0s-entrance-latency-us = <3>;
1451 bus-range = <0x0 0xff>;
1452 ranges = <0x81000000 0x0 0x32100000 0x0 0x32100000 0x0 0x00100000 /* downstream I/O (1MB) */
1453 0xc3000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000 /* prefetchable memory (768MB) */
1454 0x82000000 0x0 0x40000000 0x12 0x70000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */
1458 compatible = "nvidia,tegra194-pcie";
1459 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
1460 reg = <0x00 0x14140000 0x0 0x00020000 /* appl registers (128K) */
1461 0x00 0x34000000 0x0 0x00040000 /* configuration space (256K) */
1462 0x00 0x34040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
1463 0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */
1464 reg-names = "appl", "config", "atu_dma", "dbi";
1466 status = "disabled";
1468 #address-cells = <3>;
1470 device_type = "pci";
1473 linux,pci-domain = <3>;
1475 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>;
1476 clock-names = "core";
1478 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>,
1479 <&bpmp TEGRA194_RESET_PEX0_CORE_3>;
1480 reset-names = "apb", "core";
1482 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
1483 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
1484 interrupt-names = "intr", "msi";
1486 #interrupt-cells = <1>;
1487 interrupt-map-mask = <0 0 0 0>;
1488 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1490 nvidia,bpmp = <&bpmp 3>;
1492 nvidia,aspm-cmrt-us = <60>;
1493 nvidia,aspm-pwr-on-t-us = <20>;
1494 nvidia,aspm-l0s-entrance-latency-us = <3>;
1496 bus-range = <0x0 0xff>;
1497 ranges = <0x81000000 0x0 0x34100000 0x0 0x34100000 0x0 0x00100000 /* downstream I/O (1MB) */
1498 0xc3000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000 /* prefetchable memory (768MB) */
1499 0x82000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */
1503 compatible = "nvidia,tegra194-pcie";
1504 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
1505 reg = <0x00 0x14160000 0x0 0x00020000 /* appl registers (128K) */
1506 0x00 0x36000000 0x0 0x00040000 /* configuration space (256K) */
1507 0x00 0x36040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
1508 0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */
1509 reg-names = "appl", "config", "atu_dma", "dbi";
1511 status = "disabled";
1513 #address-cells = <3>;
1515 device_type = "pci";
1518 linux,pci-domain = <4>;
1520 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>;
1521 clock-names = "core";
1523 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>,
1524 <&bpmp TEGRA194_RESET_PEX0_CORE_4>;
1525 reset-names = "apb", "core";
1527 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
1528 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
1529 interrupt-names = "intr", "msi";
1531 #interrupt-cells = <1>;
1532 interrupt-map-mask = <0 0 0 0>;
1533 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1535 nvidia,bpmp = <&bpmp 4>;
1537 nvidia,aspm-cmrt-us = <60>;
1538 nvidia,aspm-pwr-on-t-us = <20>;
1539 nvidia,aspm-l0s-entrance-latency-us = <3>;
1541 bus-range = <0x0 0xff>;
1542 ranges = <0x81000000 0x0 0x36100000 0x0 0x36100000 0x0 0x00100000 /* downstream I/O (1MB) */
1543 0xc3000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */
1544 0x82000000 0x0 0x40000000 0x17 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */
1548 compatible = "nvidia,tegra194-pcie";
1549 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
1550 reg = <0x00 0x14180000 0x0 0x00020000 /* appl registers (128K) */
1551 0x00 0x38000000 0x0 0x00040000 /* configuration space (256K) */
1552 0x00 0x38040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
1553 0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */
1554 reg-names = "appl", "config", "atu_dma", "dbi";
1556 status = "disabled";
1558 #address-cells = <3>;
1560 device_type = "pci";
1563 linux,pci-domain = <0>;
1565 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
1566 clock-names = "core";
1568 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
1569 <&bpmp TEGRA194_RESET_PEX0_CORE_0>;
1570 reset-names = "apb", "core";
1572 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
1573 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
1574 interrupt-names = "intr", "msi";
1576 #interrupt-cells = <1>;
1577 interrupt-map-mask = <0 0 0 0>;
1578 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1580 nvidia,bpmp = <&bpmp 0>;
1582 nvidia,aspm-cmrt-us = <60>;
1583 nvidia,aspm-pwr-on-t-us = <20>;
1584 nvidia,aspm-l0s-entrance-latency-us = <3>;
1586 bus-range = <0x0 0xff>;
1587 ranges = <0x81000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000 /* downstream I/O (1MB) */
1588 0xc3000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */
1589 0x82000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */
1593 compatible = "nvidia,tegra194-pcie";
1594 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
1595 reg = <0x00 0x141a0000 0x0 0x00020000 /* appl registers (128K) */
1596 0x00 0x3a000000 0x0 0x00040000 /* configuration space (256K) */
1597 0x00 0x3a040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
1598 0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */
1599 reg-names = "appl", "config", "atu_dma", "dbi";
1601 status = "disabled";
1603 #address-cells = <3>;
1605 device_type = "pci";
1608 linux,pci-domain = <5>;
1610 pinctrl-names = "default";
1611 pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>;
1613 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>,
1614 <&bpmp TEGRA194_CLK_PEX1_CORE_5M>;
1615 clock-names = "core", "core_m";
1617 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
1618 <&bpmp TEGRA194_RESET_PEX1_CORE_5>;
1619 reset-names = "apb", "core";
1621 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
1622 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
1623 interrupt-names = "intr", "msi";
1625 nvidia,bpmp = <&bpmp 5>;
1627 #interrupt-cells = <1>;
1628 interrupt-map-mask = <0 0 0 0>;
1629 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1631 nvidia,aspm-cmrt-us = <60>;
1632 nvidia,aspm-pwr-on-t-us = <20>;
1633 nvidia,aspm-l0s-entrance-latency-us = <3>;
1635 bus-range = <0x0 0xff>;
1636 ranges = <0x81000000 0x0 0x3a100000 0x0 0x3a100000 0x0 0x00100000 /* downstream I/O (1MB) */
1637 0xc3000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */
1638 0x82000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */
1642 compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep";
1643 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
1644 reg = <0x00 0x14160000 0x0 0x00020000 /* appl registers (128K) */
1645 0x00 0x36040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
1646 0x00 0x36080000 0x0 0x00040000 /* DBI reg space (256K) */
1647 0x14 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
1648 reg-names = "appl", "atu_dma", "dbi", "addr_space";
1650 status = "disabled";
1653 num-ib-windows = <2>;
1654 num-ob-windows = <8>;
1656 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>;
1657 clock-names = "core";
1659 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>,
1660 <&bpmp TEGRA194_RESET_PEX0_CORE_4>;
1661 reset-names = "apb", "core";
1663 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
1664 interrupt-names = "intr";
1666 nvidia,bpmp = <&bpmp 4>;
1668 nvidia,aspm-cmrt-us = <60>;
1669 nvidia,aspm-pwr-on-t-us = <20>;
1670 nvidia,aspm-l0s-entrance-latency-us = <3>;
1674 compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep";
1675 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
1676 reg = <0x00 0x14180000 0x0 0x00020000 /* appl registers (128K) */
1677 0x00 0x38040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
1678 0x00 0x38080000 0x0 0x00040000 /* DBI reg space (256K) */
1679 0x18 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
1680 reg-names = "appl", "atu_dma", "dbi", "addr_space";
1682 status = "disabled";
1685 num-ib-windows = <2>;
1686 num-ob-windows = <8>;
1688 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
1689 clock-names = "core";
1691 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
1692 <&bpmp TEGRA194_RESET_PEX0_CORE_0>;
1693 reset-names = "apb", "core";
1695 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
1696 interrupt-names = "intr";
1698 nvidia,bpmp = <&bpmp 0>;
1700 nvidia,aspm-cmrt-us = <60>;
1701 nvidia,aspm-pwr-on-t-us = <20>;
1702 nvidia,aspm-l0s-entrance-latency-us = <3>;
1706 compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep";
1707 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
1708 reg = <0x00 0x141a0000 0x0 0x00020000 /* appl registers (128K) */
1709 0x00 0x3a040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */
1710 0x00 0x3a080000 0x0 0x00040000 /* DBI reg space (256K) */
1711 0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
1712 reg-names = "appl", "atu_dma", "dbi", "addr_space";
1714 status = "disabled";
1717 num-ib-windows = <2>;
1718 num-ob-windows = <8>;
1720 pinctrl-names = "default";
1721 pinctrl-0 = <&clkreq_c5_bi_dir_state>;
1723 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>;
1724 clock-names = "core";
1726 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
1727 <&bpmp TEGRA194_RESET_PEX1_CORE_5>;
1728 reset-names = "apb", "core";
1730 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
1731 interrupt-names = "intr";
1733 nvidia,bpmp = <&bpmp 5>;
1735 nvidia,aspm-cmrt-us = <60>;
1736 nvidia,aspm-pwr-on-t-us = <20>;
1737 nvidia,aspm-l0s-entrance-latency-us = <3>;
1741 compatible = "nvidia,tegra194-sysram", "mmio-sram";
1742 reg = <0x0 0x40000000 0x0 0x50000>;
1743 #address-cells = <1>;
1745 ranges = <0x0 0x0 0x40000000 0x50000>;
1747 cpu_bpmp_tx: shmem@4e000 {
1748 compatible = "nvidia,tegra194-bpmp-shmem";
1749 reg = <0x4e000 0x1000>;
1750 label = "cpu-bpmp-tx";
1754 cpu_bpmp_rx: shmem@4f000 {
1755 compatible = "nvidia,tegra194-bpmp-shmem";
1756 reg = <0x4f000 0x1000>;
1757 label = "cpu-bpmp-rx";
1763 compatible = "nvidia,tegra186-bpmp";
1764 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
1765 TEGRA_HSP_DB_MASTER_BPMP>;
1766 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
1769 #power-domain-cells = <1>;
1772 compatible = "nvidia,tegra186-bpmp-i2c";
1773 nvidia,bpmp-bus-id = <5>;
1774 #address-cells = <1>;
1778 bpmp_thermal: thermal {
1779 compatible = "nvidia,tegra186-bpmp-thermal";
1780 #thermal-sensor-cells = <1>;
1785 #address-cells = <1>;
1789 compatible = "nvidia,tegra194-carmel";
1790 device_type = "cpu";
1792 enable-method = "psci";
1793 i-cache-size = <131072>;
1794 i-cache-line-size = <64>;
1795 i-cache-sets = <512>;
1796 d-cache-size = <65536>;
1797 d-cache-line-size = <64>;
1798 d-cache-sets = <256>;
1799 next-level-cache = <&l2c_0>;
1803 compatible = "nvidia,tegra194-carmel";
1804 device_type = "cpu";
1806 enable-method = "psci";
1807 i-cache-size = <131072>;
1808 i-cache-line-size = <64>;
1809 i-cache-sets = <512>;
1810 d-cache-size = <65536>;
1811 d-cache-line-size = <64>;
1812 d-cache-sets = <256>;
1813 next-level-cache = <&l2c_0>;
1817 compatible = "nvidia,tegra194-carmel";
1818 device_type = "cpu";
1820 enable-method = "psci";
1821 i-cache-size = <131072>;
1822 i-cache-line-size = <64>;
1823 i-cache-sets = <512>;
1824 d-cache-size = <65536>;
1825 d-cache-line-size = <64>;
1826 d-cache-sets = <256>;
1827 next-level-cache = <&l2c_1>;
1831 compatible = "nvidia,tegra194-carmel";
1832 device_type = "cpu";
1834 enable-method = "psci";
1835 i-cache-size = <131072>;
1836 i-cache-line-size = <64>;
1837 i-cache-sets = <512>;
1838 d-cache-size = <65536>;
1839 d-cache-line-size = <64>;
1840 d-cache-sets = <256>;
1841 next-level-cache = <&l2c_1>;
1845 compatible = "nvidia,tegra194-carmel";
1846 device_type = "cpu";
1848 enable-method = "psci";
1849 i-cache-size = <131072>;
1850 i-cache-line-size = <64>;
1851 i-cache-sets = <512>;
1852 d-cache-size = <65536>;
1853 d-cache-line-size = <64>;
1854 d-cache-sets = <256>;
1855 next-level-cache = <&l2c_2>;
1859 compatible = "nvidia,tegra194-carmel";
1860 device_type = "cpu";
1862 enable-method = "psci";
1863 i-cache-size = <131072>;
1864 i-cache-line-size = <64>;
1865 i-cache-sets = <512>;
1866 d-cache-size = <65536>;
1867 d-cache-line-size = <64>;
1868 d-cache-sets = <256>;
1869 next-level-cache = <&l2c_2>;
1873 compatible = "nvidia,tegra194-carmel";
1874 device_type = "cpu";
1876 enable-method = "psci";
1877 i-cache-size = <131072>;
1878 i-cache-line-size = <64>;
1879 i-cache-sets = <512>;
1880 d-cache-size = <65536>;
1881 d-cache-line-size = <64>;
1882 d-cache-sets = <256>;
1883 next-level-cache = <&l2c_3>;
1887 compatible = "nvidia,tegra194-carmel";
1888 device_type = "cpu";
1890 enable-method = "psci";
1891 i-cache-size = <131072>;
1892 i-cache-line-size = <64>;
1893 i-cache-sets = <512>;
1894 d-cache-size = <65536>;
1895 d-cache-line-size = <64>;
1896 d-cache-sets = <256>;
1897 next-level-cache = <&l2c_3>;
1943 cache-size = <2097152>;
1944 cache-line-size = <64>;
1945 cache-sets = <2048>;
1946 next-level-cache = <&l3c>;
1950 cache-size = <2097152>;
1951 cache-line-size = <64>;
1952 cache-sets = <2048>;
1953 next-level-cache = <&l3c>;
1957 cache-size = <2097152>;
1958 cache-line-size = <64>;
1959 cache-sets = <2048>;
1960 next-level-cache = <&l3c>;
1964 cache-size = <2097152>;
1965 cache-line-size = <64>;
1966 cache-sets = <2048>;
1967 next-level-cache = <&l3c>;
1971 cache-size = <4194304>;
1972 cache-line-size = <64>;
1973 cache-sets = <4096>;
1978 compatible = "arm,psci-1.0";
1984 compatible = "nvidia,tegra194-tcu";
1985 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>,
1986 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>;
1987 mbox-names = "rx", "tx";
1992 thermal-sensors = <&{/bpmp/thermal}
1993 TEGRA194_BPMP_THERMAL_ZONE_CPU>;
1994 status = "disabled";
1998 thermal-sensors = <&{/bpmp/thermal}
1999 TEGRA194_BPMP_THERMAL_ZONE_GPU>;
2000 status = "disabled";
2004 thermal-sensors = <&{/bpmp/thermal}
2005 TEGRA194_BPMP_THERMAL_ZONE_AUX>;
2006 status = "disabled";
2010 thermal-sensors = <&{/bpmp/thermal}
2011 TEGRA194_BPMP_THERMAL_ZONE_PLLX>;
2012 status = "disabled";
2016 thermal-sensors = <&{/bpmp/thermal}
2017 TEGRA194_BPMP_THERMAL_ZONE_AO>;
2018 status = "disabled";
2022 thermal-sensors = <&{/bpmp/thermal}
2023 TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>;
2024 status = "disabled";
2029 compatible = "arm,armv8-timer";
2030 interrupts = <GIC_PPI 13
2031 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2033 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2035 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2037 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
2038 interrupt-parent = <&gic>;