sys/gnu/dts/arm64/nvidia/tegra194.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include <dt-bindings/clock/tegra194-clock.h>
   3 #include <dt-bindings/gpio/tegra194-gpio.h>
   4 #include <dt-bindings/interrupt-controller/arm-gic.h>
   5 #include <dt-bindings/mailbox/tegra186-hsp.h>
   6 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
   7 #include <dt-bindings/power/tegra194-powergate.h>
   8 #include <dt-bindings/reset/tegra194-reset.h>
   9 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
  10 #include <dt-bindings/memory/tegra194-mc.h>
  11
  12 / {
  13         compatible = "nvidia,tegra194";
  14         interrupt-parent = <&gic>;
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         /* control backbone */
  19         cbb@0 {
  20                 compatible = "simple-bus";
  21                 #address-cells = <1>;
  22                 #size-cells = <1>;
  23                 ranges = <0x0 0x0 0x0 0x40000000>;
  24
  25                 misc@100000 {
  26                         compatible = "nvidia,tegra194-misc";
  27                         reg = <0x00100000 0xf000>,
  28                               <0x0010f000 0x1000>;
  29                 };
  30
  31                 gpio: gpio@2200000 {
  32                         compatible = "nvidia,tegra194-gpio";
  33                         reg-names = "security", "gpio";
  34                         reg = <0x2200000 0x10000>,
  35                               <0x2210000 0x10000>;
  36                         interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
  37                                      <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
  38                                      <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
  39                                      <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
  40                                      <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
  41                                      <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
  42                         #interrupt-cells = <2>;
  43                         interrupt-controller;
  44                         #gpio-cells = <2>;
  45                         gpio-controller;
  46                 };
  47
  48                 ethernet@2490000 {
  49                         compatible = "nvidia,tegra194-eqos",
  50                                      "nvidia,tegra186-eqos",
  51                                      "snps,dwc-qos-ethernet-4.10";
  52                         reg = <0x02490000 0x10000>;
  53                         interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
  54                         clocks = <&bpmp TEGRA194_CLK_AXI_CBB>,
  55                                  <&bpmp TEGRA194_CLK_EQOS_AXI>,
  56                                  <&bpmp TEGRA194_CLK_EQOS_RX>,
  57                                  <&bpmp TEGRA194_CLK_EQOS_TX>,
  58                                  <&bpmp TEGRA194_CLK_EQOS_PTP_REF>;
  59                         clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
  60                         resets = <&bpmp TEGRA194_RESET_EQOS>;
  61                         reset-names = "eqos";
  62                         status = "disabled";
  63
  64                         snps,write-requests = <1>;
  65                         snps,read-requests = <3>;
  66                         snps,burst-map = <0x7>;
  67                         snps,txpbl = <16>;
  68                         snps,rxpbl = <8>;
  69                 };
  70
  71                 aconnect@2900000 {
  72                         compatible = "nvidia,tegra194-aconnect",
  73                                      "nvidia,tegra210-aconnect";
  74                         clocks = <&bpmp TEGRA194_CLK_APE>,
  75                                  <&bpmp TEGRA194_CLK_APB2APE>;
  76                         clock-names = "ape", "apb2ape";
  77                         power-domains = <&bpmp TEGRA194_POWER_DOMAIN_AUD>;
  78                         #address-cells = <1>;
  79                         #size-cells = <1>;
  80                         ranges = <0x02900000 0x02900000 0x200000>;
  81                         status = "disabled";
  82
  83                         dma-controller@2930000 {
  84                                 compatible = "nvidia,tegra194-adma",
  85                                              "nvidia,tegra186-adma";
  86                                 reg = <0x02930000 0x20000>;
  87                                 interrupt-parent = <&agic>;
  88                                 interrupts =  <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
  89                                               <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
  90                                               <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
  91                                               <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
  92                                               <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
  93                                               <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
  94                                               <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
  95                                               <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
  96                                               <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
  97                                               <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
  98                                               <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
  99                                               <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 100                                               <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 101                                               <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 102                                               <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 103                                               <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 104                                               <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 105                                               <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
 106                                               <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 107                                               <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 108                                               <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
 109                                               <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
 110                                               <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
 111                                               <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
 112                                               <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
 113                                               <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
 114                                               <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
 115                                               <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
 116                                               <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
 117                                               <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
 118                                               <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
 119                                               <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 120                                 #dma-cells = <1>;
 121                                 clocks = <&bpmp TEGRA194_CLK_AHUB>;
 122                                 clock-names = "d_audio";
 123                                 status = "disabled";
 124                         };
 125
 126                         agic: interrupt-controller@2a40000 {
 127                                 compatible = "nvidia,tegra194-agic",
 128                                              "nvidia,tegra210-agic";
 129                                 #interrupt-cells = <3>;
 130                                 interrupt-controller;
 131                                 reg = <0x02a41000 0x1000>,
 132                                       <0x02a42000 0x2000>;
 133                                 interrupts = <GIC_SPI 145
 134                                               (GIC_CPU_MASK_SIMPLE(4) |
 135                                                IRQ_TYPE_LEVEL_HIGH)>;
 136                                 clocks = <&bpmp TEGRA194_CLK_APE>;
 137                                 clock-names = "clk";
 138                                 status = "disabled";
 139                         };
 140                 };
 141
 142                 pinmux: pinmux@2430000 {
 143                         compatible = "nvidia,tegra194-pinmux";
 144                         reg = <0x2430000 0x17000
 145                                0xc300000 0x4000>;
 146
 147                         status = "okay";
 148
 149                         pex_rst_c5_out_state: pex_rst_c5_out {
 150                                 pex_rst {
 151                                         nvidia,pins = "pex_l5_rst_n_pgg1";
 152                                         nvidia,schmitt = <TEGRA_PIN_DISABLE>;
 153                                         nvidia,lpdr = <TEGRA_PIN_ENABLE>;
 154                                         nvidia,enable-input = <TEGRA_PIN_DISABLE>;
 155                                         nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
 156                                         nvidia,tristate = <TEGRA_PIN_DISABLE>;
 157                                         nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 158                                 };
 159                         };
 160
 161                         clkreq_c5_bi_dir_state: clkreq_c5_bi_dir {
 162                                 clkreq {
 163                                         nvidia,pins = "pex_l5_clkreq_n_pgg0";
 164                                         nvidia,schmitt = <TEGRA_PIN_DISABLE>;
 165                                         nvidia,lpdr = <TEGRA_PIN_ENABLE>;
 166                                         nvidia,enable-input = <TEGRA_PIN_ENABLE>;
 167                                         nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
 168                                         nvidia,tristate = <TEGRA_PIN_DISABLE>;
 169                                         nvidia,pull = <TEGRA_PIN_PULL_NONE>;
 170                                 };
 171                         };
 172                 };
 173
 174                 mc: memory-controller@2c00000 {
 175                         compatible = "nvidia,tegra194-mc";
 176                         reg = <0x02c00000 0x100000>,
 177                               <0x02b80000 0x040000>,
 178                               <0x01700000 0x100000>;
 179                         status = "disabled";
 180
 181                         #address-cells = <2>;
 182                         #size-cells = <2>;
 183
 184                         ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>,
 185                                  <0x02b80000 0x0 0x02b80000 0x0 0x040000>,
 186                                  <0x02c00000 0x0 0x02c00000 0x0 0x100000>;
 187
 188                         /*
 189                          * Bit 39 of addresses passing through the memory
 190                          * controller selects the XBAR format used when memory
 191                          * is accessed. This is used to transparently access
 192                          * memory in the XBAR format used by the discrete GPU
 193                          * (bit 39 set) or Tegra (bit 39 clear).
 194                          *
 195                          * As a consequence, the operating system must ensure
 196                          * that bit 39 is never used implicitly, for example
 197                          * via an I/O virtual address mapping of an IOMMU. If
 198                          * devices require access to the XBAR switch, their
 199                          * drivers must set this bit explicitly.
 200                          *
 201                          * Limit the DMA range for memory clients to [38:0].
 202                          */
 203                         dma-ranges = <0x0 0x0 0x0 0x80 0x0>;
 204
 205                         emc: external-memory-controller@2c60000 {
 206                                 compatible = "nvidia,tegra194-emc";
 207                                 reg = <0x0 0x02c60000 0x0 0x90000>,
 208                                       <0x0 0x01780000 0x0 0x80000>;
 209                                 clocks = <&bpmp TEGRA194_CLK_EMC>;
 210                                 clock-names = "emc";
 211
 212                                 nvidia,bpmp = <&bpmp>;
 213                         };
 214                 };
 215
 216                 uarta: serial@3100000 {
 217                         compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
 218                         reg = <0x03100000 0x40>;
 219                         reg-shift = <2>;
 220                         interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 221                         clocks = <&bpmp TEGRA194_CLK_UARTA>;
 222                         clock-names = "serial";
 223                         resets = <&bpmp TEGRA194_RESET_UARTA>;
 224                         reset-names = "serial";
 225                         status = "disabled";
 226                 };
 227
 228                 uartb: serial@3110000 {
 229                         compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
 230                         reg = <0x03110000 0x40>;
 231                         reg-shift = <2>;
 232                         interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 233                         clocks = <&bpmp TEGRA194_CLK_UARTB>;
 234                         clock-names = "serial";
 235                         resets = <&bpmp TEGRA194_RESET_UARTB>;
 236                         reset-names = "serial";
 237                         status = "disabled";
 238                 };
 239
 240                 uartd: serial@3130000 {
 241                         compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
 242                         reg = <0x03130000 0x40>;
 243                         reg-shift = <2>;
 244                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 245                         clocks = <&bpmp TEGRA194_CLK_UARTD>;
 246                         clock-names = "serial";
 247                         resets = <&bpmp TEGRA194_RESET_UARTD>;
 248                         reset-names = "serial";
 249                         status = "disabled";
 250                 };
 251
 252                 uarte: serial@3140000 {
 253                         compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
 254                         reg = <0x03140000 0x40>;
 255                         reg-shift = <2>;
 256                         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 257                         clocks = <&bpmp TEGRA194_CLK_UARTE>;
 258                         clock-names = "serial";
 259                         resets = <&bpmp TEGRA194_RESET_UARTE>;
 260                         reset-names = "serial";
 261                         status = "disabled";
 262                 };
 263
 264                 uartf: serial@3150000 {
 265                         compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
 266                         reg = <0x03150000 0x40>;
 267                         reg-shift = <2>;
 268                         interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 269                         clocks = <&bpmp TEGRA194_CLK_UARTF>;
 270                         clock-names = "serial";
 271                         resets = <&bpmp TEGRA194_RESET_UARTF>;
 272                         reset-names = "serial";
 273                         status = "disabled";
 274                 };
 275
 276                 gen1_i2c: i2c@3160000 {
 277                         compatible = "nvidia,tegra194-i2c";
 278                         reg = <0x03160000 0x10000>;
 279                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 280                         #address-cells = <1>;
 281                         #size-cells = <0>;
 282                         clocks = <&bpmp TEGRA194_CLK_I2C1>;
 283                         clock-names = "div-clk";
 284                         resets = <&bpmp TEGRA194_RESET_I2C1>;
 285                         reset-names = "i2c";
 286                         status = "disabled";
 287                 };
 288
 289                 uarth: serial@3170000 {
 290                         compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
 291                         reg = <0x03170000 0x40>;
 292                         reg-shift = <2>;
 293                         interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
 294                         clocks = <&bpmp TEGRA194_CLK_UARTH>;
 295                         clock-names = "serial";
 296                         resets = <&bpmp TEGRA194_RESET_UARTH>;
 297                         reset-names = "serial";
 298                         status = "disabled";
 299                 };
 300
 301                 cam_i2c: i2c@3180000 {
 302                         compatible = "nvidia,tegra194-i2c";
 303                         reg = <0x03180000 0x10000>;
 304                         interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 305                         #address-cells = <1>;
 306                         #size-cells = <0>;
 307                         clocks = <&bpmp TEGRA194_CLK_I2C3>;
 308                         clock-names = "div-clk";
 309                         resets = <&bpmp TEGRA194_RESET_I2C3>;
 310                         reset-names = "i2c";
 311                         status = "disabled";
 312                 };
 313
 314                 /* shares pads with dpaux1 */
 315                 dp_aux_ch1_i2c: i2c@3190000 {
 316                         compatible = "nvidia,tegra194-i2c";
 317                         reg = <0x03190000 0x10000>;
 318                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 319                         #address-cells = <1>;
 320                         #size-cells = <0>;
 321                         clocks = <&bpmp TEGRA194_CLK_I2C4>;
 322                         clock-names = "div-clk";
 323                         resets = <&bpmp TEGRA194_RESET_I2C4>;
 324                         reset-names = "i2c";
 325                         status = "disabled";
 326                 };
 327
 328                 /* shares pads with dpaux0 */
 329                 dp_aux_ch0_i2c: i2c@31b0000 {
 330                         compatible = "nvidia,tegra194-i2c";
 331                         reg = <0x031b0000 0x10000>;
 332                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 333                         #address-cells = <1>;
 334                         #size-cells = <0>;
 335                         clocks = <&bpmp TEGRA194_CLK_I2C6>;
 336                         clock-names = "div-clk";
 337                         resets = <&bpmp TEGRA194_RESET_I2C6>;
 338                         reset-names = "i2c";
 339                         status = "disabled";
 340                 };
 341
 342                 gen7_i2c: i2c@31c0000 {
 343                         compatible = "nvidia,tegra194-i2c";
 344                         reg = <0x031c0000 0x10000>;
 345                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 346                         #address-cells = <1>;
 347                         #size-cells = <0>;
 348                         clocks = <&bpmp TEGRA194_CLK_I2C7>;
 349                         clock-names = "div-clk";
 350                         resets = <&bpmp TEGRA194_RESET_I2C7>;
 351                         reset-names = "i2c";
 352                         status = "disabled";
 353                 };
 354
 355                 gen9_i2c: i2c@31e0000 {
 356                         compatible = "nvidia,tegra194-i2c";
 357                         reg = <0x031e0000 0x10000>;
 358                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 359                         #address-cells = <1>;
 360                         #size-cells = <0>;
 361                         clocks = <&bpmp TEGRA194_CLK_I2C9>;
 362                         clock-names = "div-clk";
 363                         resets = <&bpmp TEGRA194_RESET_I2C9>;
 364                         reset-names = "i2c";
 365                         status = "disabled";
 366                 };
 367
 368                 pwm1: pwm@3280000 {
 369                         compatible = "nvidia,tegra194-pwm",
 370                                      "nvidia,tegra186-pwm";
 371                         reg = <0x3280000 0x10000>;
 372                         clocks = <&bpmp TEGRA194_CLK_PWM1>;
 373                         clock-names = "pwm";
 374                         resets = <&bpmp TEGRA194_RESET_PWM1>;
 375                         reset-names = "pwm";
 376                         status = "disabled";
 377                         #pwm-cells = <2>;
 378                 };
 379
 380                 pwm2: pwm@3290000 {
 381                         compatible = "nvidia,tegra194-pwm",
 382                                      "nvidia,tegra186-pwm";
 383                         reg = <0x3290000 0x10000>;
 384                         clocks = <&bpmp TEGRA194_CLK_PWM2>;
 385                         clock-names = "pwm";
 386                         resets = <&bpmp TEGRA194_RESET_PWM2>;
 387                         reset-names = "pwm";
 388                         status = "disabled";
 389                         #pwm-cells = <2>;
 390                 };
 391
 392                 pwm3: pwm@32a0000 {
 393                         compatible = "nvidia,tegra194-pwm",
 394                                      "nvidia,tegra186-pwm";
 395                         reg = <0x32a0000 0x10000>;
 396                         clocks = <&bpmp TEGRA194_CLK_PWM3>;
 397                         clock-names = "pwm";
 398                         resets = <&bpmp TEGRA194_RESET_PWM3>;
 399                         reset-names = "pwm";
 400                         status = "disabled";
 401                         #pwm-cells = <2>;
 402                 };
 403
 404                 pwm5: pwm@32c0000 {
 405                         compatible = "nvidia,tegra194-pwm",
 406                                      "nvidia,tegra186-pwm";
 407                         reg = <0x32c0000 0x10000>;
 408                         clocks = <&bpmp TEGRA194_CLK_PWM5>;
 409                         clock-names = "pwm";
 410                         resets = <&bpmp TEGRA194_RESET_PWM5>;
 411                         reset-names = "pwm";
 412                         status = "disabled";
 413                         #pwm-cells = <2>;
 414                 };
 415
 416                 pwm6: pwm@32d0000 {
 417                         compatible = "nvidia,tegra194-pwm",
 418                                      "nvidia,tegra186-pwm";
 419                         reg = <0x32d0000 0x10000>;
 420                         clocks = <&bpmp TEGRA194_CLK_PWM6>;
 421                         clock-names = "pwm";
 422                         resets = <&bpmp TEGRA194_RESET_PWM6>;
 423                         reset-names = "pwm";
 424                         status = "disabled";
 425                         #pwm-cells = <2>;
 426                 };
 427
 428                 pwm7: pwm@32e0000 {
 429                         compatible = "nvidia,tegra194-pwm",
 430                                      "nvidia,tegra186-pwm";
 431                         reg = <0x32e0000 0x10000>;
 432                         clocks = <&bpmp TEGRA194_CLK_PWM7>;
 433                         clock-names = "pwm";
 434                         resets = <&bpmp TEGRA194_RESET_PWM7>;
 435                         reset-names = "pwm";
 436                         status = "disabled";
 437                         #pwm-cells = <2>;
 438                 };
 439
 440                 pwm8: pwm@32f0000 {
 441                         compatible = "nvidia,tegra194-pwm",
 442                                      "nvidia,tegra186-pwm";
 443                         reg = <0x32f0000 0x10000>;
 444                         clocks = <&bpmp TEGRA194_CLK_PWM8>;
 445                         clock-names = "pwm";
 446                         resets = <&bpmp TEGRA194_RESET_PWM8>;
 447                         reset-names = "pwm";
 448                         status = "disabled";
 449                         #pwm-cells = <2>;
 450                 };
 451
 452                 sdmmc1: sdhci@3400000 {
 453                         compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci";
 454                         reg = <0x03400000 0x10000>;
 455                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 456                         clocks = <&bpmp TEGRA194_CLK_SDMMC1>;
 457                         clock-names = "sdhci";
 458                         resets = <&bpmp TEGRA194_RESET_SDMMC1>;
 459                         reset-names = "sdhci";
 460                         nvidia,pad-autocal-pull-up-offset-3v3-timeout =
 461                                                                         <0x07>;
 462                         nvidia,pad-autocal-pull-down-offset-3v3-timeout =
 463                                                                         <0x07>;
 464                         nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
 465                         nvidia,pad-autocal-pull-down-offset-1v8-timeout =
 466                                                                         <0x07>;
 467                         nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
 468                         nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
 469                         nvidia,default-tap = <0x9>;
 470                         nvidia,default-trim = <0x5>;
 471                         status = "disabled";
 472                 };
 473
 474                 sdmmc3: sdhci@3440000 {
 475                         compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci";
 476                         reg = <0x03440000 0x10000>;
 477                         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 478                         clocks = <&bpmp TEGRA194_CLK_SDMMC3>;
 479                         clock-names = "sdhci";
 480                         resets = <&bpmp TEGRA194_RESET_SDMMC3>;
 481                         reset-names = "sdhci";
 482                         nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
 483                         nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
 484                         nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
 485                         nvidia,pad-autocal-pull-down-offset-3v3-timeout =
 486                                                                         <0x07>;
 487                         nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
 488                         nvidia,pad-autocal-pull-down-offset-1v8-timeout =
 489                                                                         <0x07>;
 490                         nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
 491                         nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
 492                         nvidia,default-tap = <0x9>;
 493                         nvidia,default-trim = <0x5>;
 494                         status = "disabled";
 495                 };
 496
 497                 sdmmc4: sdhci@3460000 {
 498                         compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci";
 499                         reg = <0x03460000 0x10000>;
 500                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 501                         clocks = <&bpmp TEGRA194_CLK_SDMMC4>;
 502                         clock-names = "sdhci";
 503                         assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC4>,
 504                                           <&bpmp TEGRA194_CLK_PLLC4>;
 505                         assigned-clock-parents =
 506                                           <&bpmp TEGRA194_CLK_PLLC4>;
 507                         resets = <&bpmp TEGRA194_RESET_SDMMC4>;
 508                         reset-names = "sdhci";
 509                         nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>;
 510                         nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>;
 511                         nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
 512                         nvidia,pad-autocal-pull-down-offset-1v8-timeout =
 513                                                                         <0x0a>;
 514                         nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
 515                         nvidia,pad-autocal-pull-down-offset-3v3-timeout =
 516                                                                         <0x0a>;
 517                         nvidia,default-tap = <0x8>;
 518                         nvidia,default-trim = <0x14>;
 519                         nvidia,dqs-trim = <40>;
 520                         supports-cqe;
 521                         status = "disabled";
 522                 };
 523
 524                 hda@3510000 {
 525                         compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda";
 526                         reg = <0x3510000 0x10000>;
 527                         interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
 528                         clocks = <&bpmp TEGRA194_CLK_HDA>,
 529                                  <&bpmp TEGRA194_CLK_HDA2CODEC_2X>,
 530                                  <&bpmp TEGRA194_CLK_HDA2HDMICODEC>;
 531                         clock-names = "hda", "hda2codec_2x", "hda2hdmi";
 532                         resets = <&bpmp TEGRA194_RESET_HDA>,
 533                                  <&bpmp TEGRA194_RESET_HDA2CODEC_2X>,
 534                                  <&bpmp TEGRA194_RESET_HDA2HDMICODEC>;
 535                         reset-names = "hda", "hda2codec_2x", "hda2hdmi";
 536                         power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
 537                         status = "disabled";
 538                 };
 539
 540                 fuse@3820000 {
 541                         compatible = "nvidia,tegra194-efuse";
 542                         reg = <0x03820000 0x10000>;
 543                         clocks = <&bpmp TEGRA194_CLK_FUSE>;
 544                         clock-names = "fuse";
 545                 };
 546
 547                 gic: interrupt-controller@3881000 {
 548                         compatible = "arm,gic-400";
 549                         #interrupt-cells = <3>;
 550                         interrupt-controller;
 551                         reg = <0x03881000 0x1000>,
 552                               <0x03882000 0x2000>,
 553                               <0x03884000 0x2000>,
 554                               <0x03886000 0x2000>;
 555                         interrupts = <GIC_PPI 9
 556                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 557                         interrupt-parent = <&gic>;
 558                 };
 559
 560                 cec@3960000 {
 561                         compatible = "nvidia,tegra194-cec";
 562                         reg = <0x03960000 0x10000>;
 563                         interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
 564                         clocks = <&bpmp TEGRA194_CLK_CEC>;
 565                         clock-names = "cec";
 566                         status = "disabled";
 567                 };
 568
 569                 hsp_top0: hsp@3c00000 {
 570                         compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp";
 571                         reg = <0x03c00000 0xa0000>;
 572                         interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
 573                                      <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 574                                      <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 575                                      <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
 576                                      <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
 577                                      <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
 578                                      <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
 579                                      <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
 580                                      <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 581                         interrupt-names = "doorbell", "shared0", "shared1", "shared2",
 582                                           "shared3", "shared4", "shared5", "shared6",
 583                                           "shared7";
 584                         #mbox-cells = <2>;
 585                 };
 586
 587                 p2u_hsio_0: phy@3e10000 {
 588                         compatible = "nvidia,tegra194-p2u";
 589                         reg = <0x03e10000 0x10000>;
 590                         reg-names = "ctl";
 591
 592                         #phy-cells = <0>;
 593                 };
 594
 595                 p2u_hsio_1: phy@3e20000 {
 596                         compatible = "nvidia,tegra194-p2u";
 597                         reg = <0x03e20000 0x10000>;
 598                         reg-names = "ctl";
 599
 600                         #phy-cells = <0>;
 601                 };
 602
 603                 p2u_hsio_2: phy@3e30000 {
 604                         compatible = "nvidia,tegra194-p2u";
 605                         reg = <0x03e30000 0x10000>;
 606                         reg-names = "ctl";
 607
 608                         #phy-cells = <0>;
 609                 };
 610
 611                 p2u_hsio_3: phy@3e40000 {
 612                         compatible = "nvidia,tegra194-p2u";
 613                         reg = <0x03e40000 0x10000>;
 614                         reg-names = "ctl";
 615
 616                         #phy-cells = <0>;
 617                 };
 618
 619                 p2u_hsio_4: phy@3e50000 {
 620                         compatible = "nvidia,tegra194-p2u";
 621                         reg = <0x03e50000 0x10000>;
 622                         reg-names = "ctl";
 623
 624                         #phy-cells = <0>;
 625                 };
 626
 627                 p2u_hsio_5: phy@3e60000 {
 628                         compatible = "nvidia,tegra194-p2u";
 629                         reg = <0x03e60000 0x10000>;
 630                         reg-names = "ctl";
 631
 632                         #phy-cells = <0>;
 633                 };
 634
 635                 p2u_hsio_6: phy@3e70000 {
 636                         compatible = "nvidia,tegra194-p2u";
 637                         reg = <0x03e70000 0x10000>;
 638                         reg-names = "ctl";
 639
 640                         #phy-cells = <0>;
 641                 };
 642
 643                 p2u_hsio_7: phy@3e80000 {
 644                         compatible = "nvidia,tegra194-p2u";
 645                         reg = <0x03e80000 0x10000>;
 646                         reg-names = "ctl";
 647
 648                         #phy-cells = <0>;
 649                 };
 650
 651                 p2u_hsio_8: phy@3e90000 {
 652                         compatible = "nvidia,tegra194-p2u";
 653                         reg = <0x03e90000 0x10000>;
 654                         reg-names = "ctl";
 655
 656                         #phy-cells = <0>;
 657                 };
 658
 659                 p2u_hsio_9: phy@3ea0000 {
 660                         compatible = "nvidia,tegra194-p2u";
 661                         reg = <0x03ea0000 0x10000>;
 662                         reg-names = "ctl";
 663
 664                         #phy-cells = <0>;
 665                 };
 666
 667                 p2u_nvhs_0: phy@3eb0000 {
 668                         compatible = "nvidia,tegra194-p2u";
 669                         reg = <0x03eb0000 0x10000>;
 670                         reg-names = "ctl";
 671
 672                         #phy-cells = <0>;
 673                 };
 674
 675                 p2u_nvhs_1: phy@3ec0000 {
 676                         compatible = "nvidia,tegra194-p2u";
 677                         reg = <0x03ec0000 0x10000>;
 678                         reg-names = "ctl";
 679
 680                         #phy-cells = <0>;
 681                 };
 682
 683                 p2u_nvhs_2: phy@3ed0000 {
 684                         compatible = "nvidia,tegra194-p2u";
 685                         reg = <0x03ed0000 0x10000>;
 686                         reg-names = "ctl";
 687
 688                         #phy-cells = <0>;
 689                 };
 690
 691                 p2u_nvhs_3: phy@3ee0000 {
 692                         compatible = "nvidia,tegra194-p2u";
 693                         reg = <0x03ee0000 0x10000>;
 694                         reg-names = "ctl";
 695
 696                         #phy-cells = <0>;
 697                 };
 698
 699                 p2u_nvhs_4: phy@3ef0000 {
 700                         compatible = "nvidia,tegra194-p2u";
 701                         reg = <0x03ef0000 0x10000>;
 702                         reg-names = "ctl";
 703
 704                         #phy-cells = <0>;
 705                 };
 706
 707                 p2u_nvhs_5: phy@3f00000 {
 708                         compatible = "nvidia,tegra194-p2u";
 709                         reg = <0x03f00000 0x10000>;
 710                         reg-names = "ctl";
 711
 712                         #phy-cells = <0>;
 713                 };
 714
 715                 p2u_nvhs_6: phy@3f10000 {
 716                         compatible = "nvidia,tegra194-p2u";
 717                         reg = <0x03f10000 0x10000>;
 718                         reg-names = "ctl";
 719
 720                         #phy-cells = <0>;
 721                 };
 722
 723                 p2u_nvhs_7: phy@3f20000 {
 724                         compatible = "nvidia,tegra194-p2u";
 725                         reg = <0x03f20000 0x10000>;
 726                         reg-names = "ctl";
 727
 728                         #phy-cells = <0>;
 729                 };
 730
 731                 p2u_hsio_10: phy@3f30000 {
 732                         compatible = "nvidia,tegra194-p2u";
 733                         reg = <0x03f30000 0x10000>;
 734                         reg-names = "ctl";
 735
 736                         #phy-cells = <0>;
 737                 };
 738
 739                 p2u_hsio_11: phy@3f40000 {
 740                         compatible = "nvidia,tegra194-p2u";
 741                         reg = <0x03f40000 0x10000>;
 742                         reg-names = "ctl";
 743
 744                         #phy-cells = <0>;
 745                 };
 746
 747                 hsp_aon: hsp@c150000 {
 748                         compatible = "nvidia,tegra194-hsp", "nvidia,tegra186-hsp";
 749                         reg = <0x0c150000 0xa0000>;
 750                         interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
 751                                      <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 752                                      <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 753                                      <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
 754                         /*
 755                          * Shared interrupt 0 is routed only to AON/SPE, so
 756                          * we only have 4 shared interrupts for the CCPLEX.
 757                          */
 758                         interrupt-names = "shared1", "shared2", "shared3", "shared4";
 759                         #mbox-cells = <2>;
 760                 };
 761
 762                 gen2_i2c: i2c@c240000 {
 763                         compatible = "nvidia,tegra194-i2c";
 764                         reg = <0x0c240000 0x10000>;
 765                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 766                         #address-cells = <1>;
 767                         #size-cells = <0>;
 768                         clocks = <&bpmp TEGRA194_CLK_I2C2>;
 769                         clock-names = "div-clk";
 770                         resets = <&bpmp TEGRA194_RESET_I2C2>;
 771                         reset-names = "i2c";
 772                         status = "disabled";
 773                 };
 774
 775                 gen8_i2c: i2c@c250000 {
 776                         compatible = "nvidia,tegra194-i2c";
 777                         reg = <0x0c250000 0x10000>;
 778                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 779                         #address-cells = <1>;
 780                         #size-cells = <0>;
 781                         clocks = <&bpmp TEGRA194_CLK_I2C8>;
 782                         clock-names = "div-clk";
 783                         resets = <&bpmp TEGRA194_RESET_I2C8>;
 784                         reset-names = "i2c";
 785                         status = "disabled";
 786                 };
 787
 788                 uartc: serial@c280000 {
 789                         compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
 790                         reg = <0x0c280000 0x40>;
 791                         reg-shift = <2>;
 792                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 793                         clocks = <&bpmp TEGRA194_CLK_UARTC>;
 794                         clock-names = "serial";
 795                         resets = <&bpmp TEGRA194_RESET_UARTC>;
 796                         reset-names = "serial";
 797                         status = "disabled";
 798                 };
 799
 800                 uartg: serial@c290000 {
 801                         compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
 802                         reg = <0x0c290000 0x40>;
 803                         reg-shift = <2>;
 804                         interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
 805                         clocks = <&bpmp TEGRA194_CLK_UARTG>;
 806                         clock-names = "serial";
 807                         resets = <&bpmp TEGRA194_RESET_UARTG>;
 808                         reset-names = "serial";
 809                         status = "disabled";
 810                 };
 811
 812                 rtc: rtc@c2a0000 {
 813                         compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc";
 814                         reg = <0x0c2a0000 0x10000>;
 815                         interrupt-parent = <&pmc>;
 816                         interrupts = <73 IRQ_TYPE_LEVEL_HIGH>;
 817                         clocks = <&bpmp TEGRA194_CLK_CLK_32K>;
 818                         clock-names = "rtc";
 819                         status = "disabled";
 820                 };
 821
 822                 gpio_aon: gpio@c2f0000 {
 823                         compatible = "nvidia,tegra194-gpio-aon";
 824                         reg-names = "security", "gpio";
 825                         reg = <0xc2f0000 0x1000>,
 826                               <0xc2f1000 0x1000>;
 827                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
 828                                      <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
 829                                      <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
 830                                      <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 831                         gpio-controller;
 832                         #gpio-cells = <2>;
 833                         interrupt-controller;
 834                         #interrupt-cells = <2>;
 835                 };
 836
 837                 pwm4: pwm@c340000 {
 838                         compatible = "nvidia,tegra194-pwm",
 839                                      "nvidia,tegra186-pwm";
 840                         reg = <0xc340000 0x10000>;
 841                         clocks = <&bpmp TEGRA194_CLK_PWM4>;
 842                         clock-names = "pwm";
 843                         resets = <&bpmp TEGRA194_RESET_PWM4>;
 844                         reset-names = "pwm";
 845                         status = "disabled";
 846                         #pwm-cells = <2>;
 847                 };
 848
 849                 pmc: pmc@c360000 {
 850                         compatible = "nvidia,tegra194-pmc";
 851                         reg = <0x0c360000 0x10000>,
 852                               <0x0c370000 0x10000>,
 853                               <0x0c380000 0x10000>,
 854                               <0x0c390000 0x10000>,
 855                               <0x0c3a0000 0x10000>;
 856                         reg-names = "pmc", "wake", "aotag", "scratch", "misc";
 857
 858                         #interrupt-cells = <2>;
 859                         interrupt-controller;
 860                 };
 861
 862                 host1x@13e00000 {
 863                         compatible = "nvidia,tegra194-host1x", "simple-bus";
 864                         reg = <0x13e00000 0x10000>,
 865                               <0x13e10000 0x10000>;
 866                         reg-names = "hypervisor", "vm";
 867                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
 868                                      <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
 869                         clocks = <&bpmp TEGRA194_CLK_HOST1X>;
 870                         clock-names = "host1x";
 871                         resets = <&bpmp TEGRA194_RESET_HOST1X>;
 872                         reset-names = "host1x";
 873
 874                         #address-cells = <1>;
 875                         #size-cells = <1>;
 876
 877                         ranges = <0x15000000 0x15000000 0x01000000>;
 878
 879                         display-hub@15200000 {
 880                                 compatible = "nvidia,tegra194-display", "simple-bus";
 881                                 reg = <0x15200000 0x00040000>;
 882                                 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>,
 883                                          <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>,
 884                                          <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>,
 885                                          <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>,
 886                                          <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>,
 887                                          <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>,
 888                                          <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>;
 889                                 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
 890                                               "wgrp3", "wgrp4", "wgrp5";
 891                                 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>,
 892                                          <&bpmp TEGRA194_CLK_NVDISPLAYHUB>;
 893                                 clock-names = "disp", "hub";
 894                                 status = "disabled";
 895
 896                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
 897
 898                                 #address-cells = <1>;
 899                                 #size-cells = <1>;
 900
 901                                 ranges = <0x15200000 0x15200000 0x40000>;
 902
 903                                 display@15200000 {
 904                                         compatible = "nvidia,tegra194-dc";
 905                                         reg = <0x15200000 0x10000>;
 906                                         interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 907                                         clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>;
 908                                         clock-names = "dc";
 909                                         resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>;
 910                                         reset-names = "dc";
 911
 912                                         power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
 913
 914                                         nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
 915                                         nvidia,head = <0>;
 916                                 };
 917
 918                                 display@15210000 {
 919                                         compatible = "nvidia,tegra194-dc";
 920                                         reg = <0x15210000 0x10000>;
 921                                         interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 922                                         clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>;
 923                                         clock-names = "dc";
 924                                         resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>;
 925                                         reset-names = "dc";
 926
 927                                         power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>;
 928
 929                                         nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
 930                                         nvidia,head = <1>;
 931                                 };
 932
 933                                 display@15220000 {
 934                                         compatible = "nvidia,tegra194-dc";
 935                                         reg = <0x15220000 0x10000>;
 936                                         interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
 937                                         clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>;
 938                                         clock-names = "dc";
 939                                         resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>;
 940                                         reset-names = "dc";
 941
 942                                         power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
 943
 944                                         nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
 945                                         nvidia,head = <2>;
 946                                 };
 947
 948                                 display@15230000 {
 949                                         compatible = "nvidia,tegra194-dc";
 950                                         reg = <0x15230000 0x10000>;
 951                                         interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
 952                                         clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>;
 953                                         clock-names = "dc";
 954                                         resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>;
 955                                         reset-names = "dc";
 956
 957                                         power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
 958
 959                                         nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
 960                                         nvidia,head = <3>;
 961                                 };
 962                         };
 963
 964                         vic@15340000 {
 965                                 compatible = "nvidia,tegra194-vic";
 966                                 reg = <0x15340000 0x00040000>;
 967                                 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
 968                                 clocks = <&bpmp TEGRA194_CLK_VIC>;
 969                                 clock-names = "vic";
 970                                 resets = <&bpmp TEGRA194_RESET_VIC>;
 971                                 reset-names = "vic";
 972
 973                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>;
 974                         };
 975
 976                         dpaux0: dpaux@155c0000 {
 977                                 compatible = "nvidia,tegra194-dpaux";
 978                                 reg = <0x155c0000 0x10000>;
 979                                 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
 980                                 clocks = <&bpmp TEGRA194_CLK_DPAUX>,
 981                                          <&bpmp TEGRA194_CLK_PLLDP>;
 982                                 clock-names = "dpaux", "parent";
 983                                 resets = <&bpmp TEGRA194_RESET_DPAUX>;
 984                                 reset-names = "dpaux";
 985                                 status = "disabled";
 986
 987                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
 988
 989                                 state_dpaux0_aux: pinmux-aux {
 990                                         groups = "dpaux-io";
 991                                         function = "aux";
 992                                 };
 993
 994                                 state_dpaux0_i2c: pinmux-i2c {
 995                                         groups = "dpaux-io";
 996                                         function = "i2c";
 997                                 };
 998
 999                                 state_dpaux0_off: pinmux-off {
1000                                         groups = "dpaux-io";
1001                                         function = "off";
1002                                 };
1003
1004                                 i2c-bus {
1005                                         #address-cells = <1>;
1006                                         #size-cells = <0>;
1007                                 };
1008                         };
1009
1010                         dpaux1: dpaux@155d0000 {
1011                                 compatible = "nvidia,tegra194-dpaux";
1012                                 reg = <0x155d0000 0x10000>;
1013                                 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
1014                                 clocks = <&bpmp TEGRA194_CLK_DPAUX1>,
1015                                          <&bpmp TEGRA194_CLK_PLLDP>;
1016                                 clock-names = "dpaux", "parent";
1017                                 resets = <&bpmp TEGRA194_RESET_DPAUX1>;
1018                                 reset-names = "dpaux";
1019                                 status = "disabled";
1020
1021                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1022
1023                                 state_dpaux1_aux: pinmux-aux {
1024                                         groups = "dpaux-io";
1025                                         function = "aux";
1026                                 };
1027
1028                                 state_dpaux1_i2c: pinmux-i2c {
1029                                         groups = "dpaux-io";
1030                                         function = "i2c";
1031                                 };
1032
1033                                 state_dpaux1_off: pinmux-off {
1034                                         groups = "dpaux-io";
1035                                         function = "off";
1036                                 };
1037
1038                                 i2c-bus {
1039                                         #address-cells = <1>;
1040                                         #size-cells = <0>;
1041                                 };
1042                         };
1043
1044                         dpaux2: dpaux@155e0000 {
1045                                 compatible = "nvidia,tegra194-dpaux";
1046                                 reg = <0x155e0000 0x10000>;
1047                                 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
1048                                 clocks = <&bpmp TEGRA194_CLK_DPAUX2>,
1049                                          <&bpmp TEGRA194_CLK_PLLDP>;
1050                                 clock-names = "dpaux", "parent";
1051                                 resets = <&bpmp TEGRA194_RESET_DPAUX2>;
1052                                 reset-names = "dpaux";
1053                                 status = "disabled";
1054
1055                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1056
1057                                 state_dpaux2_aux: pinmux-aux {
1058                                         groups = "dpaux-io";
1059                                         function = "aux";
1060                                 };
1061
1062                                 state_dpaux2_i2c: pinmux-i2c {
1063                                         groups = "dpaux-io";
1064                                         function = "i2c";
1065                                 };
1066
1067                                 state_dpaux2_off: pinmux-off {
1068                                         groups = "dpaux-io";
1069                                         function = "off";
1070                                 };
1071
1072                                 i2c-bus {
1073                                         #address-cells = <1>;
1074                                         #size-cells = <0>;
1075                                 };
1076                         };
1077
1078                         dpaux3: dpaux@155f0000 {
1079                                 compatible = "nvidia,tegra194-dpaux";
1080                                 reg = <0x155f0000 0x10000>;
1081                                 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
1082                                 clocks = <&bpmp TEGRA194_CLK_DPAUX3>,
1083                                          <&bpmp TEGRA194_CLK_PLLDP>;
1084                                 clock-names = "dpaux", "parent";
1085                                 resets = <&bpmp TEGRA194_RESET_DPAUX3>;
1086                                 reset-names = "dpaux";
1087                                 status = "disabled";
1088
1089                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1090
1091                                 state_dpaux3_aux: pinmux-aux {
1092                                         groups = "dpaux-io";
1093                                         function = "aux";
1094                                 };
1095
1096                                 state_dpaux3_i2c: pinmux-i2c {
1097                                         groups = "dpaux-io";
1098                                         function = "i2c";
1099                                 };
1100
1101                                 state_dpaux3_off: pinmux-off {
1102                                         groups = "dpaux-io";
1103                                         function = "off";
1104                                 };
1105
1106                                 i2c-bus {
1107                                         #address-cells = <1>;
1108                                         #size-cells = <0>;
1109                                 };
1110                         };
1111
1112                         sor0: sor@15b00000 {
1113                                 compatible = "nvidia,tegra194-sor";
1114                                 reg = <0x15b00000 0x40000>;
1115                                 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1116                                 clocks = <&bpmp TEGRA194_CLK_SOR0_REF>,
1117                                          <&bpmp TEGRA194_CLK_SOR0_OUT>,
1118                                          <&bpmp TEGRA194_CLK_PLLD>,
1119                                          <&bpmp TEGRA194_CLK_PLLDP>,
1120                                          <&bpmp TEGRA194_CLK_SOR_SAFE>,
1121                                          <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>;
1122                                 clock-names = "sor", "out", "parent", "dp", "safe",
1123                                               "pad";
1124                                 resets = <&bpmp TEGRA194_RESET_SOR0>;
1125                                 reset-names = "sor";
1126                                 pinctrl-0 = <&state_dpaux0_aux>;
1127                                 pinctrl-1 = <&state_dpaux0_i2c>;
1128                                 pinctrl-2 = <&state_dpaux0_off>;
1129                                 pinctrl-names = "aux", "i2c", "off";
1130                                 status = "disabled";
1131
1132                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1133                                 nvidia,interface = <0>;
1134                         };
1135
1136                         sor1: sor@15b40000 {
1137                                 compatible = "nvidia,tegra194-sor";
1138                                 reg = <0x15b40000 0x40000>;
1139                                 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1140                                 clocks = <&bpmp TEGRA194_CLK_SOR1_REF>,
1141                                          <&bpmp TEGRA194_CLK_SOR1_OUT>,
1142                                          <&bpmp TEGRA194_CLK_PLLD2>,
1143                                          <&bpmp TEGRA194_CLK_PLLDP>,
1144                                          <&bpmp TEGRA194_CLK_SOR_SAFE>,
1145                                          <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>;
1146                                 clock-names = "sor", "out", "parent", "dp", "safe",
1147                                               "pad";
1148                                 resets = <&bpmp TEGRA194_RESET_SOR1>;
1149                                 reset-names = "sor";
1150                                 pinctrl-0 = <&state_dpaux1_aux>;
1151                                 pinctrl-1 = <&state_dpaux1_i2c>;
1152                                 pinctrl-2 = <&state_dpaux1_off>;
1153                                 pinctrl-names = "aux", "i2c", "off";
1154                                 status = "disabled";
1155
1156                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1157                                 nvidia,interface = <1>;
1158                         };
1159
1160                         sor2: sor@15b80000 {
1161                                 compatible = "nvidia,tegra194-sor";
1162                                 reg = <0x15b80000 0x40000>;
1163                                 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
1164                                 clocks = <&bpmp TEGRA194_CLK_SOR2_REF>,
1165                                          <&bpmp TEGRA194_CLK_SOR2_OUT>,
1166                                          <&bpmp TEGRA194_CLK_PLLD3>,
1167                                          <&bpmp TEGRA194_CLK_PLLDP>,
1168                                          <&bpmp TEGRA194_CLK_SOR_SAFE>,
1169                                          <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>;
1170                                 clock-names = "sor", "out", "parent", "dp", "safe",
1171                                               "pad";
1172                                 resets = <&bpmp TEGRA194_RESET_SOR2>;
1173                                 reset-names = "sor";
1174                                 pinctrl-0 = <&state_dpaux2_aux>;
1175                                 pinctrl-1 = <&state_dpaux2_i2c>;
1176                                 pinctrl-2 = <&state_dpaux2_off>;
1177                                 pinctrl-names = "aux", "i2c", "off";
1178                                 status = "disabled";
1179
1180                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1181                                 nvidia,interface = <2>;
1182                         };
1183
1184                         sor3: sor@15bc0000 {
1185                                 compatible = "nvidia,tegra194-sor";
1186                                 reg = <0x15bc0000 0x40000>;
1187                                 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
1188                                 clocks = <&bpmp TEGRA194_CLK_SOR3_REF>,
1189                                          <&bpmp TEGRA194_CLK_SOR3_OUT>,
1190                                          <&bpmp TEGRA194_CLK_PLLD4>,
1191                                          <&bpmp TEGRA194_CLK_PLLDP>,
1192                                          <&bpmp TEGRA194_CLK_SOR_SAFE>,
1193                                          <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>;
1194                                 clock-names = "sor", "out", "parent", "dp", "safe",
1195                                               "pad";
1196                                 resets = <&bpmp TEGRA194_RESET_SOR3>;
1197                                 reset-names = "sor";
1198                                 pinctrl-0 = <&state_dpaux3_aux>;
1199                                 pinctrl-1 = <&state_dpaux3_i2c>;
1200                                 pinctrl-2 = <&state_dpaux3_off>;
1201                                 pinctrl-names = "aux", "i2c", "off";
1202                                 status = "disabled";
1203
1204                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
1205                                 nvidia,interface = <3>;
1206                         };
1207                 };
1208         };
1209
1210         pcie@14100000 {
1211                 compatible = "nvidia,tegra194-pcie", "snps,dw-pcie";
1212                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
1213                 reg = <0x00 0x14100000 0x0 0x00020000   /* appl registers (128K)      */
1214                        0x00 0x30000000 0x0 0x00040000   /* configuration space (256K) */
1215                        0x00 0x30040000 0x0 0x00040000   /* iATU_DMA reg space (256K)  */
1216                        0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K)       */
1217                 reg-names = "appl", "config", "atu_dma", "dbi";
1218
1219                 status = "disabled";
1220
1221                 #address-cells = <3>;
1222                 #size-cells = <2>;
1223                 device_type = "pci";
1224                 num-lanes = <1>;
1225                 num-viewport = <8>;
1226                 linux,pci-domain = <1>;
1227
1228                 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_1>;
1229                 clock-names = "core";
1230
1231                 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_1_APB>,
1232                          <&bpmp TEGRA194_RESET_PEX0_CORE_1>;
1233                 reset-names = "apb", "core";
1234
1235                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,  /* controller interrupt */
1236                              <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;  /* MSI interrupt */
1237                 interrupt-names = "intr", "msi";
1238
1239                 #interrupt-cells = <1>;
1240                 interrupt-map-mask = <0 0 0 0>;
1241                 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1242
1243                 nvidia,bpmp = <&bpmp 1>;
1244
1245                 nvidia,aspm-cmrt-us = <60>;
1246                 nvidia,aspm-pwr-on-t-us = <20>;
1247                 nvidia,aspm-l0s-entrance-latency-us = <3>;
1248
1249                 bus-range = <0x0 0xff>;
1250                 ranges = <0x81000000 0x0  0x30100000 0x0  0x30100000 0x0 0x00100000   /* downstream I/O (1MB) */
1251                           0xc2000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000   /* prefetchable memory (768MB) */
1252                           0x82000000 0x0  0x40000000 0x12 0x30000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */
1253         };
1254
1255         pcie@14120000 {
1256                 compatible = "nvidia,tegra194-pcie", "snps,dw-pcie";
1257                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
1258                 reg = <0x00 0x14120000 0x0 0x00020000   /* appl registers (128K)      */
1259                        0x00 0x32000000 0x0 0x00040000   /* configuration space (256K) */
1260                        0x00 0x32040000 0x0 0x00040000   /* iATU_DMA reg space (256K)  */
1261                        0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K)       */
1262                 reg-names = "appl", "config", "atu_dma", "dbi";
1263
1264                 status = "disabled";
1265
1266                 #address-cells = <3>;
1267                 #size-cells = <2>;
1268                 device_type = "pci";
1269                 num-lanes = <1>;
1270                 num-viewport = <8>;
1271                 linux,pci-domain = <2>;
1272
1273                 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_2>;
1274                 clock-names = "core";
1275
1276                 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_2_APB>,
1277                          <&bpmp TEGRA194_RESET_PEX0_CORE_2>;
1278                 reset-names = "apb", "core";
1279
1280                 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,  /* controller interrupt */
1281                              <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;  /* MSI interrupt */
1282                 interrupt-names = "intr", "msi";
1283
1284                 #interrupt-cells = <1>;
1285                 interrupt-map-mask = <0 0 0 0>;
1286                 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1287
1288                 nvidia,bpmp = <&bpmp 2>;
1289
1290                 nvidia,aspm-cmrt-us = <60>;
1291                 nvidia,aspm-pwr-on-t-us = <20>;
1292                 nvidia,aspm-l0s-entrance-latency-us = <3>;
1293
1294                 bus-range = <0x0 0xff>;
1295                 ranges = <0x81000000 0x0  0x32100000 0x0  0x32100000 0x0 0x00100000   /* downstream I/O (1MB) */
1296                           0xc2000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000   /* prefetchable memory (768MB) */
1297                           0x82000000 0x0  0x40000000 0x12 0x70000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */
1298         };
1299
1300         pcie@14140000 {
1301                 compatible = "nvidia,tegra194-pcie", "snps,dw-pcie";
1302                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX1A>;
1303                 reg = <0x00 0x14140000 0x0 0x00020000   /* appl registers (128K)      */
1304                        0x00 0x34000000 0x0 0x00040000   /* configuration space (256K) */
1305                        0x00 0x34040000 0x0 0x00040000   /* iATU_DMA reg space (256K)  */
1306                        0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K)       */
1307                 reg-names = "appl", "config", "atu_dma", "dbi";
1308
1309                 status = "disabled";
1310
1311                 #address-cells = <3>;
1312                 #size-cells = <2>;
1313                 device_type = "pci";
1314                 num-lanes = <1>;
1315                 num-viewport = <8>;
1316                 linux,pci-domain = <3>;
1317
1318                 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_3>;
1319                 clock-names = "core";
1320
1321                 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_3_APB>,
1322                          <&bpmp TEGRA194_RESET_PEX0_CORE_3>;
1323                 reset-names = "apb", "core";
1324
1325                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,  /* controller interrupt */
1326                              <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;  /* MSI interrupt */
1327                 interrupt-names = "intr", "msi";
1328
1329                 #interrupt-cells = <1>;
1330                 interrupt-map-mask = <0 0 0 0>;
1331                 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1332
1333                 nvidia,bpmp = <&bpmp 3>;
1334
1335                 nvidia,aspm-cmrt-us = <60>;
1336                 nvidia,aspm-pwr-on-t-us = <20>;
1337                 nvidia,aspm-l0s-entrance-latency-us = <3>;
1338
1339                 bus-range = <0x0 0xff>;
1340                 ranges = <0x81000000 0x0  0x34100000 0x0  0x34100000 0x0 0x00100000   /* downstream I/O (1MB) */
1341                           0xc2000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000   /* prefetchable memory (768MB) */
1342                           0x82000000 0x0  0x40000000 0x12 0xb0000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */
1343         };
1344
1345         pcie@14160000 {
1346                 compatible = "nvidia,tegra194-pcie", "snps,dw-pcie";
1347                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
1348                 reg = <0x00 0x14160000 0x0 0x00020000   /* appl registers (128K)      */
1349                        0x00 0x36000000 0x0 0x00040000   /* configuration space (256K) */
1350                        0x00 0x36040000 0x0 0x00040000   /* iATU_DMA reg space (256K)  */
1351                        0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K)       */
1352                 reg-names = "appl", "config", "atu_dma", "dbi";
1353
1354                 status = "disabled";
1355
1356                 #address-cells = <3>;
1357                 #size-cells = <2>;
1358                 device_type = "pci";
1359                 num-lanes = <4>;
1360                 num-viewport = <8>;
1361                 linux,pci-domain = <4>;
1362
1363                 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_4>;
1364                 clock-names = "core";
1365
1366                 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_4_APB>,
1367                          <&bpmp TEGRA194_RESET_PEX0_CORE_4>;
1368                 reset-names = "apb", "core";
1369
1370                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,  /* controller interrupt */
1371                              <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;  /* MSI interrupt */
1372                 interrupt-names = "intr", "msi";
1373
1374                 #interrupt-cells = <1>;
1375                 interrupt-map-mask = <0 0 0 0>;
1376                 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1377
1378                 nvidia,bpmp = <&bpmp 4>;
1379
1380                 nvidia,aspm-cmrt-us = <60>;
1381                 nvidia,aspm-pwr-on-t-us = <20>;
1382                 nvidia,aspm-l0s-entrance-latency-us = <3>;
1383
1384                 bus-range = <0x0 0xff>;
1385                 ranges = <0x81000000 0x0  0x36100000 0x0  0x36100000 0x0 0x00100000   /* downstream I/O (1MB) */
1386                           0xc2000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000   /* prefetchable memory (13GB) */
1387                           0x82000000 0x0  0x40000000 0x17 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */
1388         };
1389
1390         pcie@14180000 {
1391                 compatible = "nvidia,tegra194-pcie", "snps,dw-pcie";
1392                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
1393                 reg = <0x00 0x14180000 0x0 0x00020000   /* appl registers (128K)      */
1394                        0x00 0x38000000 0x0 0x00040000   /* configuration space (256K) */
1395                        0x00 0x38040000 0x0 0x00040000   /* iATU_DMA reg space (256K)  */
1396                        0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K)       */
1397                 reg-names = "appl", "config", "atu_dma", "dbi";
1398
1399                 status = "disabled";
1400
1401                 #address-cells = <3>;
1402                 #size-cells = <2>;
1403                 device_type = "pci";
1404                 num-lanes = <8>;
1405                 num-viewport = <8>;
1406                 linux,pci-domain = <0>;
1407
1408                 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
1409                 clock-names = "core";
1410
1411                 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
1412                          <&bpmp TEGRA194_RESET_PEX0_CORE_0>;
1413                 reset-names = "apb", "core";
1414
1415                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,  /* controller interrupt */
1416                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;  /* MSI interrupt */
1417                 interrupt-names = "intr", "msi";
1418
1419                 #interrupt-cells = <1>;
1420                 interrupt-map-mask = <0 0 0 0>;
1421                 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1422
1423                 nvidia,bpmp = <&bpmp 0>;
1424
1425                 nvidia,aspm-cmrt-us = <60>;
1426                 nvidia,aspm-pwr-on-t-us = <20>;
1427                 nvidia,aspm-l0s-entrance-latency-us = <3>;
1428
1429                 bus-range = <0x0 0xff>;
1430                 ranges = <0x81000000 0x0  0x38100000 0x0  0x38100000 0x0 0x00100000   /* downstream I/O (1MB) */
1431                           0xc2000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000   /* prefetchable memory (13GB) */
1432                           0x82000000 0x0  0x40000000 0x1b 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */
1433         };
1434
1435         pcie@141a0000 {
1436                 compatible = "nvidia,tegra194-pcie", "snps,dw-pcie";
1437                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
1438                 reg = <0x00 0x141a0000 0x0 0x00020000   /* appl registers (128K)      */
1439                        0x00 0x3a000000 0x0 0x00040000   /* configuration space (256K) */
1440                        0x00 0x3a040000 0x0 0x00040000   /* iATU_DMA reg space (256K)  */
1441                        0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K)       */
1442                 reg-names = "appl", "config", "atu_dma", "dbi";
1443
1444                 status = "disabled";
1445
1446                 #address-cells = <3>;
1447                 #size-cells = <2>;
1448                 device_type = "pci";
1449                 num-lanes = <8>;
1450                 num-viewport = <8>;
1451                 linux,pci-domain = <5>;
1452
1453                 pinctrl-names = "default";
1454                 pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>;
1455
1456                 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>,
1457                         <&bpmp TEGRA194_CLK_PEX1_CORE_5M>;
1458                 clock-names = "core", "core_m";
1459
1460                 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
1461                          <&bpmp TEGRA194_RESET_PEX1_CORE_5>;
1462                 reset-names = "apb", "core";
1463
1464                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,  /* controller interrupt */
1465                              <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;  /* MSI interrupt */
1466                 interrupt-names = "intr", "msi";
1467
1468                 nvidia,bpmp = <&bpmp 5>;
1469
1470                 #interrupt-cells = <1>;
1471                 interrupt-map-mask = <0 0 0 0>;
1472                 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1473
1474                 nvidia,aspm-cmrt-us = <60>;
1475                 nvidia,aspm-pwr-on-t-us = <20>;
1476                 nvidia,aspm-l0s-entrance-latency-us = <3>;
1477
1478                 bus-range = <0x0 0xff>;
1479                 ranges = <0x81000000 0x0  0x3a100000 0x0  0x3a100000 0x0 0x00100000   /* downstream I/O (1MB) */
1480                           0xc2000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000   /* prefetchable memory (13GB) */
1481                           0x82000000 0x0  0x40000000 0x1f 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */
1482         };
1483
1484         sysram@40000000 {
1485                 compatible = "nvidia,tegra194-sysram", "mmio-sram";
1486                 reg = <0x0 0x40000000 0x0 0x50000>;
1487                 #address-cells = <1>;
1488                 #size-cells = <1>;
1489                 ranges = <0x0 0x0 0x40000000 0x50000>;
1490
1491                 cpu_bpmp_tx: shmem@4e000 {
1492                         compatible = "nvidia,tegra194-bpmp-shmem";
1493                         reg = <0x4e000 0x1000>;
1494                         label = "cpu-bpmp-tx";
1495                         pool;
1496                 };
1497
1498                 cpu_bpmp_rx: shmem@4f000 {
1499                         compatible = "nvidia,tegra194-bpmp-shmem";
1500                         reg = <0x4f000 0x1000>;
1501                         label = "cpu-bpmp-rx";
1502                         pool;
1503                 };
1504         };
1505
1506         bpmp: bpmp {
1507                 compatible = "nvidia,tegra186-bpmp";
1508                 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
1509                                     TEGRA_HSP_DB_MASTER_BPMP>;
1510                 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
1511                 #clock-cells = <1>;
1512                 #reset-cells = <1>;
1513                 #power-domain-cells = <1>;
1514
1515                 bpmp_i2c: i2c {
1516                         compatible = "nvidia,tegra186-bpmp-i2c";
1517                         nvidia,bpmp-bus-id = <5>;
1518                         #address-cells = <1>;
1519                         #size-cells = <0>;
1520                 };
1521
1522                 bpmp_thermal: thermal {
1523                         compatible = "nvidia,tegra186-bpmp-thermal";
1524                         #thermal-sensor-cells = <1>;
1525                 };
1526         };
1527
1528         cpus {
1529                 #address-cells = <1>;
1530                 #size-cells = <0>;
1531
1532                 cpu0_0: cpu@0 {
1533                         compatible = "nvidia,tegra194-carmel";
1534                         device_type = "cpu";
1535                         reg = <0x000>;
1536                         enable-method = "psci";
1537                         i-cache-size = <131072>;
1538                         i-cache-line-size = <64>;
1539                         i-cache-sets = <512>;
1540                         d-cache-size = <65536>;
1541                         d-cache-line-size = <64>;
1542                         d-cache-sets = <256>;
1543                         next-level-cache = <&l2c_0>;
1544                 };
1545
1546                 cpu0_1: cpu@1 {
1547                         compatible = "nvidia,tegra194-carmel";
1548                         device_type = "cpu";
1549                         reg = <0x001>;
1550                         enable-method = "psci";
1551                         i-cache-size = <131072>;
1552                         i-cache-line-size = <64>;
1553                         i-cache-sets = <512>;
1554                         d-cache-size = <65536>;
1555                         d-cache-line-size = <64>;
1556                         d-cache-sets = <256>;
1557                         next-level-cache = <&l2c_0>;
1558                 };
1559
1560                 cpu1_0: cpu@100 {
1561                         compatible = "nvidia,tegra194-carmel";
1562                         device_type = "cpu";
1563                         reg = <0x100>;
1564                         enable-method = "psci";
1565                         i-cache-size = <131072>;
1566                         i-cache-line-size = <64>;
1567                         i-cache-sets = <512>;
1568                         d-cache-size = <65536>;
1569                         d-cache-line-size = <64>;
1570                         d-cache-sets = <256>;
1571                         next-level-cache = <&l2c_1>;
1572                 };
1573
1574                 cpu1_1: cpu@101 {
1575                         compatible = "nvidia,tegra194-carmel";
1576                         device_type = "cpu";
1577                         reg = <0x101>;
1578                         enable-method = "psci";
1579                         i-cache-size = <131072>;
1580                         i-cache-line-size = <64>;
1581                         i-cache-sets = <512>;
1582                         d-cache-size = <65536>;
1583                         d-cache-line-size = <64>;
1584                         d-cache-sets = <256>;
1585                         next-level-cache = <&l2c_1>;
1586                 };
1587
1588                 cpu2_0: cpu@200 {
1589                         compatible = "nvidia,tegra194-carmel";
1590                         device_type = "cpu";
1591                         reg = <0x200>;
1592                         enable-method = "psci";
1593                         i-cache-size = <131072>;
1594                         i-cache-line-size = <64>;
1595                         i-cache-sets = <512>;
1596                         d-cache-size = <65536>;
1597                         d-cache-line-size = <64>;
1598                         d-cache-sets = <256>;
1599                         next-level-cache = <&l2c_2>;
1600                 };
1601
1602                 cpu2_1: cpu@201 {
1603                         compatible = "nvidia,tegra194-carmel";
1604                         device_type = "cpu";
1605                         reg = <0x201>;
1606                         enable-method = "psci";
1607                         i-cache-size = <131072>;
1608                         i-cache-line-size = <64>;
1609                         i-cache-sets = <512>;
1610                         d-cache-size = <65536>;
1611                         d-cache-line-size = <64>;
1612                         d-cache-sets = <256>;
1613                         next-level-cache = <&l2c_2>;
1614                 };
1615
1616                 cpu3_0: cpu@300 {
1617                         compatible = "nvidia,tegra194-carmel";
1618                         device_type = "cpu";
1619                         reg = <0x300>;
1620                         enable-method = "psci";
1621                         i-cache-size = <131072>;
1622                         i-cache-line-size = <64>;
1623                         i-cache-sets = <512>;
1624                         d-cache-size = <65536>;
1625                         d-cache-line-size = <64>;
1626                         d-cache-sets = <256>;
1627                         next-level-cache = <&l2c_3>;
1628                 };
1629
1630                 cpu3_1: cpu@301 {
1631                         compatible = "nvidia,tegra194-carmel";
1632                         device_type = "cpu";
1633                         reg = <0x301>;
1634                         enable-method = "psci";
1635                         i-cache-size = <131072>;
1636                         i-cache-line-size = <64>;
1637                         i-cache-sets = <512>;
1638                         d-cache-size = <65536>;
1639                         d-cache-line-size = <64>;
1640                         d-cache-sets = <256>;
1641                         next-level-cache = <&l2c_3>;
1642                 };
1643
1644                 cpu-map {
1645                         cluster0 {
1646                                 core0 {
1647                                         cpu = <&cpu0_0>;
1648                                 };
1649
1650                                 core1 {
1651                                         cpu = <&cpu0_1>;
1652                                 };
1653                         };
1654
1655                         cluster1 {
1656                                 core0 {
1657                                         cpu = <&cpu1_0>;
1658                                 };
1659
1660                                 core1 {
1661                                         cpu = <&cpu1_1>;
1662                                 };
1663                         };
1664
1665                         cluster2 {
1666                                 core0 {
1667                                         cpu = <&cpu2_0>;
1668                                 };
1669
1670                                 core1 {
1671                                         cpu = <&cpu2_1>;
1672                                 };
1673                         };
1674
1675                         cluster3 {
1676                                 core0 {
1677                                         cpu = <&cpu3_0>;
1678                                 };
1679
1680                                 core1 {
1681                                         cpu = <&cpu3_1>;
1682                                 };
1683                         };
1684                 };
1685
1686                 l2c_0: l2-cache0 {
1687                         cache-size = <2097152>;
1688                         cache-line-size = <64>;
1689                         cache-sets = <2048>;
1690                         next-level-cache = <&l3c>;
1691                 };
1692
1693                 l2c_1: l2-cache1 {
1694                         cache-size = <2097152>;
1695                         cache-line-size = <64>;
1696                         cache-sets = <2048>;
1697                         next-level-cache = <&l3c>;
1698                 };
1699
1700                 l2c_2: l2-cache2 {
1701                         cache-size = <2097152>;
1702                         cache-line-size = <64>;
1703                         cache-sets = <2048>;
1704                         next-level-cache = <&l3c>;
1705                 };
1706
1707                 l2c_3: l2-cache3 {
1708                         cache-size = <2097152>;
1709                         cache-line-size = <64>;
1710                         cache-sets = <2048>;
1711                         next-level-cache = <&l3c>;
1712                 };
1713
1714                 l3c: l3-cache {
1715                         cache-size = <4194304>;
1716                         cache-line-size = <64>;
1717                         cache-sets = <4096>;
1718                 };
1719         };
1720
1721         psci {
1722                 compatible = "arm,psci-1.0";
1723                 status = "okay";
1724                 method = "smc";
1725         };
1726
1727         tcu: tcu {
1728                 compatible = "nvidia,tegra194-tcu";
1729                 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>,
1730                          <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>;
1731                 mbox-names = "rx", "tx";
1732         };
1733
1734         thermal-zones {
1735                 cpu {
1736                         thermal-sensors = <&{/bpmp/thermal}
1737                                            TEGRA194_BPMP_THERMAL_ZONE_CPU>;
1738                         status = "disabled";
1739                 };
1740
1741                 gpu {
1742                         thermal-sensors = <&{/bpmp/thermal}
1743                                            TEGRA194_BPMP_THERMAL_ZONE_GPU>;
1744                         status = "disabled";
1745                 };
1746
1747                 aux {
1748                         thermal-sensors = <&{/bpmp/thermal}
1749                                            TEGRA194_BPMP_THERMAL_ZONE_AUX>;
1750                         status = "disabled";
1751                 };
1752
1753                 pllx {
1754                         thermal-sensors = <&{/bpmp/thermal}
1755                                            TEGRA194_BPMP_THERMAL_ZONE_PLLX>;
1756                         status = "disabled";
1757                 };
1758
1759                 ao {
1760                         thermal-sensors = <&{/bpmp/thermal}
1761                                            TEGRA194_BPMP_THERMAL_ZONE_AO>;
1762                         status = "disabled";
1763                 };
1764
1765                 tj {
1766                         thermal-sensors = <&{/bpmp/thermal}
1767                                            TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>;
1768                         status = "disabled";
1769                 };
1770         };
1771
1772         timer {
1773                 compatible = "arm,armv8-timer";
1774                 interrupts = <GIC_PPI 13
1775                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1776                              <GIC_PPI 14
1777                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1778                              <GIC_PPI 11
1779                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1780                              <GIC_PPI 10
1781                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1782                 interrupt-parent = <&gic>;
1783                 always-on;
1784         };
1785 };