sys/gnu/dts/arm64/nvidia/tegra194.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include <dt-bindings/clock/tegra194-clock.h>
   3 #include <dt-bindings/gpio/tegra194-gpio.h>
   4 #include <dt-bindings/interrupt-controller/arm-gic.h>
   5 #include <dt-bindings/mailbox/tegra186-hsp.h>
   6 #include <dt-bindings/reset/tegra194-reset.h>
   7 #include <dt-bindings/power/tegra194-powergate.h>
   8 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
   9
  10 / {
  11         compatible = "nvidia,tegra194";
  12         interrupt-parent = <&gic>;
  13         #address-cells = <2>;
  14         #size-cells = <2>;
  15
  16         /* control backbone */
  17         cbb {
  18                 compatible = "simple-bus";
  19                 #address-cells = <1>;
  20                 #size-cells = <1>;
  21                 ranges = <0x0 0x0 0x0 0x40000000>;
  22
  23                 gpio: gpio@2200000 {
  24                         compatible = "nvidia,tegra194-gpio";
  25                         reg-names = "security", "gpio";
  26                         reg = <0x2200000 0x10000>,
  27                               <0x2210000 0x10000>;
  28                         interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
  29                                      <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
  30                                      <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
  31                                      <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
  32                                      <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
  33                                      <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
  34                         #interrupt-cells = <2>;
  35                         interrupt-controller;
  36                         #gpio-cells = <2>;
  37                         gpio-controller;
  38                 };
  39
  40                 ethernet@2490000 {
  41                         compatible = "nvidia,tegra186-eqos",
  42                                      "snps,dwc-qos-ethernet-4.10";
  43                         reg = <0x02490000 0x10000>;
  44                         interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
  45                         clocks = <&bpmp TEGRA194_CLK_AXI_CBB>,
  46                                  <&bpmp TEGRA194_CLK_EQOS_AXI>,
  47                                  <&bpmp TEGRA194_CLK_EQOS_RX>,
  48                                  <&bpmp TEGRA194_CLK_EQOS_TX>,
  49                                  <&bpmp TEGRA194_CLK_EQOS_PTP_REF>;
  50                         clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref";
  51                         resets = <&bpmp TEGRA194_RESET_EQOS>;
  52                         reset-names = "eqos";
  53                         status = "disabled";
  54
  55                         snps,write-requests = <1>;
  56                         snps,read-requests = <3>;
  57                         snps,burst-map = <0x7>;
  58                         snps,txpbl = <16>;
  59                         snps,rxpbl = <8>;
  60                 };
  61
  62                 uarta: serial@3100000 {
  63                         compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
  64                         reg = <0x03100000 0x40>;
  65                         reg-shift = <2>;
  66                         interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
  67                         clocks = <&bpmp TEGRA194_CLK_UARTA>;
  68                         clock-names = "serial";
  69                         resets = <&bpmp TEGRA194_RESET_UARTA>;
  70                         reset-names = "serial";
  71                         status = "disabled";
  72                 };
  73
  74                 uartb: serial@3110000 {
  75                         compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
  76                         reg = <0x03110000 0x40>;
  77                         reg-shift = <2>;
  78                         interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
  79                         clocks = <&bpmp TEGRA194_CLK_UARTB>;
  80                         clock-names = "serial";
  81                         resets = <&bpmp TEGRA194_RESET_UARTB>;
  82                         reset-names = "serial";
  83                         status = "disabled";
  84                 };
  85
  86                 uartd: serial@3130000 {
  87                         compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
  88                         reg = <0x03130000 0x40>;
  89                         reg-shift = <2>;
  90                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
  91                         clocks = <&bpmp TEGRA194_CLK_UARTD>;
  92                         clock-names = "serial";
  93                         resets = <&bpmp TEGRA194_RESET_UARTD>;
  94                         reset-names = "serial";
  95                         status = "disabled";
  96                 };
  97
  98                 uarte: serial@3140000 {
  99                         compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
 100                         reg = <0x03140000 0x40>;
 101                         reg-shift = <2>;
 102                         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 103                         clocks = <&bpmp TEGRA194_CLK_UARTE>;
 104                         clock-names = "serial";
 105                         resets = <&bpmp TEGRA194_RESET_UARTE>;
 106                         reset-names = "serial";
 107                         status = "disabled";
 108                 };
 109
 110                 uartf: serial@3150000 {
 111                         compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
 112                         reg = <0x03150000 0x40>;
 113                         reg-shift = <2>;
 114                         interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 115                         clocks = <&bpmp TEGRA194_CLK_UARTF>;
 116                         clock-names = "serial";
 117                         resets = <&bpmp TEGRA194_RESET_UARTF>;
 118                         reset-names = "serial";
 119                         status = "disabled";
 120                 };
 121
 122                 gen1_i2c: i2c@3160000 {
 123                         compatible = "nvidia,tegra194-i2c";
 124                         reg = <0x03160000 0x10000>;
 125                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 126                         #address-cells = <1>;
 127                         #size-cells = <0>;
 128                         clocks = <&bpmp TEGRA194_CLK_I2C1>;
 129                         clock-names = "div-clk";
 130                         resets = <&bpmp TEGRA194_RESET_I2C1>;
 131                         reset-names = "i2c";
 132                         status = "disabled";
 133                 };
 134
 135                 uarth: serial@3170000 {
 136                         compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
 137                         reg = <0x03170000 0x40>;
 138                         reg-shift = <2>;
 139                         interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
 140                         clocks = <&bpmp TEGRA194_CLK_UARTH>;
 141                         clock-names = "serial";
 142                         resets = <&bpmp TEGRA194_RESET_UARTH>;
 143                         reset-names = "serial";
 144                         status = "disabled";
 145                 };
 146
 147                 cam_i2c: i2c@3180000 {
 148                         compatible = "nvidia,tegra194-i2c";
 149                         reg = <0x03180000 0x10000>;
 150                         interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 151                         #address-cells = <1>;
 152                         #size-cells = <0>;
 153                         clocks = <&bpmp TEGRA194_CLK_I2C3>;
 154                         clock-names = "div-clk";
 155                         resets = <&bpmp TEGRA194_RESET_I2C3>;
 156                         reset-names = "i2c";
 157                         status = "disabled";
 158                 };
 159
 160                 /* shares pads with dpaux1 */
 161                 dp_aux_ch1_i2c: i2c@3190000 {
 162                         compatible = "nvidia,tegra194-i2c";
 163                         reg = <0x03190000 0x10000>;
 164                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 165                         #address-cells = <1>;
 166                         #size-cells = <0>;
 167                         clocks = <&bpmp TEGRA194_CLK_I2C4>;
 168                         clock-names = "div-clk";
 169                         resets = <&bpmp TEGRA194_RESET_I2C4>;
 170                         reset-names = "i2c";
 171                         status = "disabled";
 172                 };
 173
 174                 /* shares pads with dpaux0 */
 175                 dp_aux_ch0_i2c: i2c@31b0000 {
 176                         compatible = "nvidia,tegra194-i2c";
 177                         reg = <0x031b0000 0x10000>;
 178                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 179                         #address-cells = <1>;
 180                         #size-cells = <0>;
 181                         clocks = <&bpmp TEGRA194_CLK_I2C6>;
 182                         clock-names = "div-clk";
 183                         resets = <&bpmp TEGRA194_RESET_I2C6>;
 184                         reset-names = "i2c";
 185                         status = "disabled";
 186                 };
 187
 188                 gen7_i2c: i2c@31c0000 {
 189                         compatible = "nvidia,tegra194-i2c";
 190                         reg = <0x031c0000 0x10000>;
 191                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 192                         #address-cells = <1>;
 193                         #size-cells = <0>;
 194                         clocks = <&bpmp TEGRA194_CLK_I2C7>;
 195                         clock-names = "div-clk";
 196                         resets = <&bpmp TEGRA194_RESET_I2C7>;
 197                         reset-names = "i2c";
 198                         status = "disabled";
 199                 };
 200
 201                 gen9_i2c: i2c@31e0000 {
 202                         compatible = "nvidia,tegra194-i2c";
 203                         reg = <0x031e0000 0x10000>;
 204                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 205                         #address-cells = <1>;
 206                         #size-cells = <0>;
 207                         clocks = <&bpmp TEGRA194_CLK_I2C9>;
 208                         clock-names = "div-clk";
 209                         resets = <&bpmp TEGRA194_RESET_I2C9>;
 210                         reset-names = "i2c";
 211                         status = "disabled";
 212                 };
 213
 214                 pwm1: pwm@3280000 {
 215                         compatible = "nvidia,tegra194-pwm",
 216                                      "nvidia,tegra186-pwm";
 217                         reg = <0x3280000 0x10000>;
 218                         clocks = <&bpmp TEGRA194_CLK_PWM1>;
 219                         clock-names = "pwm";
 220                         resets = <&bpmp TEGRA194_RESET_PWM1>;
 221                         reset-names = "pwm";
 222                         status = "disabled";
 223                         #pwm-cells = <2>;
 224                 };
 225
 226                 pwm2: pwm@3290000 {
 227                         compatible = "nvidia,tegra194-pwm",
 228                                      "nvidia,tegra186-pwm";
 229                         reg = <0x3290000 0x10000>;
 230                         clocks = <&bpmp TEGRA194_CLK_PWM2>;
 231                         clock-names = "pwm";
 232                         resets = <&bpmp TEGRA194_RESET_PWM2>;
 233                         reset-names = "pwm";
 234                         status = "disabled";
 235                         #pwm-cells = <2>;
 236                 };
 237
 238                 pwm3: pwm@32a0000 {
 239                         compatible = "nvidia,tegra194-pwm",
 240                                      "nvidia,tegra186-pwm";
 241                         reg = <0x32a0000 0x10000>;
 242                         clocks = <&bpmp TEGRA194_CLK_PWM3>;
 243                         clock-names = "pwm";
 244                         resets = <&bpmp TEGRA194_RESET_PWM3>;
 245                         reset-names = "pwm";
 246                         status = "disabled";
 247                         #pwm-cells = <2>;
 248                 };
 249
 250                 pwm5: pwm@32c0000 {
 251                         compatible = "nvidia,tegra194-pwm",
 252                                      "nvidia,tegra186-pwm";
 253                         reg = <0x32c0000 0x10000>;
 254                         clocks = <&bpmp TEGRA194_CLK_PWM5>;
 255                         clock-names = "pwm";
 256                         resets = <&bpmp TEGRA194_RESET_PWM5>;
 257                         reset-names = "pwm";
 258                         status = "disabled";
 259                         #pwm-cells = <2>;
 260                 };
 261
 262                 pwm6: pwm@32d0000 {
 263                         compatible = "nvidia,tegra194-pwm",
 264                                      "nvidia,tegra186-pwm";
 265                         reg = <0x32d0000 0x10000>;
 266                         clocks = <&bpmp TEGRA194_CLK_PWM6>;
 267                         clock-names = "pwm";
 268                         resets = <&bpmp TEGRA194_RESET_PWM6>;
 269                         reset-names = "pwm";
 270                         status = "disabled";
 271                         #pwm-cells = <2>;
 272                 };
 273
 274                 pwm7: pwm@32e0000 {
 275                         compatible = "nvidia,tegra194-pwm",
 276                                      "nvidia,tegra186-pwm";
 277                         reg = <0x32e0000 0x10000>;
 278                         clocks = <&bpmp TEGRA194_CLK_PWM7>;
 279                         clock-names = "pwm";
 280                         resets = <&bpmp TEGRA194_RESET_PWM7>;
 281                         reset-names = "pwm";
 282                         status = "disabled";
 283                         #pwm-cells = <2>;
 284                 };
 285
 286                 pwm8: pwm@32f0000 {
 287                         compatible = "nvidia,tegra194-pwm",
 288                                      "nvidia,tegra186-pwm";
 289                         reg = <0x32f0000 0x10000>;
 290                         clocks = <&bpmp TEGRA194_CLK_PWM8>;
 291                         clock-names = "pwm";
 292                         resets = <&bpmp TEGRA194_RESET_PWM8>;
 293                         reset-names = "pwm";
 294                         status = "disabled";
 295                         #pwm-cells = <2>;
 296                 };
 297
 298                 sdmmc1: sdhci@3400000 {
 299                         compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci";
 300                         reg = <0x03400000 0x10000>;
 301                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 302                         clocks = <&bpmp TEGRA194_CLK_SDMMC1>;
 303                         clock-names = "sdhci";
 304                         resets = <&bpmp TEGRA194_RESET_SDMMC1>;
 305                         reset-names = "sdhci";
 306                         status = "disabled";
 307                 };
 308
 309                 sdmmc3: sdhci@3440000 {
 310                         compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci";
 311                         reg = <0x03440000 0x10000>;
 312                         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 313                         clocks = <&bpmp TEGRA194_CLK_SDMMC3>;
 314                         clock-names = "sdhci";
 315                         resets = <&bpmp TEGRA194_RESET_SDMMC3>;
 316                         reset-names = "sdhci";
 317                         status = "disabled";
 318                 };
 319
 320                 sdmmc4: sdhci@3460000 {
 321                         compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci";
 322                         reg = <0x03460000 0x10000>;
 323                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 324                         clocks = <&bpmp TEGRA194_CLK_SDMMC4>;
 325                         clock-names = "sdhci";
 326                         resets = <&bpmp TEGRA194_RESET_SDMMC4>;
 327                         reset-names = "sdhci";
 328                         status = "disabled";
 329                 };
 330
 331                 hda@3510000 {
 332                         compatible = "nvidia,tegra194-hda", "nvidia,tegra30-hda";
 333                         reg = <0x3510000 0x10000>;
 334                         interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
 335                         clocks = <&bpmp TEGRA194_CLK_HDA>,
 336                                  <&bpmp TEGRA194_CLK_HDA2CODEC_2X>,
 337                                  <&bpmp TEGRA194_CLK_HDA2HDMICODEC>;
 338                         clock-names = "hda", "hda2codec_2x", "hda2hdmi";
 339                         resets = <&bpmp TEGRA194_RESET_HDA>,
 340                                  <&bpmp TEGRA194_RESET_HDA2CODEC_2X>,
 341                                  <&bpmp TEGRA194_RESET_HDA2HDMICODEC>;
 342                         reset-names = "hda", "hda2codec_2x", "hda2hdmi";
 343                         power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
 344                         status = "disabled";
 345                 };
 346
 347                 gic: interrupt-controller@3881000 {
 348                         compatible = "arm,gic-400";
 349                         #interrupt-cells = <3>;
 350                         interrupt-controller;
 351                         reg = <0x03881000 0x1000>,
 352                               <0x03882000 0x2000>,
 353                               <0x03884000 0x2000>,
 354                               <0x03886000 0x2000>;
 355                         interrupts = <GIC_PPI 9
 356                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 357                         interrupt-parent = <&gic>;
 358                 };
 359
 360                 cec@3960000 {
 361                         compatible = "nvidia,tegra194-cec";
 362                         reg = <0x03960000 0x10000>;
 363                         interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
 364                         clocks = <&bpmp TEGRA194_CLK_CEC>;
 365                         clock-names = "cec";
 366                         status = "disabled";
 367                 };
 368
 369                 hsp_top0: hsp@3c00000 {
 370                         compatible = "nvidia,tegra186-hsp";
 371                         reg = <0x03c00000 0xa0000>;
 372                         interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
 373                         interrupt-names = "doorbell";
 374                         #mbox-cells = <2>;
 375                 };
 376
 377                 gen2_i2c: i2c@c240000 {
 378                         compatible = "nvidia,tegra194-i2c";
 379                         reg = <0x0c240000 0x10000>;
 380                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 381                         #address-cells = <1>;
 382                         #size-cells = <0>;
 383                         clocks = <&bpmp TEGRA194_CLK_I2C2>;
 384                         clock-names = "div-clk";
 385                         resets = <&bpmp TEGRA194_RESET_I2C2>;
 386                         reset-names = "i2c";
 387                         status = "disabled";
 388                 };
 389
 390                 gen8_i2c: i2c@c250000 {
 391                         compatible = "nvidia,tegra194-i2c";
 392                         reg = <0x0c250000 0x10000>;
 393                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 394                         #address-cells = <1>;
 395                         #size-cells = <0>;
 396                         clocks = <&bpmp TEGRA194_CLK_I2C8>;
 397                         clock-names = "div-clk";
 398                         resets = <&bpmp TEGRA194_RESET_I2C8>;
 399                         reset-names = "i2c";
 400                         status = "disabled";
 401                 };
 402
 403                 uartc: serial@c280000 {
 404                         compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
 405                         reg = <0x0c280000 0x40>;
 406                         reg-shift = <2>;
 407                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 408                         clocks = <&bpmp TEGRA194_CLK_UARTC>;
 409                         clock-names = "serial";
 410                         resets = <&bpmp TEGRA194_RESET_UARTC>;
 411                         reset-names = "serial";
 412                         status = "disabled";
 413                 };
 414
 415                 uartg: serial@c290000 {
 416                         compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
 417                         reg = <0x0c290000 0x40>;
 418                         reg-shift = <2>;
 419                         interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
 420                         clocks = <&bpmp TEGRA194_CLK_UARTG>;
 421                         clock-names = "serial";
 422                         resets = <&bpmp TEGRA194_RESET_UARTG>;
 423                         reset-names = "serial";
 424                         status = "disabled";
 425                 };
 426
 427                 rtc: rtc@c2a0000 {
 428                         compatible = "nvidia,tegra194-rtc", "nvidia,tegra20-rtc";
 429                         reg = <0x0c2a0000 0x10000>;
 430                         interrupt-parent = <&pmc>;
 431                         interrupts = <73 IRQ_TYPE_LEVEL_HIGH>;
 432                         clocks = <&bpmp TEGRA194_CLK_CLK_32K>;
 433                         clock-names = "rtc";
 434                         status = "disabled";
 435                 };
 436
 437                 gpio_aon: gpio@c2f0000 {
 438                         compatible = "nvidia,tegra194-gpio-aon";
 439                         reg-names = "security", "gpio";
 440                         reg = <0xc2f0000 0x1000>,
 441                               <0xc2f1000 0x1000>;
 442                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
 443                                      <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
 444                                      <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
 445                                      <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 446                         gpio-controller;
 447                         #gpio-cells = <2>;
 448                         interrupt-controller;
 449                         #interrupt-cells = <2>;
 450                 };
 451
 452                 pwm4: pwm@c340000 {
 453                         compatible = "nvidia,tegra194-pwm",
 454                                      "nvidia,tegra186-pwm";
 455                         reg = <0xc340000 0x10000>;
 456                         clocks = <&bpmp TEGRA194_CLK_PWM4>;
 457                         clock-names = "pwm";
 458                         resets = <&bpmp TEGRA194_RESET_PWM4>;
 459                         reset-names = "pwm";
 460                         status = "disabled";
 461                         #pwm-cells = <2>;
 462                 };
 463
 464                 pmc: pmc@c360000 {
 465                         compatible = "nvidia,tegra194-pmc";
 466                         reg = <0x0c360000 0x10000>,
 467                               <0x0c370000 0x10000>,
 468                               <0x0c380000 0x10000>,
 469                               <0x0c390000 0x10000>,
 470                               <0x0c3a0000 0x10000>;
 471                         reg-names = "pmc", "wake", "aotag", "scratch", "misc";
 472
 473                         #interrupt-cells = <2>;
 474                         interrupt-controller;
 475                 };
 476
 477                 host1x@13e00000 {
 478                         compatible = "nvidia,tegra194-host1x", "simple-bus";
 479                         reg = <0x13e00000 0x10000>,
 480                               <0x13e10000 0x10000>;
 481                         reg-names = "hypervisor", "vm";
 482                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
 483                                      <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
 484                         clocks = <&bpmp TEGRA194_CLK_HOST1X>;
 485                         clock-names = "host1x";
 486                         resets = <&bpmp TEGRA194_RESET_HOST1X>;
 487                         reset-names = "host1x";
 488
 489                         #address-cells = <1>;
 490                         #size-cells = <1>;
 491
 492                         ranges = <0x15000000 0x15000000 0x01000000>;
 493
 494                         display-hub@15200000 {
 495                                 compatible = "nvidia,tegra194-display", "simple-bus";
 496                                 reg = <0x15200000 0x00040000>;
 497                                 resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_MISC>,
 498                                          <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP0>,
 499                                          <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP1>,
 500                                          <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP2>,
 501                                          <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP3>,
 502                                          <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP4>,
 503                                          <&bpmp TEGRA194_RESET_NVDISPLAY0_WGRP5>;
 504                                 reset-names = "misc", "wgrp0", "wgrp1", "wgrp2",
 505                                               "wgrp3", "wgrp4", "wgrp5";
 506                                 clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_DISP>,
 507                                          <&bpmp TEGRA194_CLK_NVDISPLAYHUB>;
 508                                 clock-names = "disp", "hub";
 509                                 status = "disabled";
 510
 511                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
 512
 513                                 #address-cells = <1>;
 514                                 #size-cells = <1>;
 515
 516                                 ranges = <0x15200000 0x15200000 0x40000>;
 517
 518                                 display@15200000 {
 519                                         compatible = "nvidia,tegra194-dc";
 520                                         reg = <0x15200000 0x10000>;
 521                                         interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 522                                         clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P0>;
 523                                         clock-names = "dc";
 524                                         resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD0>;
 525                                         reset-names = "dc";
 526
 527                                         power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
 528
 529                                         nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
 530                                         nvidia,head = <0>;
 531                                 };
 532
 533                                 display@15210000 {
 534                                         compatible = "nvidia,tegra194-dc";
 535                                         reg = <0x15210000 0x10000>;
 536                                         interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 537                                         clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P1>;
 538                                         clock-names = "dc";
 539                                         resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD1>;
 540                                         reset-names = "dc";
 541
 542                                         power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPB>;
 543
 544                                         nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
 545                                         nvidia,head = <1>;
 546                                 };
 547
 548                                 display@15220000 {
 549                                         compatible = "nvidia,tegra194-dc";
 550                                         reg = <0x15220000 0x10000>;
 551                                         interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
 552                                         clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P2>;
 553                                         clock-names = "dc";
 554                                         resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD2>;
 555                                         reset-names = "dc";
 556
 557                                         power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
 558
 559                                         nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
 560                                         nvidia,head = <2>;
 561                                 };
 562
 563                                 display@15230000 {
 564                                         compatible = "nvidia,tegra194-dc";
 565                                         reg = <0x15230000 0x10000>;
 566                                         interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
 567                                         clocks = <&bpmp TEGRA194_CLK_NVDISPLAY_P3>;
 568                                         clock-names = "dc";
 569                                         resets = <&bpmp TEGRA194_RESET_NVDISPLAY0_HEAD3>;
 570                                         reset-names = "dc";
 571
 572                                         power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISPC>;
 573
 574                                         nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>;
 575                                         nvidia,head = <3>;
 576                                 };
 577                         };
 578
 579                         vic@15340000 {
 580                                 compatible = "nvidia,tegra194-vic";
 581                                 reg = <0x15340000 0x00040000>;
 582                                 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
 583                                 clocks = <&bpmp TEGRA194_CLK_VIC>;
 584                                 clock-names = "vic";
 585                                 resets = <&bpmp TEGRA194_RESET_VIC>;
 586                                 reset-names = "vic";
 587
 588                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>;
 589                         };
 590
 591                         dpaux0: dpaux@155c0000 {
 592                                 compatible = "nvidia,tegra194-dpaux";
 593                                 reg = <0x155c0000 0x10000>;
 594                                 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
 595                                 clocks = <&bpmp TEGRA194_CLK_DPAUX>,
 596                                          <&bpmp TEGRA194_CLK_PLLDP>;
 597                                 clock-names = "dpaux", "parent";
 598                                 resets = <&bpmp TEGRA194_RESET_DPAUX>;
 599                                 reset-names = "dpaux";
 600                                 status = "disabled";
 601
 602                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
 603
 604                                 state_dpaux0_aux: pinmux-aux {
 605                                         groups = "dpaux-io";
 606                                         function = "aux";
 607                                 };
 608
 609                                 state_dpaux0_i2c: pinmux-i2c {
 610                                         groups = "dpaux-io";
 611                                         function = "i2c";
 612                                 };
 613
 614                                 state_dpaux0_off: pinmux-off {
 615                                         groups = "dpaux-io";
 616                                         function = "off";
 617                                 };
 618
 619                                 i2c-bus {
 620                                         #address-cells = <1>;
 621                                         #size-cells = <0>;
 622                                 };
 623                         };
 624
 625                         dpaux1: dpaux@155d0000 {
 626                                 compatible = "nvidia,tegra194-dpaux";
 627                                 reg = <0x155d0000 0x10000>;
 628                                 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
 629                                 clocks = <&bpmp TEGRA194_CLK_DPAUX1>,
 630                                          <&bpmp TEGRA194_CLK_PLLDP>;
 631                                 clock-names = "dpaux", "parent";
 632                                 resets = <&bpmp TEGRA194_RESET_DPAUX1>;
 633                                 reset-names = "dpaux";
 634                                 status = "disabled";
 635
 636                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
 637
 638                                 state_dpaux1_aux: pinmux-aux {
 639                                         groups = "dpaux-io";
 640                                         function = "aux";
 641                                 };
 642
 643                                 state_dpaux1_i2c: pinmux-i2c {
 644                                         groups = "dpaux-io";
 645                                         function = "i2c";
 646                                 };
 647
 648                                 state_dpaux1_off: pinmux-off {
 649                                         groups = "dpaux-io";
 650                                         function = "off";
 651                                 };
 652
 653                                 i2c-bus {
 654                                         #address-cells = <1>;
 655                                         #size-cells = <0>;
 656                                 };
 657                         };
 658
 659                         dpaux2: dpaux@155e0000 {
 660                                 compatible = "nvidia,tegra194-dpaux";
 661                                 reg = <0x155e0000 0x10000>;
 662                                 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
 663                                 clocks = <&bpmp TEGRA194_CLK_DPAUX2>,
 664                                          <&bpmp TEGRA194_CLK_PLLDP>;
 665                                 clock-names = "dpaux", "parent";
 666                                 resets = <&bpmp TEGRA194_RESET_DPAUX2>;
 667                                 reset-names = "dpaux";
 668                                 status = "disabled";
 669
 670                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
 671
 672                                 state_dpaux2_aux: pinmux-aux {
 673                                         groups = "dpaux-io";
 674                                         function = "aux";
 675                                 };
 676
 677                                 state_dpaux2_i2c: pinmux-i2c {
 678                                         groups = "dpaux-io";
 679                                         function = "i2c";
 680                                 };
 681
 682                                 state_dpaux2_off: pinmux-off {
 683                                         groups = "dpaux-io";
 684                                         function = "off";
 685                                 };
 686
 687                                 i2c-bus {
 688                                         #address-cells = <1>;
 689                                         #size-cells = <0>;
 690                                 };
 691                         };
 692
 693                         dpaux3: dpaux@155f0000 {
 694                                 compatible = "nvidia,tegra194-dpaux";
 695                                 reg = <0x155f0000 0x10000>;
 696                                 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
 697                                 clocks = <&bpmp TEGRA194_CLK_DPAUX3>,
 698                                          <&bpmp TEGRA194_CLK_PLLDP>;
 699                                 clock-names = "dpaux", "parent";
 700                                 resets = <&bpmp TEGRA194_RESET_DPAUX3>;
 701                                 reset-names = "dpaux";
 702                                 status = "disabled";
 703
 704                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
 705
 706                                 state_dpaux3_aux: pinmux-aux {
 707                                         groups = "dpaux-io";
 708                                         function = "aux";
 709                                 };
 710
 711                                 state_dpaux3_i2c: pinmux-i2c {
 712                                         groups = "dpaux-io";
 713                                         function = "i2c";
 714                                 };
 715
 716                                 state_dpaux3_off: pinmux-off {
 717                                         groups = "dpaux-io";
 718                                         function = "off";
 719                                 };
 720
 721                                 i2c-bus {
 722                                         #address-cells = <1>;
 723                                         #size-cells = <0>;
 724                                 };
 725                         };
 726
 727                         sor0: sor@15b00000 {
 728                                 compatible = "nvidia,tegra194-sor";
 729                                 reg = <0x15b00000 0x40000>;
 730                                 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
 731                                 clocks = <&bpmp TEGRA194_CLK_SOR0_REF>,
 732                                          <&bpmp TEGRA194_CLK_SOR0_OUT>,
 733                                          <&bpmp TEGRA194_CLK_PLLD>,
 734                                          <&bpmp TEGRA194_CLK_PLLDP>,
 735                                          <&bpmp TEGRA194_CLK_SOR_SAFE>,
 736                                          <&bpmp TEGRA194_CLK_SOR0_PAD_CLKOUT>;
 737                                 clock-names = "sor", "out", "parent", "dp", "safe",
 738                                               "pad";
 739                                 resets = <&bpmp TEGRA194_RESET_SOR0>;
 740                                 reset-names = "sor";
 741                                 pinctrl-0 = <&state_dpaux0_aux>;
 742                                 pinctrl-1 = <&state_dpaux0_i2c>;
 743                                 pinctrl-2 = <&state_dpaux0_off>;
 744                                 pinctrl-names = "aux", "i2c", "off";
 745                                 status = "disabled";
 746
 747                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
 748                                 nvidia,interface = <0>;
 749                         };
 750
 751                         sor1: sor@15b40000 {
 752                                 compatible = "nvidia,tegra194-sor";
 753                                 reg = <0x155c0000 0x40000>;
 754                                 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
 755                                 clocks = <&bpmp TEGRA194_CLK_SOR1_REF>,
 756                                          <&bpmp TEGRA194_CLK_SOR1_OUT>,
 757                                          <&bpmp TEGRA194_CLK_PLLD2>,
 758                                          <&bpmp TEGRA194_CLK_PLLDP>,
 759                                          <&bpmp TEGRA194_CLK_SOR_SAFE>,
 760                                          <&bpmp TEGRA194_CLK_SOR1_PAD_CLKOUT>;
 761                                 clock-names = "sor", "out", "parent", "dp", "safe",
 762                                               "pad";
 763                                 resets = <&bpmp TEGRA194_RESET_SOR1>;
 764                                 reset-names = "sor";
 765                                 pinctrl-0 = <&state_dpaux1_aux>;
 766                                 pinctrl-1 = <&state_dpaux1_i2c>;
 767                                 pinctrl-2 = <&state_dpaux1_off>;
 768                                 pinctrl-names = "aux", "i2c", "off";
 769                                 status = "disabled";
 770
 771                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
 772                                 nvidia,interface = <1>;
 773                         };
 774
 775                         sor2: sor@15b80000 {
 776                                 compatible = "nvidia,tegra194-sor";
 777                                 reg = <0x15b80000 0x40000>;
 778                                 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
 779                                 clocks = <&bpmp TEGRA194_CLK_SOR2_REF>,
 780                                          <&bpmp TEGRA194_CLK_SOR2_OUT>,
 781                                          <&bpmp TEGRA194_CLK_PLLD3>,
 782                                          <&bpmp TEGRA194_CLK_PLLDP>,
 783                                          <&bpmp TEGRA194_CLK_SOR_SAFE>,
 784                                          <&bpmp TEGRA194_CLK_SOR2_PAD_CLKOUT>;
 785                                 clock-names = "sor", "out", "parent", "dp", "safe",
 786                                               "pad";
 787                                 resets = <&bpmp TEGRA194_RESET_SOR2>;
 788                                 reset-names = "sor";
 789                                 pinctrl-0 = <&state_dpaux2_aux>;
 790                                 pinctrl-1 = <&state_dpaux2_i2c>;
 791                                 pinctrl-2 = <&state_dpaux2_off>;
 792                                 pinctrl-names = "aux", "i2c", "off";
 793                                 status = "disabled";
 794
 795                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
 796                                 nvidia,interface = <2>;
 797                         };
 798
 799                         sor3: sor@15bc0000 {
 800                                 compatible = "nvidia,tegra194-sor";
 801                                 reg = <0x15bc0000 0x40000>;
 802                                 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
 803                                 clocks = <&bpmp TEGRA194_CLK_SOR3_REF>,
 804                                          <&bpmp TEGRA194_CLK_SOR3_OUT>,
 805                                          <&bpmp TEGRA194_CLK_PLLD4>,
 806                                          <&bpmp TEGRA194_CLK_PLLDP>,
 807                                          <&bpmp TEGRA194_CLK_SOR_SAFE>,
 808                                          <&bpmp TEGRA194_CLK_SOR3_PAD_CLKOUT>;
 809                                 clock-names = "sor", "out", "parent", "dp", "safe",
 810                                               "pad";
 811                                 resets = <&bpmp TEGRA194_RESET_SOR3>;
 812                                 reset-names = "sor";
 813                                 pinctrl-0 = <&state_dpaux3_aux>;
 814                                 pinctrl-1 = <&state_dpaux3_i2c>;
 815                                 pinctrl-2 = <&state_dpaux3_off>;
 816                                 pinctrl-names = "aux", "i2c", "off";
 817                                 status = "disabled";
 818
 819                                 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_DISP>;
 820                                 nvidia,interface = <3>;
 821                         };
 822                 };
 823         };
 824
 825         sysram@40000000 {
 826                 compatible = "nvidia,tegra194-sysram", "mmio-sram";
 827                 reg = <0x0 0x40000000 0x0 0x50000>;
 828                 #address-cells = <1>;
 829                 #size-cells = <1>;
 830                 ranges = <0x0 0x0 0x40000000 0x50000>;
 831
 832                 cpu_bpmp_tx: shmem@4e000 {
 833                         compatible = "nvidia,tegra194-bpmp-shmem";
 834                         reg = <0x4e000 0x1000>;
 835                         label = "cpu-bpmp-tx";
 836                         pool;
 837                 };
 838
 839                 cpu_bpmp_rx: shmem@4f000 {
 840                         compatible = "nvidia,tegra194-bpmp-shmem";
 841                         reg = <0x4f000 0x1000>;
 842                         label = "cpu-bpmp-rx";
 843                         pool;
 844                 };
 845         };
 846
 847         bpmp: bpmp {
 848                 compatible = "nvidia,tegra186-bpmp";
 849                 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
 850                                     TEGRA_HSP_DB_MASTER_BPMP>;
 851                 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
 852                 #clock-cells = <1>;
 853                 #reset-cells = <1>;
 854                 #power-domain-cells = <1>;
 855
 856                 bpmp_i2c: i2c {
 857                         compatible = "nvidia,tegra186-bpmp-i2c";
 858                         nvidia,bpmp-bus-id = <5>;
 859                         #address-cells = <1>;
 860                         #size-cells = <0>;
 861                 };
 862
 863                 bpmp_thermal: thermal {
 864                         compatible = "nvidia,tegra186-bpmp-thermal";
 865                         #thermal-sensor-cells = <1>;
 866                 };
 867         };
 868
 869         cpus {
 870                 #address-cells = <1>;
 871                 #size-cells = <0>;
 872
 873                 cpu@0 {
 874                         compatible = "nvidia,tegra194-carmel", "arm,armv8";
 875                         device_type = "cpu";
 876                         reg = <0x10000>;
 877                         enable-method = "psci";
 878                 };
 879
 880                 cpu@1 {
 881                         compatible = "nvidia,tegra194-carmel", "arm,armv8";
 882                         device_type = "cpu";
 883                         reg = <0x10001>;
 884                         enable-method = "psci";
 885                 };
 886
 887                 cpu@2 {
 888                         compatible = "nvidia,tegra194-carmel", "arm,armv8";
 889                         device_type = "cpu";
 890                         reg = <0x100>;
 891                         enable-method = "psci";
 892                 };
 893
 894                 cpu@3 {
 895                         compatible = "nvidia,tegra194-carmel", "arm,armv8";
 896                         device_type = "cpu";
 897                         reg = <0x101>;
 898                         enable-method = "psci";
 899                 };
 900
 901                 cpu@4 {
 902                         compatible = "nvidia,tegra194-carmel", "arm,armv8";
 903                         device_type = "cpu";
 904                         reg = <0x200>;
 905                         enable-method = "psci";
 906                 };
 907
 908                 cpu@5 {
 909                         compatible = "nvidia,tegra194-carmel", "arm,armv8";
 910                         device_type = "cpu";
 911                         reg = <0x201>;
 912                         enable-method = "psci";
 913                 };
 914
 915                 cpu@6 {
 916                         compatible = "nvidia,tegra194-carmel", "arm,armv8";
 917                         device_type = "cpu";
 918                         reg = <0x10300>;
 919                         enable-method = "psci";
 920                 };
 921
 922                 cpu@7 {
 923                         compatible = "nvidia,tegra194-carmel", "arm,armv8";
 924                         device_type = "cpu";
 925                         reg = <0x10301>;
 926                         enable-method = "psci";
 927                 };
 928         };
 929
 930         psci {
 931                 compatible = "arm,psci-1.0";
 932                 status = "okay";
 933                 method = "smc";
 934         };
 935
 936         thermal-zones {
 937                 cpu {
 938                         thermal-sensors = <&{/bpmp/thermal}
 939                                            TEGRA194_BPMP_THERMAL_ZONE_CPU>;
 940                         status = "disabled";
 941                 };
 942
 943                 gpu {
 944                         thermal-sensors = <&{/bpmp/thermal}
 945                                            TEGRA194_BPMP_THERMAL_ZONE_GPU>;
 946                         status = "disabled";
 947                 };
 948
 949                 aux {
 950                         thermal-sensors = <&{/bpmp/thermal}
 951                                            TEGRA194_BPMP_THERMAL_ZONE_AUX>;
 952                         status = "disabled";
 953                 };
 954
 955                 pllx {
 956                         thermal-sensors = <&{/bpmp/thermal}
 957                                            TEGRA194_BPMP_THERMAL_ZONE_PLLX>;
 958                         status = "disabled";
 959                 };
 960
 961                 ao {
 962                         thermal-sensors = <&{/bpmp/thermal}
 963                                            TEGRA194_BPMP_THERMAL_ZONE_AO>;
 964                         status = "disabled";
 965                 };
 966
 967                 tj {
 968                         thermal-sensors = <&{/bpmp/thermal}
 969                                            TEGRA194_BPMP_THERMAL_ZONE_TJ_MAX>;
 970                         status = "disabled";
 971                 };
 972         };
 973
 974         timer {
 975                 compatible = "arm,armv8-timer";
 976                 interrupts = <GIC_PPI 13
 977                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 978                              <GIC_PPI 14
 979                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 980                              <GIC_PPI 11
 981                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 982                              <GIC_PPI 10
 983                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 984                 interrupt-parent = <&gic>;
 985         };
 986 };