1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra210-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra210-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7 #include <dt-bindings/reset/tegra210-car.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/tegra124-soctherm.h>
12 compatible = "nvidia,tegra210";
13 interrupt-parent = <&lic>;
18 compatible = "nvidia,tegra210-pcie";
20 reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
21 0x0 0x01003800 0x0 0x00000800 /* AFI registers */
22 0x0 0x02000000 0x0 0x10000000>; /* configuration space */
23 reg-names = "pads", "afi", "cs";
24 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
25 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
26 interrupt-names = "intr", "msi";
28 #interrupt-cells = <1>;
29 interrupt-map-mask = <0 0 0 0>;
30 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
32 bus-range = <0x00 0xff>;
36 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */
37 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */
38 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */
39 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */
40 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
42 clocks = <&tegra_car TEGRA210_CLK_PCIE>,
43 <&tegra_car TEGRA210_CLK_AFI>,
44 <&tegra_car TEGRA210_CLK_PLL_E>,
45 <&tegra_car TEGRA210_CLK_CML0>;
46 clock-names = "pex", "afi", "pll_e", "cml";
47 resets = <&tegra_car 70>,
50 reset-names = "pex", "afi", "pcie_x";
52 pinctrl-names = "default", "idle";
53 pinctrl-0 = <&pex_dpd_disable>;
54 pinctrl-1 = <&pex_dpd_enable>;
60 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
61 reg = <0x000800 0 0 0 0>;
62 bus-range = <0x00 0xff>;
69 nvidia,num-lanes = <4>;
74 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
75 reg = <0x001000 0 0 0 0>;
76 bus-range = <0x00 0xff>;
83 nvidia,num-lanes = <1>;
88 compatible = "nvidia,tegra210-host1x", "simple-bus";
89 reg = <0x0 0x50000000 0x0 0x00034000>;
90 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
91 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
92 clocks = <&tegra_car TEGRA210_CLK_HOST1X>;
93 clock-names = "host1x";
94 resets = <&tegra_car 28>;
95 reset-names = "host1x";
100 ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>;
102 iommus = <&mc TEGRA_SWGROUP_HC>;
104 dpaux1: dpaux@54040000 {
105 compatible = "nvidia,tegra210-dpaux";
106 reg = <0x0 0x54040000 0x0 0x00040000>;
107 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
108 clocks = <&tegra_car TEGRA210_CLK_DPAUX1>,
109 <&tegra_car TEGRA210_CLK_PLL_DP>;
110 clock-names = "dpaux", "parent";
111 resets = <&tegra_car 207>;
112 reset-names = "dpaux";
113 power-domains = <&pd_sor>;
116 state_dpaux1_aux: pinmux-aux {
121 state_dpaux1_i2c: pinmux-i2c {
126 state_dpaux1_off: pinmux-off {
132 #address-cells = <1>;
138 compatible = "nvidia,tegra210-vi";
139 reg = <0x0 0x54080000 0x0 0x00040000>;
140 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
145 compatible = "nvidia,tegra210-tsec";
146 reg = <0x0 0x54100000 0x0 0x00040000>;
150 compatible = "nvidia,tegra210-dc";
151 reg = <0x0 0x54200000 0x0 0x00040000>;
152 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
153 clocks = <&tegra_car TEGRA210_CLK_DISP1>,
154 <&tegra_car TEGRA210_CLK_PLL_P>;
155 clock-names = "dc", "parent";
156 resets = <&tegra_car 27>;
159 iommus = <&mc TEGRA_SWGROUP_DC>;
165 compatible = "nvidia,tegra210-dc";
166 reg = <0x0 0x54240000 0x0 0x00040000>;
167 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
168 clocks = <&tegra_car TEGRA210_CLK_DISP2>,
169 <&tegra_car TEGRA210_CLK_PLL_P>;
170 clock-names = "dc", "parent";
171 resets = <&tegra_car 26>;
174 iommus = <&mc TEGRA_SWGROUP_DCB>;
180 compatible = "nvidia,tegra210-dsi";
181 reg = <0x0 0x54300000 0x0 0x00040000>;
182 clocks = <&tegra_car TEGRA210_CLK_DSIA>,
183 <&tegra_car TEGRA210_CLK_DSIALP>,
184 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>;
185 clock-names = "dsi", "lp", "parent";
186 resets = <&tegra_car 48>;
188 power-domains = <&pd_sor>;
189 nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */
193 #address-cells = <1>;
198 compatible = "nvidia,tegra210-vic";
199 reg = <0x0 0x54340000 0x0 0x00040000>;
200 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
201 clocks = <&tegra_car TEGRA210_CLK_VIC03>;
203 resets = <&tegra_car 178>;
206 iommus = <&mc TEGRA_SWGROUP_VIC>;
207 power-domains = <&pd_vic>;
211 compatible = "nvidia,tegra210-nvjpg";
212 reg = <0x0 0x54380000 0x0 0x00040000>;
217 compatible = "nvidia,tegra210-dsi";
218 reg = <0x0 0x54400000 0x0 0x00040000>;
219 clocks = <&tegra_car TEGRA210_CLK_DSIB>,
220 <&tegra_car TEGRA210_CLK_DSIBLP>,
221 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>;
222 clock-names = "dsi", "lp", "parent";
223 resets = <&tegra_car 82>;
225 power-domains = <&pd_sor>;
226 nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */
230 #address-cells = <1>;
235 compatible = "nvidia,tegra210-nvdec";
236 reg = <0x0 0x54480000 0x0 0x00040000>;
241 compatible = "nvidia,tegra210-nvenc";
242 reg = <0x0 0x544c0000 0x0 0x00040000>;
247 compatible = "nvidia,tegra210-tsec";
248 reg = <0x0 0x54500000 0x0 0x00040000>;
253 compatible = "nvidia,tegra210-sor";
254 reg = <0x0 0x54540000 0x0 0x00040000>;
255 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
256 clocks = <&tegra_car TEGRA210_CLK_SOR0>,
257 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>,
258 <&tegra_car TEGRA210_CLK_PLL_DP>,
259 <&tegra_car TEGRA210_CLK_SOR_SAFE>;
260 clock-names = "sor", "parent", "dp", "safe";
261 resets = <&tegra_car 182>;
263 pinctrl-0 = <&state_dpaux_aux>;
264 pinctrl-1 = <&state_dpaux_i2c>;
265 pinctrl-2 = <&state_dpaux_off>;
266 pinctrl-names = "aux", "i2c", "off";
267 power-domains = <&pd_sor>;
272 compatible = "nvidia,tegra210-sor1";
273 reg = <0x0 0x54580000 0x0 0x00040000>;
274 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
275 clocks = <&tegra_car TEGRA210_CLK_SOR1>,
276 <&tegra_car TEGRA210_CLK_SOR1_OUT>,
277 <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>,
278 <&tegra_car TEGRA210_CLK_PLL_DP>,
279 <&tegra_car TEGRA210_CLK_SOR_SAFE>;
280 clock-names = "sor", "out", "parent", "dp", "safe";
281 resets = <&tegra_car 183>;
283 pinctrl-0 = <&state_dpaux1_aux>;
284 pinctrl-1 = <&state_dpaux1_i2c>;
285 pinctrl-2 = <&state_dpaux1_off>;
286 pinctrl-names = "aux", "i2c", "off";
287 power-domains = <&pd_sor>;
291 dpaux: dpaux@545c0000 {
292 compatible = "nvidia,tegra124-dpaux";
293 reg = <0x0 0x545c0000 0x0 0x00040000>;
294 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
295 clocks = <&tegra_car TEGRA210_CLK_DPAUX>,
296 <&tegra_car TEGRA210_CLK_PLL_DP>;
297 clock-names = "dpaux", "parent";
298 resets = <&tegra_car 181>;
299 reset-names = "dpaux";
300 power-domains = <&pd_sor>;
303 state_dpaux_aux: pinmux-aux {
308 state_dpaux_i2c: pinmux-i2c {
313 state_dpaux_off: pinmux-off {
319 #address-cells = <1>;
325 compatible = "nvidia,tegra210-isp";
326 reg = <0x0 0x54600000 0x0 0x00040000>;
327 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
332 compatible = "nvidia,tegra210-isp";
333 reg = <0x0 0x54680000 0x0 0x00040000>;
334 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
339 compatible = "nvidia,tegra210-i2c-vi";
340 reg = <0x0 0x546c0000 0x0 0x00040000>;
341 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
346 gic: interrupt-controller@50041000 {
347 compatible = "arm,gic-400";
348 #interrupt-cells = <3>;
349 interrupt-controller;
350 reg = <0x0 0x50041000 0x0 0x1000>,
351 <0x0 0x50042000 0x0 0x2000>,
352 <0x0 0x50044000 0x0 0x2000>,
353 <0x0 0x50046000 0x0 0x2000>;
354 interrupts = <GIC_PPI 9
355 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
356 interrupt-parent = <&gic>;
360 compatible = "nvidia,gm20b";
361 reg = <0x0 0x57000000 0x0 0x01000000>,
362 <0x0 0x58000000 0x0 0x01000000>;
363 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
364 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
365 interrupt-names = "stall", "nonstall";
366 clocks = <&tegra_car TEGRA210_CLK_GPU>,
367 <&tegra_car TEGRA210_CLK_PLL_P_OUT5>,
368 <&tegra_car TEGRA210_CLK_PLL_G_REF>;
369 clock-names = "gpu", "pwr", "ref";
370 resets = <&tegra_car 184>;
373 iommus = <&mc TEGRA_SWGROUP_GPU>;
378 lic: interrupt-controller@60004000 {
379 compatible = "nvidia,tegra210-ictlr";
380 reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */
381 <0x0 0x60004100 0x0 0x40>, /* secondary controller */
382 <0x0 0x60004200 0x0 0x40>, /* tertiary controller */
383 <0x0 0x60004300 0x0 0x40>, /* quaternary controller */
384 <0x0 0x60004400 0x0 0x40>, /* quinary controller */
385 <0x0 0x60004500 0x0 0x40>; /* senary controller */
386 interrupt-controller;
387 #interrupt-cells = <3>;
388 interrupt-parent = <&gic>;
392 compatible = "nvidia,tegra210-timer";
393 reg = <0x0 0x60005000 0x0 0x400>;
394 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
395 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
396 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
397 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
398 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
399 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
400 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
401 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
402 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
403 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
404 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
405 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
406 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
407 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
408 clocks = <&tegra_car TEGRA210_CLK_TIMER>;
409 clock-names = "timer";
412 tegra_car: clock@60006000 {
413 compatible = "nvidia,tegra210-car";
414 reg = <0x0 0x60006000 0x0 0x1000>;
419 flow-controller@60007000 {
420 compatible = "nvidia,tegra210-flowctrl";
421 reg = <0x0 0x60007000 0x0 0x1000>;
424 gpio: gpio@6000d000 {
425 compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio";
426 reg = <0x0 0x6000d000 0x0 0x1000>;
427 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
428 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
429 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
430 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
431 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
432 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
433 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
434 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
437 #interrupt-cells = <2>;
438 interrupt-controller;
441 apbdma: dma@60020000 {
442 compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma";
443 reg = <0x0 0x60020000 0x0 0x1400>;
444 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
445 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
446 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
447 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
448 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
449 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
450 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
451 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
452 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
453 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
454 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
455 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
456 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
457 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
458 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
459 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
460 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
461 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
462 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
463 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
464 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
465 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
466 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
467 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
468 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
469 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
470 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
471 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
472 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
473 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
474 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
475 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
476 clocks = <&tegra_car TEGRA210_CLK_APBDMA>;
478 resets = <&tegra_car 34>;
484 compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc";
485 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */
486 <0x0 0x70000008 0x0 0x04>; /* Strapping options */
489 pinmux: pinmux@700008d4 {
490 compatible = "nvidia,tegra210-pinmux";
491 reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */
492 <0x0 0x70003000 0x0 0x294>; /* Mux registers */
493 sdmmc1_3v3_drv: sdmmc1-3v3-drv {
495 nvidia,pins = "drive_sdmmc1";
496 nvidia,pull-down-strength = <0x8>;
497 nvidia,pull-up-strength = <0x8>;
500 sdmmc1_1v8_drv: sdmmc1-1v8-drv {
502 nvidia,pins = "drive_sdmmc1";
503 nvidia,pull-down-strength = <0x4>;
504 nvidia,pull-up-strength = <0x3>;
507 sdmmc2_1v8_drv: sdmmc2-1v8-drv {
509 nvidia,pins = "drive_sdmmc2";
510 nvidia,pull-down-strength = <0x10>;
511 nvidia,pull-up-strength = <0x10>;
514 sdmmc3_3v3_drv: sdmmc3-3v3-drv {
516 nvidia,pins = "drive_sdmmc3";
517 nvidia,pull-down-strength = <0x8>;
518 nvidia,pull-up-strength = <0x8>;
521 sdmmc3_1v8_drv: sdmmc3-1v8-drv {
523 nvidia,pins = "drive_sdmmc3";
524 nvidia,pull-down-strength = <0x4>;
525 nvidia,pull-up-strength = <0x3>;
528 sdmmc4_1v8_drv: sdmmc4-1v8-drv {
530 nvidia,pins = "drive_sdmmc4";
531 nvidia,pull-down-strength = <0x10>;
532 nvidia,pull-up-strength = <0x10>;
538 * There are two serial driver i.e. 8250 based simple serial
539 * driver and APB DMA based serial driver for higher baudrate
540 * and performance. To enable the 8250 based driver, the compatible
541 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
542 * the APB DMA based serial driver, the compatible is
543 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
545 uarta: serial@70006000 {
546 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
547 reg = <0x0 0x70006000 0x0 0x40>;
549 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
550 clocks = <&tegra_car TEGRA210_CLK_UARTA>;
551 clock-names = "serial";
552 resets = <&tegra_car 6>;
553 reset-names = "serial";
554 dmas = <&apbdma 8>, <&apbdma 8>;
555 dma-names = "rx", "tx";
559 uartb: serial@70006040 {
560 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
561 reg = <0x0 0x70006040 0x0 0x40>;
563 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
564 clocks = <&tegra_car TEGRA210_CLK_UARTB>;
565 clock-names = "serial";
566 resets = <&tegra_car 7>;
567 reset-names = "serial";
568 dmas = <&apbdma 9>, <&apbdma 9>;
569 dma-names = "rx", "tx";
573 uartc: serial@70006200 {
574 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
575 reg = <0x0 0x70006200 0x0 0x40>;
577 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
578 clocks = <&tegra_car TEGRA210_CLK_UARTC>;
579 clock-names = "serial";
580 resets = <&tegra_car 55>;
581 reset-names = "serial";
582 dmas = <&apbdma 10>, <&apbdma 10>;
583 dma-names = "rx", "tx";
587 uartd: serial@70006300 {
588 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
589 reg = <0x0 0x70006300 0x0 0x40>;
591 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
592 clocks = <&tegra_car TEGRA210_CLK_UARTD>;
593 clock-names = "serial";
594 resets = <&tegra_car 65>;
595 reset-names = "serial";
596 dmas = <&apbdma 19>, <&apbdma 19>;
597 dma-names = "rx", "tx";
602 compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm";
603 reg = <0x0 0x7000a000 0x0 0x100>;
605 clocks = <&tegra_car TEGRA210_CLK_PWM>;
607 resets = <&tegra_car 17>;
613 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
614 reg = <0x0 0x7000c000 0x0 0x100>;
615 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
616 #address-cells = <1>;
618 clocks = <&tegra_car TEGRA210_CLK_I2C1>;
619 clock-names = "div-clk";
620 resets = <&tegra_car 12>;
622 dmas = <&apbdma 21>, <&apbdma 21>;
623 dma-names = "rx", "tx";
628 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
629 reg = <0x0 0x7000c400 0x0 0x100>;
630 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
631 #address-cells = <1>;
633 clocks = <&tegra_car TEGRA210_CLK_I2C2>;
634 clock-names = "div-clk";
635 resets = <&tegra_car 54>;
637 dmas = <&apbdma 22>, <&apbdma 22>;
638 dma-names = "rx", "tx";
643 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
644 reg = <0x0 0x7000c500 0x0 0x100>;
645 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
646 #address-cells = <1>;
648 clocks = <&tegra_car TEGRA210_CLK_I2C3>;
649 clock-names = "div-clk";
650 resets = <&tegra_car 67>;
652 dmas = <&apbdma 23>, <&apbdma 23>;
653 dma-names = "rx", "tx";
658 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
659 reg = <0x0 0x7000c700 0x0 0x100>;
660 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
661 #address-cells = <1>;
663 clocks = <&tegra_car TEGRA210_CLK_I2C4>;
664 clock-names = "div-clk";
665 resets = <&tegra_car 103>;
667 dmas = <&apbdma 26>, <&apbdma 26>;
668 dma-names = "rx", "tx";
669 pinctrl-0 = <&state_dpaux1_i2c>;
670 pinctrl-1 = <&state_dpaux1_off>;
671 pinctrl-names = "default", "idle";
676 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
677 reg = <0x0 0x7000d000 0x0 0x100>;
678 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
679 #address-cells = <1>;
681 clocks = <&tegra_car TEGRA210_CLK_I2C5>;
682 clock-names = "div-clk";
683 resets = <&tegra_car 47>;
685 dmas = <&apbdma 24>, <&apbdma 24>;
686 dma-names = "rx", "tx";
691 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
692 reg = <0x0 0x7000d100 0x0 0x100>;
693 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
694 #address-cells = <1>;
696 clocks = <&tegra_car TEGRA210_CLK_I2C6>;
697 clock-names = "div-clk";
698 resets = <&tegra_car 166>;
700 dmas = <&apbdma 30>, <&apbdma 30>;
701 dma-names = "rx", "tx";
702 pinctrl-0 = <&state_dpaux_i2c>;
703 pinctrl-1 = <&state_dpaux_off>;
704 pinctrl-names = "default", "idle";
709 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
710 reg = <0x0 0x7000d400 0x0 0x200>;
711 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
712 #address-cells = <1>;
714 clocks = <&tegra_car TEGRA210_CLK_SBC1>;
716 resets = <&tegra_car 41>;
718 dmas = <&apbdma 15>, <&apbdma 15>;
719 dma-names = "rx", "tx";
724 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
725 reg = <0x0 0x7000d600 0x0 0x200>;
726 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
727 #address-cells = <1>;
729 clocks = <&tegra_car TEGRA210_CLK_SBC2>;
731 resets = <&tegra_car 44>;
733 dmas = <&apbdma 16>, <&apbdma 16>;
734 dma-names = "rx", "tx";
739 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
740 reg = <0x0 0x7000d800 0x0 0x200>;
741 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
742 #address-cells = <1>;
744 clocks = <&tegra_car TEGRA210_CLK_SBC3>;
746 resets = <&tegra_car 46>;
748 dmas = <&apbdma 17>, <&apbdma 17>;
749 dma-names = "rx", "tx";
754 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
755 reg = <0x0 0x7000da00 0x0 0x200>;
756 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
757 #address-cells = <1>;
759 clocks = <&tegra_car TEGRA210_CLK_SBC4>;
761 resets = <&tegra_car 68>;
763 dmas = <&apbdma 18>, <&apbdma 18>;
764 dma-names = "rx", "tx";
769 compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc";
770 reg = <0x0 0x7000e000 0x0 0x100>;
771 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
772 clocks = <&tegra_car TEGRA210_CLK_RTC>;
777 compatible = "nvidia,tegra210-pmc";
778 reg = <0x0 0x7000e400 0x0 0x400>;
779 clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
780 clock-names = "pclk", "clk32k_in";
784 clocks = <&tegra_car TEGRA210_CLK_APE>,
785 <&tegra_car TEGRA210_CLK_APB2APE>;
786 resets = <&tegra_car 198>;
787 #power-domain-cells = <0>;
791 clocks = <&tegra_car TEGRA210_CLK_SOR0>,
792 <&tegra_car TEGRA210_CLK_SOR1>,
793 <&tegra_car TEGRA210_CLK_CSI>,
794 <&tegra_car TEGRA210_CLK_DSIA>,
795 <&tegra_car TEGRA210_CLK_DSIB>,
796 <&tegra_car TEGRA210_CLK_DPAUX>,
797 <&tegra_car TEGRA210_CLK_DPAUX1>,
798 <&tegra_car TEGRA210_CLK_MIPI_CAL>;
799 resets = <&tegra_car TEGRA210_CLK_SOR0>,
800 <&tegra_car TEGRA210_CLK_SOR1>,
801 <&tegra_car TEGRA210_CLK_CSI>,
802 <&tegra_car TEGRA210_CLK_DSIA>,
803 <&tegra_car TEGRA210_CLK_DSIB>,
804 <&tegra_car TEGRA210_CLK_DPAUX>,
805 <&tegra_car TEGRA210_CLK_DPAUX1>,
806 <&tegra_car TEGRA210_CLK_MIPI_CAL>;
807 #power-domain-cells = <0>;
811 clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>;
812 resets = <&tegra_car TEGRA210_CLK_XUSB_SS>;
813 #power-domain-cells = <0>;
817 clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>;
818 resets = <&tegra_car 95>;
819 #power-domain-cells = <0>;
823 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>;
824 resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>;
825 #power-domain-cells = <0>;
829 clocks = <&tegra_car TEGRA210_CLK_VIC03>;
831 resets = <&tegra_car 178>;
833 #power-domain-cells = <0>;
837 sdmmc1_3v3: sdmmc1-3v3 {
839 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
842 sdmmc1_1v8: sdmmc1-1v8 {
844 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
847 sdmmc3_3v3: sdmmc3-3v3 {
849 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
852 sdmmc3_1v8: sdmmc3-1v8 {
854 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
857 pex_dpd_disable: pex_en {
859 pins = "pex-bias", "pex-clk1", "pex-clk2";
864 pex_dpd_enable: pex_dis {
866 pins = "pex-bias", "pex-clk1", "pex-clk2";
873 compatible = "nvidia,tegra210-efuse";
874 reg = <0x0 0x7000f800 0x0 0x400>;
875 clocks = <&tegra_car TEGRA210_CLK_FUSE>;
876 clock-names = "fuse";
877 resets = <&tegra_car 39>;
878 reset-names = "fuse";
881 mc: memory-controller@70019000 {
882 compatible = "nvidia,tegra210-mc";
883 reg = <0x0 0x70019000 0x0 0x1000>;
884 clocks = <&tegra_car TEGRA210_CLK_MC>;
887 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
893 compatible = "nvidia,tegra210-ahci";
894 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
895 <0x0 0x70020000 0x0 0x7000>, /* SATA */
896 <0x0 0x70001100 0x0 0x1000>; /* SATA AUX */
897 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
898 clocks = <&tegra_car TEGRA210_CLK_SATA>,
899 <&tegra_car TEGRA210_CLK_SATA_OOB>;
900 clock-names = "sata", "sata-oob";
901 resets = <&tegra_car 124>,
904 reset-names = "sata", "sata-oob", "sata-cold";
909 compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda";
910 reg = <0x0 0x70030000 0x0 0x10000>;
911 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
912 clocks = <&tegra_car TEGRA210_CLK_HDA>,
913 <&tegra_car TEGRA210_CLK_HDA2HDMI>,
914 <&tegra_car TEGRA210_CLK_HDA2CODEC_2X>;
915 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
916 resets = <&tegra_car 125>, /* hda */
917 <&tegra_car 128>, /* hda2hdmi */
918 <&tegra_car 111>; /* hda2codec_2x */
919 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
924 compatible = "nvidia,tegra210-xusb";
925 reg = <0x0 0x70090000 0x0 0x8000>,
926 <0x0 0x70098000 0x0 0x1000>,
927 <0x0 0x70099000 0x0 0x1000>;
928 reg-names = "hcd", "fpci", "ipfs";
930 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
931 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
933 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>,
934 <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>,
935 <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>,
936 <&tegra_car TEGRA210_CLK_XUSB_SS>,
937 <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>,
938 <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>,
939 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>,
940 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>,
941 <&tegra_car TEGRA210_CLK_PLL_U_480M>,
942 <&tegra_car TEGRA210_CLK_CLK_M>,
943 <&tegra_car TEGRA210_CLK_PLL_E>;
944 clock-names = "xusb_host", "xusb_host_src",
945 "xusb_falcon_src", "xusb_ss",
946 "xusb_ss_div2", "xusb_ss_src",
947 "xusb_hs_src", "xusb_fs_src",
948 "pll_u_480m", "clk_m", "pll_e";
949 resets = <&tegra_car 89>, <&tegra_car 156>,
951 reset-names = "xusb_host", "xusb_ss", "xusb_src";
952 power-domains = <&pd_xusbhost>, <&pd_xusbss>;
953 power-domain-names = "xusb_host", "xusb_ss";
955 nvidia,xusb-padctl = <&padctl>;
960 padctl: padctl@7009f000 {
961 compatible = "nvidia,tegra210-xusb-padctl";
962 reg = <0x0 0x7009f000 0x0 0x1000>;
963 resets = <&tegra_car 142>;
964 reset-names = "padctl";
970 clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>;
998 clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>;
1000 status = "disabled";
1004 status = "disabled";
1009 status = "disabled";
1016 clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
1017 clock-names = "pll";
1018 resets = <&tegra_car 205>;
1019 reset-names = "phy";
1020 status = "disabled";
1024 status = "disabled";
1029 status = "disabled";
1034 status = "disabled";
1039 status = "disabled";
1044 status = "disabled";
1049 status = "disabled";
1054 status = "disabled";
1061 clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
1062 clock-names = "pll";
1063 resets = <&tegra_car 204>;
1064 reset-names = "phy";
1065 status = "disabled";
1069 status = "disabled";
1078 status = "disabled";
1082 status = "disabled";
1086 status = "disabled";
1090 status = "disabled";
1094 status = "disabled";
1098 status = "disabled";
1102 status = "disabled";
1106 status = "disabled";
1110 status = "disabled";
1116 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
1117 reg = <0x0 0x700b0000 0x0 0x200>;
1118 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1119 clocks = <&tegra_car TEGRA210_CLK_SDMMC1>;
1120 clock-names = "sdhci";
1121 resets = <&tegra_car 14>;
1122 reset-names = "sdhci";
1123 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8",
1124 "sdmmc-3v3-drv", "sdmmc-1v8-drv";
1125 pinctrl-0 = <&sdmmc1_3v3>;
1126 pinctrl-1 = <&sdmmc1_1v8>;
1127 pinctrl-2 = <&sdmmc1_3v3_drv>;
1128 pinctrl-3 = <&sdmmc1_1v8_drv>;
1129 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
1130 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
1131 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
1132 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
1133 nvidia,default-tap = <0x2>;
1134 nvidia,default-trim = <0x4>;
1135 assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
1136 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>,
1137 <&tegra_car TEGRA210_CLK_PLL_C4>;
1138 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
1139 assigned-clock-rates = <200000000>, <1000000000>, <1000000000>;
1140 status = "disabled";
1144 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
1145 reg = <0x0 0x700b0200 0x0 0x200>;
1146 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1147 clocks = <&tegra_car TEGRA210_CLK_SDMMC2>;
1148 clock-names = "sdhci";
1149 resets = <&tegra_car 9>;
1150 reset-names = "sdhci";
1151 pinctrl-names = "sdmmc-1v8-drv";
1152 pinctrl-0 = <&sdmmc2_1v8_drv>;
1153 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>;
1154 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>;
1155 nvidia,default-tap = <0x8>;
1156 nvidia,default-trim = <0x0>;
1157 status = "disabled";
1161 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
1162 reg = <0x0 0x700b0400 0x0 0x200>;
1163 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1164 clocks = <&tegra_car TEGRA210_CLK_SDMMC3>;
1165 clock-names = "sdhci";
1166 resets = <&tegra_car 69>;
1167 reset-names = "sdhci";
1168 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8",
1169 "sdmmc-3v3-drv", "sdmmc-1v8-drv";
1170 pinctrl-0 = <&sdmmc3_3v3>;
1171 pinctrl-1 = <&sdmmc3_1v8>;
1172 pinctrl-2 = <&sdmmc3_3v3_drv>;
1173 pinctrl-3 = <&sdmmc3_1v8_drv>;
1174 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
1175 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
1176 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
1177 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
1178 nvidia,default-tap = <0x3>;
1179 nvidia,default-trim = <0x3>;
1180 status = "disabled";
1184 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
1185 reg = <0x0 0x700b0600 0x0 0x200>;
1186 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1187 clocks = <&tegra_car TEGRA210_CLK_SDMMC4>;
1188 clock-names = "sdhci";
1189 resets = <&tegra_car 15>;
1190 reset-names = "sdhci";
1191 pinctrl-names = "sdmmc-3v3-drv", "sdmmc-1v8-drv";
1192 pinctrl-0 = <&sdmmc4_1v8_drv>;
1193 pinctrl-1 = <&sdmmc4_1v8_drv>;
1194 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>;
1195 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>;
1196 nvidia,default-tap = <0x8>;
1197 nvidia,default-trim = <0x0>;
1198 assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
1199 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
1200 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
1201 nvidia,dqs-trim = <40>;
1203 status = "disabled";
1206 mipi: mipi@700e3000 {
1207 compatible = "nvidia,tegra210-mipi";
1208 reg = <0x0 0x700e3000 0x0 0x100>;
1209 clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>;
1210 clock-names = "mipi-cal";
1211 power-domains = <&pd_sor>;
1212 #nvidia,mipi-calibrate-cells = <1>;
1215 dfll: clock@70110000 {
1216 compatible = "nvidia,tegra210-dfll";
1217 reg = <0 0x70110000 0 0x100>, /* DFLL control */
1218 <0 0x70110000 0 0x100>, /* I2C output control */
1219 <0 0x70110100 0 0x100>, /* Integrated I2C controller */
1220 <0 0x70110200 0 0x100>; /* Look-up table RAM */
1221 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1222 clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>,
1223 <&tegra_car TEGRA210_CLK_DFLL_REF>,
1224 <&tegra_car TEGRA210_CLK_I2C5>;
1225 clock-names = "soc", "ref", "i2c";
1226 resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>;
1227 reset-names = "dvco";
1229 clock-output-names = "dfllCPU_out";
1230 status = "disabled";
1234 compatible = "nvidia,tegra210-aconnect";
1235 clocks = <&tegra_car TEGRA210_CLK_APE>,
1236 <&tegra_car TEGRA210_CLK_APB2APE>;
1237 clock-names = "ape", "apb2ape";
1238 power-domains = <&pd_audio>;
1239 #address-cells = <1>;
1241 ranges = <0x702c0000 0x0 0x702c0000 0x00040000>;
1242 status = "disabled";
1244 adma: dma@702e2000 {
1245 compatible = "nvidia,tegra210-adma";
1246 reg = <0x702e2000 0x2000>;
1247 interrupt-parent = <&agic>;
1248 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
1249 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
1250 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
1251 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
1252 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
1253 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
1254 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
1255 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
1256 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
1257 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
1258 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
1259 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
1260 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
1261 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
1262 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
1263 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
1264 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1265 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
1266 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
1267 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
1268 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
1269 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1271 clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
1272 clock-names = "d_audio";
1273 status = "disabled";
1276 agic: agic@702f9000 {
1277 compatible = "nvidia,tegra210-agic";
1278 #interrupt-cells = <3>;
1279 interrupt-controller;
1280 reg = <0x702f9000 0x1000>,
1281 <0x702fa000 0x2000>;
1282 interrupts = <GIC_SPI 102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1283 clocks = <&tegra_car TEGRA210_CLK_APE>;
1284 clock-names = "clk";
1285 status = "disabled";
1290 compatible = "nvidia,tegra210-qspi";
1291 reg = <0x0 0x70410000 0x0 0x1000>;
1292 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1293 #address-cells = <1>;
1295 clocks = <&tegra_car TEGRA210_CLK_QSPI>;
1296 clock-names = "qspi";
1297 resets = <&tegra_car 211>;
1298 reset-names = "qspi";
1299 dmas = <&apbdma 5>, <&apbdma 5>;
1300 dma-names = "rx", "tx";
1301 status = "disabled";
1305 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1306 reg = <0x0 0x7d000000 0x0 0x4000>;
1307 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1309 clocks = <&tegra_car TEGRA210_CLK_USBD>;
1310 clock-names = "usb";
1311 resets = <&tegra_car 22>;
1312 reset-names = "usb";
1313 nvidia,phy = <&phy1>;
1314 status = "disabled";
1317 phy1: usb-phy@7d000000 {
1318 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy";
1319 reg = <0x0 0x7d000000 0x0 0x4000>,
1320 <0x0 0x7d000000 0x0 0x4000>;
1322 clocks = <&tegra_car TEGRA210_CLK_USBD>,
1323 <&tegra_car TEGRA210_CLK_PLL_U>,
1324 <&tegra_car TEGRA210_CLK_USBD>;
1325 clock-names = "reg", "pll_u", "utmi-pads";
1326 resets = <&tegra_car 22>, <&tegra_car 22>;
1327 reset-names = "usb", "utmi-pads";
1328 nvidia,hssync-start-delay = <0>;
1329 nvidia,idle-wait-delay = <17>;
1330 nvidia,elastic-limit = <16>;
1331 nvidia,term-range-adj = <6>;
1332 nvidia,xcvr-setup = <9>;
1333 nvidia,xcvr-lsfslew = <0>;
1334 nvidia,xcvr-lsrslew = <3>;
1335 nvidia,hssquelch-level = <2>;
1336 nvidia,hsdiscon-level = <5>;
1337 nvidia,xcvr-hsslew = <12>;
1338 nvidia,has-utmi-pad-registers;
1339 status = "disabled";
1343 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1344 reg = <0x0 0x7d004000 0x0 0x4000>;
1345 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1347 clocks = <&tegra_car TEGRA210_CLK_USB2>;
1348 clock-names = "usb";
1349 resets = <&tegra_car 58>;
1350 reset-names = "usb";
1351 nvidia,phy = <&phy2>;
1352 status = "disabled";
1355 phy2: usb-phy@7d004000 {
1356 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy";
1357 reg = <0x0 0x7d004000 0x0 0x4000>,
1358 <0x0 0x7d000000 0x0 0x4000>;
1360 clocks = <&tegra_car TEGRA210_CLK_USB2>,
1361 <&tegra_car TEGRA210_CLK_PLL_U>,
1362 <&tegra_car TEGRA210_CLK_USBD>;
1363 clock-names = "reg", "pll_u", "utmi-pads";
1364 resets = <&tegra_car 58>, <&tegra_car 22>;
1365 reset-names = "usb", "utmi-pads";
1366 nvidia,hssync-start-delay = <0>;
1367 nvidia,idle-wait-delay = <17>;
1368 nvidia,elastic-limit = <16>;
1369 nvidia,term-range-adj = <6>;
1370 nvidia,xcvr-setup = <9>;
1371 nvidia,xcvr-lsfslew = <0>;
1372 nvidia,xcvr-lsrslew = <3>;
1373 nvidia,hssquelch-level = <2>;
1374 nvidia,hsdiscon-level = <5>;
1375 nvidia,xcvr-hsslew = <12>;
1376 status = "disabled";
1380 #address-cells = <1>;
1384 device_type = "cpu";
1385 compatible = "arm,cortex-a57";
1387 clocks = <&tegra_car TEGRA210_CLK_CCLK_G>,
1388 <&tegra_car TEGRA210_CLK_PLL_X>,
1389 <&tegra_car TEGRA210_CLK_PLL_P_OUT4>,
1391 clock-names = "cpu_g", "pll_x", "pll_p", "dfll";
1392 clock-latency = <300000>;
1393 cpu-idle-states = <&CPU_SLEEP>;
1394 next-level-cache = <&L2>;
1398 device_type = "cpu";
1399 compatible = "arm,cortex-a57";
1401 cpu-idle-states = <&CPU_SLEEP>;
1402 next-level-cache = <&L2>;
1406 device_type = "cpu";
1407 compatible = "arm,cortex-a57";
1409 cpu-idle-states = <&CPU_SLEEP>;
1410 next-level-cache = <&L2>;
1414 device_type = "cpu";
1415 compatible = "arm,cortex-a57";
1417 cpu-idle-states = <&CPU_SLEEP>;
1418 next-level-cache = <&L2>;
1422 entry-method = "psci";
1424 CPU_SLEEP: cpu-sleep {
1425 compatible = "arm,idle-state";
1426 arm,psci-suspend-param = <0x40000007>;
1427 entry-latency-us = <100>;
1428 exit-latency-us = <30>;
1429 min-residency-us = <1000>;
1430 wakeup-latency-us = <130>;
1431 idle-state-name = "cpu-sleep";
1432 status = "disabled";
1437 compatible = "cache";
1442 compatible = "arm,armv8-timer";
1443 interrupts = <GIC_PPI 13
1444 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1446 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1448 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1450 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1451 interrupt-parent = <&gic>;
1452 arm,no-tick-in-suspend;
1455 soctherm: thermal-sensor@700e2000 {
1456 compatible = "nvidia,tegra210-soctherm";
1457 reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */
1458 0x0 0x60006000 0x0 0x400>; /* CAR reg_base */
1459 reg-names = "soctherm-reg", "car-reg";
1460 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1461 clocks = <&tegra_car TEGRA210_CLK_TSENSOR>,
1462 <&tegra_car TEGRA210_CLK_SOC_THERM>;
1463 clock-names = "tsensor", "soctherm";
1464 resets = <&tegra_car 78>;
1465 reset-names = "soctherm";
1466 #thermal-sensor-cells = <1>;
1469 throttle_heavy: heavy {
1470 nvidia,priority = <100>;
1471 nvidia,cpu-throt-percent = <85>;
1473 #cooling-cells = <2>;
1480 polling-delay-passive = <1000>;
1481 polling-delay = <0>;
1484 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
1488 temperature = <102500>;
1493 cpu_throttle_trip: throttle-trip {
1494 temperature = <98500>;
1495 hysteresis = <1000>;
1502 trip = <&cpu_throttle_trip>;
1503 cooling-device = <&throttle_heavy 1 1>;
1508 polling-delay-passive = <0>;
1509 polling-delay = <0>;
1512 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>;
1516 temperature = <103000>;
1524 * There are currently no cooling maps,
1525 * because there are no cooling devices.
1530 polling-delay-passive = <1000>;
1531 polling-delay = <0>;
1534 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>;
1538 temperature = <103000>;
1543 gpu_throttle_trip: throttle-trip {
1544 temperature = <100000>;
1545 hysteresis = <1000>;
1552 trip = <&gpu_throttle_trip>;
1553 cooling-device = <&throttle_heavy 1 1>;
1558 polling-delay-passive = <0>;
1559 polling-delay = <0>;
1562 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>;
1565 pllx-shutdown-trip {
1566 temperature = <103000>;
1574 * There are currently no cooling maps,
1575 * because there are no cooling devices.