sys/gnu/dts/arm64/nvidia/tegra210.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include <dt-bindings/clock/tegra210-car.h>
   3 #include <dt-bindings/gpio/tegra-gpio.h>
   4 #include <dt-bindings/memory/tegra210-mc.h>
   5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
   6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
   7 #include <dt-bindings/reset/tegra210-car.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/thermal/tegra124-soctherm.h>
  10
  11 / {
  12         compatible = "nvidia,tegra210";
  13         interrupt-parent = <&lic>;
  14         #address-cells = <2>;
  15         #size-cells = <2>;
  16
  17         pcie@1003000 {
  18                 compatible = "nvidia,tegra210-pcie";
  19                 device_type = "pci";
  20                 reg = <0x0 0x01003000 0x0 0x00000800   /* PADS registers */
  21                        0x0 0x01003800 0x0 0x00000800   /* AFI registers */
  22                        0x0 0x02000000 0x0 0x10000000>; /* configuration space */
  23                 reg-names = "pads", "afi", "cs";
  24                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
  25                              <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
  26                 interrupt-names = "intr", "msi";
  27
  28                 #interrupt-cells = <1>;
  29                 interrupt-map-mask = <0 0 0 0>;
  30                 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
  31
  32                 bus-range = <0x00 0xff>;
  33                 #address-cells = <3>;
  34                 #size-cells = <2>;
  35
  36                 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000   /* port 0 configuration space */
  37                           0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000   /* port 1 configuration space */
  38                           0x81000000 0 0x0        0x0 0x12000000 0 0x00010000   /* downstream I/O (64 KiB) */
  39                           0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000   /* non-prefetchable memory (208 MiB) */
  40                           0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
  41
  42                 clocks = <&tegra_car TEGRA210_CLK_PCIE>,
  43                          <&tegra_car TEGRA210_CLK_AFI>,
  44                          <&tegra_car TEGRA210_CLK_PLL_E>,
  45                          <&tegra_car TEGRA210_CLK_CML0>;
  46                 clock-names = "pex", "afi", "pll_e", "cml";
  47                 resets = <&tegra_car 70>,
  48                          <&tegra_car 72>,
  49                          <&tegra_car 74>;
  50                 reset-names = "pex", "afi", "pcie_x";
  51
  52                 pinctrl-names = "default", "idle";
  53                 pinctrl-0 = <&pex_dpd_disable>;
  54                 pinctrl-1 = <&pex_dpd_enable>;
  55
  56                 status = "disabled";
  57
  58                 pci@1,0 {
  59                         device_type = "pci";
  60                         assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
  61                         reg = <0x000800 0 0 0 0>;
  62                         bus-range = <0x00 0xff>;
  63                         status = "disabled";
  64
  65                         #address-cells = <3>;
  66                         #size-cells = <2>;
  67                         ranges;
  68
  69                         nvidia,num-lanes = <4>;
  70                 };
  71
  72                 pci@2,0 {
  73                         device_type = "pci";
  74                         assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
  75                         reg = <0x001000 0 0 0 0>;
  76                         bus-range = <0x00 0xff>;
  77                         status = "disabled";
  78
  79                         #address-cells = <3>;
  80                         #size-cells = <2>;
  81                         ranges;
  82
  83                         nvidia,num-lanes = <1>;
  84                 };
  85         };
  86
  87         host1x@50000000 {
  88                 compatible = "nvidia,tegra210-host1x", "simple-bus";
  89                 reg = <0x0 0x50000000 0x0 0x00034000>;
  90                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
  91                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
  92                 clocks = <&tegra_car TEGRA210_CLK_HOST1X>;
  93                 clock-names = "host1x";
  94                 resets = <&tegra_car 28>;
  95                 reset-names = "host1x";
  96
  97                 #address-cells = <2>;
  98                 #size-cells = <2>;
  99
 100                 ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>;
 101
 102                 iommus = <&mc TEGRA_SWGROUP_HC>;
 103
 104                 dpaux1: dpaux@54040000 {
 105                         compatible = "nvidia,tegra210-dpaux";
 106                         reg = <0x0 0x54040000 0x0 0x00040000>;
 107                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 108                         clocks = <&tegra_car TEGRA210_CLK_DPAUX1>,
 109                                  <&tegra_car TEGRA210_CLK_PLL_DP>;
 110                         clock-names = "dpaux", "parent";
 111                         resets = <&tegra_car 207>;
 112                         reset-names = "dpaux";
 113                         power-domains = <&pd_sor>;
 114                         status = "disabled";
 115
 116                         state_dpaux1_aux: pinmux-aux {
 117                                 groups = "dpaux-io";
 118                                 function = "aux";
 119                         };
 120
 121                         state_dpaux1_i2c: pinmux-i2c {
 122                                 groups = "dpaux-io";
 123                                 function = "i2c";
 124                         };
 125
 126                         state_dpaux1_off: pinmux-off {
 127                                 groups = "dpaux-io";
 128                                 function = "off";
 129                         };
 130
 131                         i2c-bus {
 132                                 #address-cells = <1>;
 133                                 #size-cells = <0>;
 134                         };
 135                 };
 136
 137                 vi@54080000 {
 138                         compatible = "nvidia,tegra210-vi";
 139                         reg = <0x0 0x54080000 0x0 0x00040000>;
 140                         interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 141                         status = "disabled";
 142                 };
 143
 144                 tsec@54100000 {
 145                         compatible = "nvidia,tegra210-tsec";
 146                         reg = <0x0 0x54100000 0x0 0x00040000>;
 147                 };
 148
 149                 dc@54200000 {
 150                         compatible = "nvidia,tegra210-dc";
 151                         reg = <0x0 0x54200000 0x0 0x00040000>;
 152                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 153                         clocks = <&tegra_car TEGRA210_CLK_DISP1>,
 154                                  <&tegra_car TEGRA210_CLK_PLL_P>;
 155                         clock-names = "dc", "parent";
 156                         resets = <&tegra_car 27>;
 157                         reset-names = "dc";
 158
 159                         iommus = <&mc TEGRA_SWGROUP_DC>;
 160
 161                         nvidia,head = <0>;
 162                 };
 163
 164                 dc@54240000 {
 165                         compatible = "nvidia,tegra210-dc";
 166                         reg = <0x0 0x54240000 0x0 0x00040000>;
 167                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 168                         clocks = <&tegra_car TEGRA210_CLK_DISP2>,
 169                                  <&tegra_car TEGRA210_CLK_PLL_P>;
 170                         clock-names = "dc", "parent";
 171                         resets = <&tegra_car 26>;
 172                         reset-names = "dc";
 173
 174                         iommus = <&mc TEGRA_SWGROUP_DCB>;
 175
 176                         nvidia,head = <1>;
 177                 };
 178
 179                 dsi@54300000 {
 180                         compatible = "nvidia,tegra210-dsi";
 181                         reg = <0x0 0x54300000 0x0 0x00040000>;
 182                         clocks = <&tegra_car TEGRA210_CLK_DSIA>,
 183                                  <&tegra_car TEGRA210_CLK_DSIALP>,
 184                                  <&tegra_car TEGRA210_CLK_PLL_D_OUT0>;
 185                         clock-names = "dsi", "lp", "parent";
 186                         resets = <&tegra_car 48>;
 187                         reset-names = "dsi";
 188                         power-domains = <&pd_sor>;
 189                         nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */
 190
 191                         status = "disabled";
 192
 193                         #address-cells = <1>;
 194                         #size-cells = <0>;
 195                 };
 196
 197                 vic@54340000 {
 198                         compatible = "nvidia,tegra210-vic";
 199                         reg = <0x0 0x54340000 0x0 0x00040000>;
 200                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 201                         clocks = <&tegra_car TEGRA210_CLK_VIC03>;
 202                         clock-names = "vic";
 203                         resets = <&tegra_car 178>;
 204                         reset-names = "vic";
 205
 206                         iommus = <&mc TEGRA_SWGROUP_VIC>;
 207                         power-domains = <&pd_vic>;
 208                 };
 209
 210                 nvjpg@54380000 {
 211                         compatible = "nvidia,tegra210-nvjpg";
 212                         reg = <0x0 0x54380000 0x0 0x00040000>;
 213                         status = "disabled";
 214                 };
 215
 216                 dsi@54400000 {
 217                         compatible = "nvidia,tegra210-dsi";
 218                         reg = <0x0 0x54400000 0x0 0x00040000>;
 219                         clocks = <&tegra_car TEGRA210_CLK_DSIB>,
 220                                  <&tegra_car TEGRA210_CLK_DSIBLP>,
 221                                  <&tegra_car TEGRA210_CLK_PLL_D_OUT0>;
 222                         clock-names = "dsi", "lp", "parent";
 223                         resets = <&tegra_car 82>;
 224                         reset-names = "dsi";
 225                         power-domains = <&pd_sor>;
 226                         nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */
 227
 228                         status = "disabled";
 229
 230                         #address-cells = <1>;
 231                         #size-cells = <0>;
 232                 };
 233
 234                 nvdec@54480000 {
 235                         compatible = "nvidia,tegra210-nvdec";
 236                         reg = <0x0 0x54480000 0x0 0x00040000>;
 237                         status = "disabled";
 238                 };
 239
 240                 nvenc@544c0000 {
 241                         compatible = "nvidia,tegra210-nvenc";
 242                         reg = <0x0 0x544c0000 0x0 0x00040000>;
 243                         status = "disabled";
 244                 };
 245
 246                 tsec@54500000 {
 247                         compatible = "nvidia,tegra210-tsec";
 248                         reg = <0x0 0x54500000 0x0 0x00040000>;
 249                         status = "disabled";
 250                 };
 251
 252                 sor@54540000 {
 253                         compatible = "nvidia,tegra210-sor";
 254                         reg = <0x0 0x54540000 0x0 0x00040000>;
 255                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 256                         clocks = <&tegra_car TEGRA210_CLK_SOR0>,
 257                                  <&tegra_car TEGRA210_CLK_SOR0_OUT>,
 258                                  <&tegra_car TEGRA210_CLK_PLL_D_OUT0>,
 259                                  <&tegra_car TEGRA210_CLK_PLL_DP>,
 260                                  <&tegra_car TEGRA210_CLK_SOR_SAFE>;
 261                         clock-names = "sor", "out", "parent", "dp", "safe";
 262                         resets = <&tegra_car 182>;
 263                         reset-names = "sor";
 264                         pinctrl-0 = <&state_dpaux_aux>;
 265                         pinctrl-1 = <&state_dpaux_i2c>;
 266                         pinctrl-2 = <&state_dpaux_off>;
 267                         pinctrl-names = "aux", "i2c", "off";
 268                         power-domains = <&pd_sor>;
 269                         status = "disabled";
 270                 };
 271
 272                 sor@54580000 {
 273                         compatible = "nvidia,tegra210-sor1";
 274                         reg = <0x0 0x54580000 0x0 0x00040000>;
 275                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 276                         clocks = <&tegra_car TEGRA210_CLK_SOR1>,
 277                                  <&tegra_car TEGRA210_CLK_SOR1_OUT>,
 278                                  <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>,
 279                                  <&tegra_car TEGRA210_CLK_PLL_DP>,
 280                                  <&tegra_car TEGRA210_CLK_SOR_SAFE>;
 281                         clock-names = "sor", "out", "parent", "dp", "safe";
 282                         resets = <&tegra_car 183>;
 283                         reset-names = "sor";
 284                         pinctrl-0 = <&state_dpaux1_aux>;
 285                         pinctrl-1 = <&state_dpaux1_i2c>;
 286                         pinctrl-2 = <&state_dpaux1_off>;
 287                         pinctrl-names = "aux", "i2c", "off";
 288                         power-domains = <&pd_sor>;
 289                         status = "disabled";
 290                 };
 291
 292                 dpaux: dpaux@545c0000 {
 293                         compatible = "nvidia,tegra124-dpaux";
 294                         reg = <0x0 0x545c0000 0x0 0x00040000>;
 295                         interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
 296                         clocks = <&tegra_car TEGRA210_CLK_DPAUX>,
 297                                  <&tegra_car TEGRA210_CLK_PLL_DP>;
 298                         clock-names = "dpaux", "parent";
 299                         resets = <&tegra_car 181>;
 300                         reset-names = "dpaux";
 301                         power-domains = <&pd_sor>;
 302                         status = "disabled";
 303
 304                         state_dpaux_aux: pinmux-aux {
 305                                 groups = "dpaux-io";
 306                                 function = "aux";
 307                         };
 308
 309                         state_dpaux_i2c: pinmux-i2c {
 310                                 groups = "dpaux-io";
 311                                 function = "i2c";
 312                         };
 313
 314                         state_dpaux_off: pinmux-off {
 315                                 groups = "dpaux-io";
 316                                 function = "off";
 317                         };
 318
 319                         i2c-bus {
 320                                 #address-cells = <1>;
 321                                 #size-cells = <0>;
 322                         };
 323                 };
 324
 325                 isp@54600000 {
 326                         compatible = "nvidia,tegra210-isp";
 327                         reg = <0x0 0x54600000 0x0 0x00040000>;
 328                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 329                         status = "disabled";
 330                 };
 331
 332                 isp@54680000 {
 333                         compatible = "nvidia,tegra210-isp";
 334                         reg = <0x0 0x54680000 0x0 0x00040000>;
 335                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 336                         status = "disabled";
 337                 };
 338
 339                 i2c@546c0000 {
 340                         compatible = "nvidia,tegra210-i2c-vi";
 341                         reg = <0x0 0x546c0000 0x0 0x00040000>;
 342                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 343                         status = "disabled";
 344                 };
 345         };
 346
 347         gic: interrupt-controller@50041000 {
 348                 compatible = "arm,gic-400";
 349                 #interrupt-cells = <3>;
 350                 interrupt-controller;
 351                 reg = <0x0 0x50041000 0x0 0x1000>,
 352                       <0x0 0x50042000 0x0 0x2000>,
 353                       <0x0 0x50044000 0x0 0x2000>,
 354                       <0x0 0x50046000 0x0 0x2000>;
 355                 interrupts = <GIC_PPI 9
 356                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 357                 interrupt-parent = <&gic>;
 358         };
 359
 360         gpu@57000000 {
 361                 compatible = "nvidia,gm20b";
 362                 reg = <0x0 0x57000000 0x0 0x01000000>,
 363                       <0x0 0x58000000 0x0 0x01000000>;
 364                 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
 365                              <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
 366                 interrupt-names = "stall", "nonstall";
 367                 clocks = <&tegra_car TEGRA210_CLK_GPU>,
 368                          <&tegra_car TEGRA210_CLK_PLL_P_OUT5>,
 369                          <&tegra_car TEGRA210_CLK_PLL_G_REF>;
 370                 clock-names = "gpu", "pwr", "ref";
 371                 resets = <&tegra_car 184>;
 372                 reset-names = "gpu";
 373
 374                 iommus = <&mc TEGRA_SWGROUP_GPU>;
 375
 376                 status = "disabled";
 377         };
 378
 379         lic: interrupt-controller@60004000 {
 380                 compatible = "nvidia,tegra210-ictlr";
 381                 reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */
 382                       <0x0 0x60004100 0x0 0x40>, /* secondary controller */
 383                       <0x0 0x60004200 0x0 0x40>, /* tertiary controller */
 384                       <0x0 0x60004300 0x0 0x40>, /* quaternary controller */
 385                       <0x0 0x60004400 0x0 0x40>, /* quinary controller */
 386                       <0x0 0x60004500 0x0 0x40>; /* senary controller */
 387                 interrupt-controller;
 388                 #interrupt-cells = <3>;
 389                 interrupt-parent = <&gic>;
 390         };
 391
 392         timer@60005000 {
 393                 compatible = "nvidia,tegra210-timer";
 394                 reg = <0x0 0x60005000 0x0 0x400>;
 395                 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
 396                              <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 397                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 398                              <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 399                              <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
 400                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 401                              <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
 402                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
 403                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
 404                              <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
 405                              <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
 406                              <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
 407                              <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
 408                              <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
 409                 clocks = <&tegra_car TEGRA210_CLK_TIMER>;
 410                 clock-names = "timer";
 411         };
 412
 413         tegra_car: clock@60006000 {
 414                 compatible = "nvidia,tegra210-car";
 415                 reg = <0x0 0x60006000 0x0 0x1000>;
 416                 #clock-cells = <1>;
 417                 #reset-cells = <1>;
 418         };
 419
 420         flow-controller@60007000 {
 421                 compatible = "nvidia,tegra210-flowctrl";
 422                 reg = <0x0 0x60007000 0x0 0x1000>;
 423         };
 424
 425         gpio: gpio@6000d000 {
 426                 compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio";
 427                 reg = <0x0 0x6000d000 0x0 0x1000>;
 428                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
 429                              <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 430                              <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
 431                              <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
 432                              <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 433                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 434                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
 435                              <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
 436                 #gpio-cells = <2>;
 437                 gpio-controller;
 438                 #interrupt-cells = <2>;
 439                 interrupt-controller;
 440         };
 441
 442         apbdma: dma@60020000 {
 443                 compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma";
 444                 reg = <0x0 0x60020000 0x0 0x1400>;
 445                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 446                              <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 447                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 448                              <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 449                              <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
 450                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
 451                              <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
 452                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
 453                              <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 454                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 455                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 456                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 457                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 458                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 459                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 460                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
 461                              <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
 462                              <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
 463                              <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
 464                              <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
 465                              <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
 466                              <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
 467                              <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 468                              <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 469                              <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
 470                              <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
 471                              <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
 472                              <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
 473                              <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
 474                              <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
 475                              <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 476                              <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 477                 clocks = <&tegra_car TEGRA210_CLK_APBDMA>;
 478                 clock-names = "dma";
 479                 resets = <&tegra_car 34>;
 480                 reset-names = "dma";
 481                 #dma-cells = <1>;
 482         };
 483
 484         apbmisc@70000800 {
 485                 compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc";
 486                 reg = <0x0 0x70000800 0x0 0x64>,   /* Chip revision */
 487                       <0x0 0x70000008 0x0 0x04>;   /* Strapping options */
 488         };
 489
 490         pinmux: pinmux@700008d4 {
 491                 compatible = "nvidia,tegra210-pinmux";
 492                 reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */
 493                       <0x0 0x70003000 0x0 0x294>; /* Mux registers */
 494                 sdmmc1_3v3_drv: sdmmc1-3v3-drv {
 495                         sdmmc1 {
 496                                 nvidia,pins = "drive_sdmmc1";
 497                                 nvidia,pull-down-strength = <0x8>;
 498                                 nvidia,pull-up-strength = <0x8>;
 499                         };
 500                 };
 501                 sdmmc1_1v8_drv: sdmmc1-1v8-drv {
 502                         sdmmc1 {
 503                                 nvidia,pins = "drive_sdmmc1";
 504                                 nvidia,pull-down-strength = <0x4>;
 505                                 nvidia,pull-up-strength = <0x3>;
 506                         };
 507                 };
 508                 sdmmc2_1v8_drv: sdmmc2-1v8-drv {
 509                         sdmmc2 {
 510                                 nvidia,pins = "drive_sdmmc2";
 511                                 nvidia,pull-down-strength = <0x10>;
 512                                 nvidia,pull-up-strength = <0x10>;
 513                         };
 514                 };
 515                 sdmmc3_3v3_drv: sdmmc3-3v3-drv {
 516                         sdmmc3 {
 517                                 nvidia,pins = "drive_sdmmc3";
 518                                 nvidia,pull-down-strength = <0x8>;
 519                                 nvidia,pull-up-strength = <0x8>;
 520                         };
 521                 };
 522                 sdmmc3_1v8_drv: sdmmc3-1v8-drv {
 523                         sdmmc3 {
 524                                 nvidia,pins = "drive_sdmmc3";
 525                                 nvidia,pull-down-strength = <0x4>;
 526                                 nvidia,pull-up-strength = <0x3>;
 527                         };
 528                 };
 529                 sdmmc4_1v8_drv: sdmmc4-1v8-drv {
 530                         sdmmc4 {
 531                                 nvidia,pins = "drive_sdmmc4";
 532                                 nvidia,pull-down-strength = <0x10>;
 533                                 nvidia,pull-up-strength = <0x10>;
 534                         };
 535                 };
 536         };
 537
 538         /*
 539          * There are two serial driver i.e. 8250 based simple serial
 540          * driver and APB DMA based serial driver for higher baudrate
 541          * and performance. To enable the 8250 based driver, the compatible
 542          * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
 543          * the APB DMA based serial driver, the compatible is
 544          * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
 545          */
 546         uarta: serial@70006000 {
 547                 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
 548                 reg = <0x0 0x70006000 0x0 0x40>;
 549                 reg-shift = <2>;
 550                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 551                 clocks = <&tegra_car TEGRA210_CLK_UARTA>;
 552                 clock-names = "serial";
 553                 resets = <&tegra_car 6>;
 554                 reset-names = "serial";
 555                 dmas = <&apbdma 8>, <&apbdma 8>;
 556                 dma-names = "rx", "tx";
 557                 status = "disabled";
 558         };
 559
 560         uartb: serial@70006040 {
 561                 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
 562                 reg = <0x0 0x70006040 0x0 0x40>;
 563                 reg-shift = <2>;
 564                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 565                 clocks = <&tegra_car TEGRA210_CLK_UARTB>;
 566                 clock-names = "serial";
 567                 resets = <&tegra_car 7>;
 568                 reset-names = "serial";
 569                 dmas = <&apbdma 9>, <&apbdma 9>;
 570                 dma-names = "rx", "tx";
 571                 status = "disabled";
 572         };
 573
 574         uartc: serial@70006200 {
 575                 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
 576                 reg = <0x0 0x70006200 0x0 0x40>;
 577                 reg-shift = <2>;
 578                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 579                 clocks = <&tegra_car TEGRA210_CLK_UARTC>;
 580                 clock-names = "serial";
 581                 resets = <&tegra_car 55>;
 582                 reset-names = "serial";
 583                 dmas = <&apbdma 10>, <&apbdma 10>;
 584                 dma-names = "rx", "tx";
 585                 status = "disabled";
 586         };
 587
 588         uartd: serial@70006300 {
 589                 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
 590                 reg = <0x0 0x70006300 0x0 0x40>;
 591                 reg-shift = <2>;
 592                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 593                 clocks = <&tegra_car TEGRA210_CLK_UARTD>;
 594                 clock-names = "serial";
 595                 resets = <&tegra_car 65>;
 596                 reset-names = "serial";
 597                 dmas = <&apbdma 19>, <&apbdma 19>;
 598                 dma-names = "rx", "tx";
 599                 status = "disabled";
 600         };
 601
 602         pwm: pwm@7000a000 {
 603                 compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm";
 604                 reg = <0x0 0x7000a000 0x0 0x100>;
 605                 #pwm-cells = <2>;
 606                 clocks = <&tegra_car TEGRA210_CLK_PWM>;
 607                 clock-names = "pwm";
 608                 resets = <&tegra_car 17>;
 609                 reset-names = "pwm";
 610                 status = "disabled";
 611         };
 612
 613         i2c@7000c000 {
 614                 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
 615                 reg = <0x0 0x7000c000 0x0 0x100>;
 616                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 617                 #address-cells = <1>;
 618                 #size-cells = <0>;
 619                 clocks = <&tegra_car TEGRA210_CLK_I2C1>;
 620                 clock-names = "div-clk";
 621                 resets = <&tegra_car 12>;
 622                 reset-names = "i2c";
 623                 dmas = <&apbdma 21>, <&apbdma 21>;
 624                 dma-names = "rx", "tx";
 625                 status = "disabled";
 626         };
 627
 628         i2c@7000c400 {
 629                 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
 630                 reg = <0x0 0x7000c400 0x0 0x100>;
 631                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 632                 #address-cells = <1>;
 633                 #size-cells = <0>;
 634                 clocks = <&tegra_car TEGRA210_CLK_I2C2>;
 635                 clock-names = "div-clk";
 636                 resets = <&tegra_car 54>;
 637                 reset-names = "i2c";
 638                 dmas = <&apbdma 22>, <&apbdma 22>;
 639                 dma-names = "rx", "tx";
 640                 status = "disabled";
 641         };
 642
 643         i2c@7000c500 {
 644                 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
 645                 reg = <0x0 0x7000c500 0x0 0x100>;
 646                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 647                 #address-cells = <1>;
 648                 #size-cells = <0>;
 649                 clocks = <&tegra_car TEGRA210_CLK_I2C3>;
 650                 clock-names = "div-clk";
 651                 resets = <&tegra_car 67>;
 652                 reset-names = "i2c";
 653                 dmas = <&apbdma 23>, <&apbdma 23>;
 654                 dma-names = "rx", "tx";
 655                 status = "disabled";
 656         };
 657
 658         i2c@7000c700 {
 659                 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
 660                 reg = <0x0 0x7000c700 0x0 0x100>;
 661                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
 662                 #address-cells = <1>;
 663                 #size-cells = <0>;
 664                 clocks = <&tegra_car TEGRA210_CLK_I2C4>;
 665                 clock-names = "div-clk";
 666                 resets = <&tegra_car 103>;
 667                 reset-names = "i2c";
 668                 dmas = <&apbdma 26>, <&apbdma 26>;
 669                 dma-names = "rx", "tx";
 670                 pinctrl-0 = <&state_dpaux1_i2c>;
 671                 pinctrl-1 = <&state_dpaux1_off>;
 672                 pinctrl-names = "default", "idle";
 673                 status = "disabled";
 674         };
 675
 676         i2c@7000d000 {
 677                 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
 678                 reg = <0x0 0x7000d000 0x0 0x100>;
 679                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 680                 #address-cells = <1>;
 681                 #size-cells = <0>;
 682                 clocks = <&tegra_car TEGRA210_CLK_I2C5>;
 683                 clock-names = "div-clk";
 684                 resets = <&tegra_car 47>;
 685                 reset-names = "i2c";
 686                 dmas = <&apbdma 24>, <&apbdma 24>;
 687                 dma-names = "rx", "tx";
 688                 status = "disabled";
 689         };
 690
 691         i2c@7000d100 {
 692                 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
 693                 reg = <0x0 0x7000d100 0x0 0x100>;
 694                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 695                 #address-cells = <1>;
 696                 #size-cells = <0>;
 697                 clocks = <&tegra_car TEGRA210_CLK_I2C6>;
 698                 clock-names = "div-clk";
 699                 resets = <&tegra_car 166>;
 700                 reset-names = "i2c";
 701                 dmas = <&apbdma 30>, <&apbdma 30>;
 702                 dma-names = "rx", "tx";
 703                 pinctrl-0 = <&state_dpaux_i2c>;
 704                 pinctrl-1 = <&state_dpaux_off>;
 705                 pinctrl-names = "default", "idle";
 706                 status = "disabled";
 707         };
 708
 709         spi@7000d400 {
 710                 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
 711                 reg = <0x0 0x7000d400 0x0 0x200>;
 712                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 713                 #address-cells = <1>;
 714                 #size-cells = <0>;
 715                 clocks = <&tegra_car TEGRA210_CLK_SBC1>;
 716                 clock-names = "spi";
 717                 resets = <&tegra_car 41>;
 718                 reset-names = "spi";
 719                 dmas = <&apbdma 15>, <&apbdma 15>;
 720                 dma-names = "rx", "tx";
 721                 status = "disabled";
 722         };
 723
 724         spi@7000d600 {
 725                 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
 726                 reg = <0x0 0x7000d600 0x0 0x200>;
 727                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 728                 #address-cells = <1>;
 729                 #size-cells = <0>;
 730                 clocks = <&tegra_car TEGRA210_CLK_SBC2>;
 731                 clock-names = "spi";
 732                 resets = <&tegra_car 44>;
 733                 reset-names = "spi";
 734                 dmas = <&apbdma 16>, <&apbdma 16>;
 735                 dma-names = "rx", "tx";
 736                 status = "disabled";
 737         };
 738
 739         spi@7000d800 {
 740                 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
 741                 reg = <0x0 0x7000d800 0x0 0x200>;
 742                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 743                 #address-cells = <1>;
 744                 #size-cells = <0>;
 745                 clocks = <&tegra_car TEGRA210_CLK_SBC3>;
 746                 clock-names = "spi";
 747                 resets = <&tegra_car 46>;
 748                 reset-names = "spi";
 749                 dmas = <&apbdma 17>, <&apbdma 17>;
 750                 dma-names = "rx", "tx";
 751                 status = "disabled";
 752         };
 753
 754         spi@7000da00 {
 755                 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
 756                 reg = <0x0 0x7000da00 0x0 0x200>;
 757                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 758                 #address-cells = <1>;
 759                 #size-cells = <0>;
 760                 clocks = <&tegra_car TEGRA210_CLK_SBC4>;
 761                 clock-names = "spi";
 762                 resets = <&tegra_car 68>;
 763                 reset-names = "spi";
 764                 dmas = <&apbdma 18>, <&apbdma 18>;
 765                 dma-names = "rx", "tx";
 766                 status = "disabled";
 767         };
 768
 769         rtc@7000e000 {
 770                 compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc";
 771                 reg = <0x0 0x7000e000 0x0 0x100>;
 772                 interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
 773                 interrupt-parent = <&pmc>;
 774                 clocks = <&tegra_car TEGRA210_CLK_RTC>;
 775                 clock-names = "rtc";
 776         };
 777
 778         pmc: pmc@7000e400 {
 779                 compatible = "nvidia,tegra210-pmc";
 780                 reg = <0x0 0x7000e400 0x0 0x400>;
 781                 clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
 782                 clock-names = "pclk", "clk32k_in";
 783                 #interrupt-cells = <2>;
 784                 interrupt-controller;
 785
 786                 powergates {
 787                         pd_audio: aud {
 788                                 clocks = <&tegra_car TEGRA210_CLK_APE>,
 789                                          <&tegra_car TEGRA210_CLK_APB2APE>;
 790                                 resets = <&tegra_car 198>;
 791                                 #power-domain-cells = <0>;
 792                         };
 793
 794                         pd_sor: sor {
 795                                 clocks = <&tegra_car TEGRA210_CLK_SOR0>,
 796                                          <&tegra_car TEGRA210_CLK_SOR1>,
 797                                          <&tegra_car TEGRA210_CLK_CSI>,
 798                                          <&tegra_car TEGRA210_CLK_DSIA>,
 799                                          <&tegra_car TEGRA210_CLK_DSIB>,
 800                                          <&tegra_car TEGRA210_CLK_DPAUX>,
 801                                          <&tegra_car TEGRA210_CLK_DPAUX1>,
 802                                          <&tegra_car TEGRA210_CLK_MIPI_CAL>;
 803                                 resets = <&tegra_car TEGRA210_CLK_SOR0>,
 804                                          <&tegra_car TEGRA210_CLK_SOR1>,
 805                                          <&tegra_car TEGRA210_CLK_CSI>,
 806                                          <&tegra_car TEGRA210_CLK_DSIA>,
 807                                          <&tegra_car TEGRA210_CLK_DSIB>,
 808                                          <&tegra_car TEGRA210_CLK_DPAUX>,
 809                                          <&tegra_car TEGRA210_CLK_DPAUX1>,
 810                                          <&tegra_car TEGRA210_CLK_MIPI_CAL>;
 811                                 #power-domain-cells = <0>;
 812                         };
 813
 814                         pd_xusbss: xusba {
 815                                 clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>;
 816                                 resets = <&tegra_car TEGRA210_CLK_XUSB_SS>;
 817                                 #power-domain-cells = <0>;
 818                         };
 819
 820                         pd_xusbdev: xusbb {
 821                                 clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>;
 822                                 resets = <&tegra_car 95>;
 823                                 #power-domain-cells = <0>;
 824                         };
 825
 826                         pd_xusbhost: xusbc {
 827                                 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>;
 828                                 resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>;
 829                                 #power-domain-cells = <0>;
 830                         };
 831
 832                         pd_vic: vic {
 833                                 clocks = <&tegra_car TEGRA210_CLK_VIC03>;
 834                                 clock-names = "vic";
 835                                 resets = <&tegra_car 178>;
 836                                 reset-names = "vic";
 837                                 #power-domain-cells = <0>;
 838                         };
 839                 };
 840
 841                 sdmmc1_3v3: sdmmc1-3v3 {
 842                         pins = "sdmmc1";
 843                         power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
 844                 };
 845
 846                 sdmmc1_1v8: sdmmc1-1v8 {
 847                         pins = "sdmmc1";
 848                         power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
 849                 };
 850
 851                 sdmmc3_3v3: sdmmc3-3v3 {
 852                         pins = "sdmmc3";
 853                         power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
 854                 };
 855
 856                 sdmmc3_1v8: sdmmc3-1v8 {
 857                         pins = "sdmmc3";
 858                         power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
 859                 };
 860
 861                 pex_dpd_disable: pex_en {
 862                         pex-dpd-disable {
 863                                 pins = "pex-bias", "pex-clk1", "pex-clk2";
 864                                 low-power-disable;
 865                         };
 866                 };
 867
 868                 pex_dpd_enable: pex_dis {
 869                         pex-dpd-enable {
 870                                 pins = "pex-bias", "pex-clk1", "pex-clk2";
 871                                 low-power-enable;
 872                         };
 873                 };
 874         };
 875
 876         fuse@7000f800 {
 877                 compatible = "nvidia,tegra210-efuse";
 878                 reg = <0x0 0x7000f800 0x0 0x400>;
 879                 clocks = <&tegra_car TEGRA210_CLK_FUSE>;
 880                 clock-names = "fuse";
 881                 resets = <&tegra_car 39>;
 882                 reset-names = "fuse";
 883         };
 884
 885         mc: memory-controller@70019000 {
 886                 compatible = "nvidia,tegra210-mc";
 887                 reg = <0x0 0x70019000 0x0 0x1000>;
 888                 clocks = <&tegra_car TEGRA210_CLK_MC>;
 889                 clock-names = "mc";
 890
 891                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 892
 893                 #iommu-cells = <1>;
 894         };
 895
 896         sata@70020000 {
 897                 compatible = "nvidia,tegra210-ahci";
 898                 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
 899                       <0x0 0x70020000 0x0 0x7000>, /* SATA */
 900                       <0x0 0x70001100 0x0 0x1000>; /* SATA AUX */
 901                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 902                 clocks = <&tegra_car TEGRA210_CLK_SATA>,
 903                          <&tegra_car TEGRA210_CLK_SATA_OOB>;
 904                 clock-names = "sata", "sata-oob";
 905                 resets = <&tegra_car 124>,
 906                          <&tegra_car 123>,
 907                          <&tegra_car 129>;
 908                 reset-names = "sata", "sata-oob", "sata-cold";
 909                 status = "disabled";
 910         };
 911
 912         hda@70030000 {
 913                 compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda";
 914                 reg = <0x0 0x70030000 0x0 0x10000>;
 915                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 916                 clocks = <&tegra_car TEGRA210_CLK_HDA>,
 917                          <&tegra_car TEGRA210_CLK_HDA2HDMI>,
 918                          <&tegra_car TEGRA210_CLK_HDA2CODEC_2X>;
 919                 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
 920                 resets = <&tegra_car 125>, /* hda */
 921                          <&tegra_car 128>, /* hda2hdmi */
 922                          <&tegra_car 111>; /* hda2codec_2x */
 923                 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
 924                 status = "disabled";
 925         };
 926
 927         usb@70090000 {
 928                 compatible = "nvidia,tegra210-xusb";
 929                 reg = <0x0 0x70090000 0x0 0x8000>,
 930                       <0x0 0x70098000 0x0 0x1000>,
 931                       <0x0 0x70099000 0x0 0x1000>;
 932                 reg-names = "hcd", "fpci", "ipfs";
 933
 934                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
 935                              <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 936
 937                 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>,
 938                          <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>,
 939                          <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>,
 940                          <&tegra_car TEGRA210_CLK_XUSB_SS>,
 941                          <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>,
 942                          <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>,
 943                          <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>,
 944                          <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>,
 945                          <&tegra_car TEGRA210_CLK_PLL_U_480M>,
 946                          <&tegra_car TEGRA210_CLK_CLK_M>,
 947                          <&tegra_car TEGRA210_CLK_PLL_E>;
 948                 clock-names = "xusb_host", "xusb_host_src",
 949                               "xusb_falcon_src", "xusb_ss",
 950                               "xusb_ss_div2", "xusb_ss_src",
 951                               "xusb_hs_src", "xusb_fs_src",
 952                               "pll_u_480m", "clk_m", "pll_e";
 953                 resets = <&tegra_car 89>, <&tegra_car 156>,
 954                          <&tegra_car 143>;
 955                 reset-names = "xusb_host", "xusb_ss", "xusb_src";
 956                 power-domains = <&pd_xusbhost>, <&pd_xusbss>;
 957                 power-domain-names = "xusb_host", "xusb_ss";
 958
 959                 nvidia,xusb-padctl = <&padctl>;
 960
 961                 status = "disabled";
 962         };
 963
 964         padctl: padctl@7009f000 {
 965                 compatible = "nvidia,tegra210-xusb-padctl";
 966                 reg = <0x0 0x7009f000 0x0 0x1000>;
 967                 resets = <&tegra_car 142>;
 968                 reset-names = "padctl";
 969
 970                 status = "disabled";
 971
 972                 pads {
 973                         usb2 {
 974                                 clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>;
 975                                 clock-names = "trk";
 976                                 status = "disabled";
 977
 978                                 lanes {
 979                                         usb2-0 {
 980                                                 status = "disabled";
 981                                                 #phy-cells = <0>;
 982                                         };
 983
 984                                         usb2-1 {
 985                                                 status = "disabled";
 986                                                 #phy-cells = <0>;
 987                                         };
 988
 989                                         usb2-2 {
 990                                                 status = "disabled";
 991                                                 #phy-cells = <0>;
 992                                         };
 993
 994                                         usb2-3 {
 995                                                 status = "disabled";
 996                                                 #phy-cells = <0>;
 997                                         };
 998                                 };
 999                         };
1000
1001                         hsic {
1002                                 clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>;
1003                                 clock-names = "trk";
1004                                 status = "disabled";
1005
1006                                 lanes {
1007                                         hsic-0 {
1008                                                 status = "disabled";
1009                                                 #phy-cells = <0>;
1010                                         };
1011
1012                                         hsic-1 {
1013                                                 status = "disabled";
1014                                                 #phy-cells = <0>;
1015                                         };
1016                                 };
1017                         };
1018
1019                         pcie {
1020                                 clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
1021                                 clock-names = "pll";
1022                                 resets = <&tegra_car 205>;
1023                                 reset-names = "phy";
1024                                 status = "disabled";
1025
1026                                 lanes {
1027                                         pcie-0 {
1028                                                 status = "disabled";
1029                                                 #phy-cells = <0>;
1030                                         };
1031
1032                                         pcie-1 {
1033                                                 status = "disabled";
1034                                                 #phy-cells = <0>;
1035                                         };
1036
1037                                         pcie-2 {
1038                                                 status = "disabled";
1039                                                 #phy-cells = <0>;
1040                                         };
1041
1042                                         pcie-3 {
1043                                                 status = "disabled";
1044                                                 #phy-cells = <0>;
1045                                         };
1046
1047                                         pcie-4 {
1048                                                 status = "disabled";
1049                                                 #phy-cells = <0>;
1050                                         };
1051
1052                                         pcie-5 {
1053                                                 status = "disabled";
1054                                                 #phy-cells = <0>;
1055                                         };
1056
1057                                         pcie-6 {
1058                                                 status = "disabled";
1059                                                 #phy-cells = <0>;
1060                                         };
1061                                 };
1062                         };
1063
1064                         sata {
1065                                 clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
1066                                 clock-names = "pll";
1067                                 resets = <&tegra_car 204>;
1068                                 reset-names = "phy";
1069                                 status = "disabled";
1070
1071                                 lanes {
1072                                         sata-0 {
1073                                                 status = "disabled";
1074                                                 #phy-cells = <0>;
1075                                         };
1076                                 };
1077                         };
1078                 };
1079
1080                 ports {
1081                         usb2-0 {
1082                                 status = "disabled";
1083                         };
1084
1085                         usb2-1 {
1086                                 status = "disabled";
1087                         };
1088
1089                         usb2-2 {
1090                                 status = "disabled";
1091                         };
1092
1093                         usb2-3 {
1094                                 status = "disabled";
1095                         };
1096
1097                         hsic-0 {
1098                                 status = "disabled";
1099                         };
1100
1101                         usb3-0 {
1102                                 status = "disabled";
1103                         };
1104
1105                         usb3-1 {
1106                                 status = "disabled";
1107                         };
1108
1109                         usb3-2 {
1110                                 status = "disabled";
1111                         };
1112
1113                         usb3-3 {
1114                                 status = "disabled";
1115                         };
1116                 };
1117         };
1118
1119         sdhci@700b0000 {
1120                 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
1121                 reg = <0x0 0x700b0000 0x0 0x200>;
1122                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1123                 clocks = <&tegra_car TEGRA210_CLK_SDMMC1>;
1124                 clock-names = "sdhci";
1125                 resets = <&tegra_car 14>;
1126                 reset-names = "sdhci";
1127                 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8",
1128                                 "sdmmc-3v3-drv", "sdmmc-1v8-drv";
1129                 pinctrl-0 = <&sdmmc1_3v3>;
1130                 pinctrl-1 = <&sdmmc1_1v8>;
1131                 pinctrl-2 = <&sdmmc1_3v3_drv>;
1132                 pinctrl-3 = <&sdmmc1_1v8_drv>;
1133                 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
1134                 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
1135                 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
1136                 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
1137                 nvidia,default-tap = <0x2>;
1138                 nvidia,default-trim = <0x4>;
1139                 assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
1140                                   <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>,
1141                                   <&tegra_car TEGRA210_CLK_PLL_C4>;
1142                 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
1143                 assigned-clock-rates = <200000000>, <1000000000>, <1000000000>;
1144                 status = "disabled";
1145         };
1146
1147         sdhci@700b0200 {
1148                 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
1149                 reg = <0x0 0x700b0200 0x0 0x200>;
1150                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1151                 clocks = <&tegra_car TEGRA210_CLK_SDMMC2>;
1152                 clock-names = "sdhci";
1153                 resets = <&tegra_car 9>;
1154                 reset-names = "sdhci";
1155                 pinctrl-names = "sdmmc-1v8-drv";
1156                 pinctrl-0 = <&sdmmc2_1v8_drv>;
1157                 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>;
1158                 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>;
1159                 nvidia,default-tap = <0x8>;
1160                 nvidia,default-trim = <0x0>;
1161                 status = "disabled";
1162         };
1163
1164         sdhci@700b0400 {
1165                 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
1166                 reg = <0x0 0x700b0400 0x0 0x200>;
1167                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1168                 clocks = <&tegra_car TEGRA210_CLK_SDMMC3>;
1169                 clock-names = "sdhci";
1170                 resets = <&tegra_car 69>;
1171                 reset-names = "sdhci";
1172                 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8",
1173                                 "sdmmc-3v3-drv", "sdmmc-1v8-drv";
1174                 pinctrl-0 = <&sdmmc3_3v3>;
1175                 pinctrl-1 = <&sdmmc3_1v8>;
1176                 pinctrl-2 = <&sdmmc3_3v3_drv>;
1177                 pinctrl-3 = <&sdmmc3_1v8_drv>;
1178                 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
1179                 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
1180                 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
1181                 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
1182                 nvidia,default-tap = <0x3>;
1183                 nvidia,default-trim = <0x3>;
1184                 status = "disabled";
1185         };
1186
1187         sdhci@700b0600 {
1188                 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
1189                 reg = <0x0 0x700b0600 0x0 0x200>;
1190                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1191                 clocks = <&tegra_car TEGRA210_CLK_SDMMC4>;
1192                 clock-names = "sdhci";
1193                 resets = <&tegra_car 15>;
1194                 reset-names = "sdhci";
1195                 pinctrl-names = "sdmmc-3v3-drv", "sdmmc-1v8-drv";
1196                 pinctrl-0 = <&sdmmc4_1v8_drv>;
1197                 pinctrl-1 = <&sdmmc4_1v8_drv>;
1198                 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>;
1199                 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>;
1200                 nvidia,default-tap = <0x8>;
1201                 nvidia,default-trim = <0x0>;
1202                 assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
1203                                   <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
1204                 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
1205                 nvidia,dqs-trim = <40>;
1206                 mmc-hs400-1_8v;
1207                 status = "disabled";
1208         };
1209
1210         mipi: mipi@700e3000 {
1211                 compatible = "nvidia,tegra210-mipi";
1212                 reg = <0x0 0x700e3000 0x0 0x100>;
1213                 clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>;
1214                 clock-names = "mipi-cal";
1215                 power-domains = <&pd_sor>;
1216                 #nvidia,mipi-calibrate-cells = <1>;
1217         };
1218
1219         dfll: clock@70110000 {
1220                 compatible = "nvidia,tegra210-dfll";
1221                 reg = <0 0x70110000 0 0x100>, /* DFLL control */
1222                       <0 0x70110000 0 0x100>, /* I2C output control */
1223                       <0 0x70110100 0 0x100>, /* Integrated I2C controller */
1224                       <0 0x70110200 0 0x100>; /* Look-up table RAM */
1225                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1226                 clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>,
1227                          <&tegra_car TEGRA210_CLK_DFLL_REF>,
1228                          <&tegra_car TEGRA210_CLK_I2C5>;
1229                 clock-names = "soc", "ref", "i2c";
1230                 resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>;
1231                 reset-names = "dvco";
1232                 #clock-cells = <0>;
1233                 clock-output-names = "dfllCPU_out";
1234                 status = "disabled";
1235         };
1236
1237         aconnect@702c0000 {
1238                 compatible = "nvidia,tegra210-aconnect";
1239                 clocks = <&tegra_car TEGRA210_CLK_APE>,
1240                          <&tegra_car TEGRA210_CLK_APB2APE>;
1241                 clock-names = "ape", "apb2ape";
1242                 power-domains = <&pd_audio>;
1243                 #address-cells = <1>;
1244                 #size-cells = <1>;
1245                 ranges = <0x702c0000 0x0 0x702c0000 0x00040000>;
1246                 status = "disabled";
1247
1248                 adma: dma@702e2000 {
1249                         compatible = "nvidia,tegra210-adma";
1250                         reg = <0x702e2000 0x2000>;
1251                         interrupt-parent = <&agic>;
1252                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
1253                                      <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
1254                                      <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
1255                                      <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
1256                                      <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
1257                                      <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
1258                                      <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
1259                                      <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
1260                                      <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
1261                                      <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
1262                                      <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
1263                                      <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
1264                                      <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
1265                                      <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
1266                                      <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
1267                                      <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
1268                                      <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1269                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
1270                                      <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
1271                                      <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
1272                                      <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
1273                                      <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1274                         #dma-cells = <1>;
1275                         clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
1276                         clock-names = "d_audio";
1277                         status = "disabled";
1278                 };
1279
1280                 agic: agic@702f9000 {
1281                         compatible = "nvidia,tegra210-agic";
1282                         #interrupt-cells = <3>;
1283                         interrupt-controller;
1284                         reg = <0x702f9000 0x1000>,
1285                               <0x702fa000 0x2000>;
1286                         interrupts = <GIC_SPI 102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1287                         clocks = <&tegra_car TEGRA210_CLK_APE>;
1288                         clock-names = "clk";
1289                         status = "disabled";
1290                 };
1291         };
1292
1293         spi@70410000 {
1294                 compatible = "nvidia,tegra210-qspi";
1295                 reg = <0x0 0x70410000 0x0 0x1000>;
1296                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1297                 #address-cells = <1>;
1298                 #size-cells = <0>;
1299                 clocks = <&tegra_car TEGRA210_CLK_QSPI>;
1300                 clock-names = "qspi";
1301                 resets = <&tegra_car 211>;
1302                 reset-names = "qspi";
1303                 dmas = <&apbdma 5>, <&apbdma 5>;
1304                 dma-names = "rx", "tx";
1305                 status = "disabled";
1306         };
1307
1308         usb@7d000000 {
1309                 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1310                 reg = <0x0 0x7d000000 0x0 0x4000>;
1311                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1312                 phy_type = "utmi";
1313                 clocks = <&tegra_car TEGRA210_CLK_USBD>;
1314                 clock-names = "usb";
1315                 resets = <&tegra_car 22>;
1316                 reset-names = "usb";
1317                 nvidia,phy = <&phy1>;
1318                 status = "disabled";
1319         };
1320
1321         phy1: usb-phy@7d000000 {
1322                 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy";
1323                 reg = <0x0 0x7d000000 0x0 0x4000>,
1324                       <0x0 0x7d000000 0x0 0x4000>;
1325                 phy_type = "utmi";
1326                 clocks = <&tegra_car TEGRA210_CLK_USBD>,
1327                          <&tegra_car TEGRA210_CLK_PLL_U>,
1328                          <&tegra_car TEGRA210_CLK_USBD>;
1329                 clock-names = "reg", "pll_u", "utmi-pads";
1330                 resets = <&tegra_car 22>, <&tegra_car 22>;
1331                 reset-names = "usb", "utmi-pads";
1332                 nvidia,hssync-start-delay = <0>;
1333                 nvidia,idle-wait-delay = <17>;
1334                 nvidia,elastic-limit = <16>;
1335                 nvidia,term-range-adj = <6>;
1336                 nvidia,xcvr-setup = <9>;
1337                 nvidia,xcvr-lsfslew = <0>;
1338                 nvidia,xcvr-lsrslew = <3>;
1339                 nvidia,hssquelch-level = <2>;
1340                 nvidia,hsdiscon-level = <5>;
1341                 nvidia,xcvr-hsslew = <12>;
1342                 nvidia,has-utmi-pad-registers;
1343                 status = "disabled";
1344         };
1345
1346         usb@7d004000 {
1347                 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1348                 reg = <0x0 0x7d004000 0x0 0x4000>;
1349                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1350                 phy_type = "utmi";
1351                 clocks = <&tegra_car TEGRA210_CLK_USB2>;
1352                 clock-names = "usb";
1353                 resets = <&tegra_car 58>;
1354                 reset-names = "usb";
1355                 nvidia,phy = <&phy2>;
1356                 status = "disabled";
1357         };
1358
1359         phy2: usb-phy@7d004000 {
1360                 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy";
1361                 reg = <0x0 0x7d004000 0x0 0x4000>,
1362                       <0x0 0x7d000000 0x0 0x4000>;
1363                 phy_type = "utmi";
1364                 clocks = <&tegra_car TEGRA210_CLK_USB2>,
1365                          <&tegra_car TEGRA210_CLK_PLL_U>,
1366                          <&tegra_car TEGRA210_CLK_USBD>;
1367                 clock-names = "reg", "pll_u", "utmi-pads";
1368                 resets = <&tegra_car 58>, <&tegra_car 22>;
1369                 reset-names = "usb", "utmi-pads";
1370                 nvidia,hssync-start-delay = <0>;
1371                 nvidia,idle-wait-delay = <17>;
1372                 nvidia,elastic-limit = <16>;
1373                 nvidia,term-range-adj = <6>;
1374                 nvidia,xcvr-setup = <9>;
1375                 nvidia,xcvr-lsfslew = <0>;
1376                 nvidia,xcvr-lsrslew = <3>;
1377                 nvidia,hssquelch-level = <2>;
1378                 nvidia,hsdiscon-level = <5>;
1379                 nvidia,xcvr-hsslew = <12>;
1380                 status = "disabled";
1381         };
1382
1383         cpus {
1384                 #address-cells = <1>;
1385                 #size-cells = <0>;
1386
1387                 cpu@0 {
1388                         device_type = "cpu";
1389                         compatible = "arm,cortex-a57";
1390                         reg = <0>;
1391                         clocks = <&tegra_car TEGRA210_CLK_CCLK_G>,
1392                                  <&tegra_car TEGRA210_CLK_PLL_X>,
1393                                  <&tegra_car TEGRA210_CLK_PLL_P_OUT4>,
1394                                  <&dfll>;
1395                         clock-names = "cpu_g", "pll_x", "pll_p", "dfll";
1396                         clock-latency = <300000>;
1397                         cpu-idle-states = <&CPU_SLEEP>;
1398                         next-level-cache = <&L2>;
1399                 };
1400
1401                 cpu@1 {
1402                         device_type = "cpu";
1403                         compatible = "arm,cortex-a57";
1404                         reg = <1>;
1405                         cpu-idle-states = <&CPU_SLEEP>;
1406                         next-level-cache = <&L2>;
1407                 };
1408
1409                 cpu@2 {
1410                         device_type = "cpu";
1411                         compatible = "arm,cortex-a57";
1412                         reg = <2>;
1413                         cpu-idle-states = <&CPU_SLEEP>;
1414                         next-level-cache = <&L2>;
1415                 };
1416
1417                 cpu@3 {
1418                         device_type = "cpu";
1419                         compatible = "arm,cortex-a57";
1420                         reg = <3>;
1421                         cpu-idle-states = <&CPU_SLEEP>;
1422                         next-level-cache = <&L2>;
1423                 };
1424
1425                 idle-states {
1426                         entry-method = "psci";
1427
1428                         CPU_SLEEP: cpu-sleep {
1429                                 compatible = "arm,idle-state";
1430                                 arm,psci-suspend-param = <0x40000007>;
1431                                 entry-latency-us = <100>;
1432                                 exit-latency-us = <30>;
1433                                 min-residency-us = <1000>;
1434                                 wakeup-latency-us = <130>;
1435                                 idle-state-name = "cpu-sleep";
1436                                 status = "disabled";
1437                         };
1438                 };
1439
1440                 L2: l2-cache {
1441                         compatible = "cache";
1442                 };
1443         };
1444
1445         pmu {
1446                 compatible = "arm,armv8-pmuv3";
1447                 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
1448                              <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1449                              <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1450                              <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
1451                 interrupt-affinity = <&{/cpus/cpu@0} &{/cpus/cpu@1}
1452                                       &{/cpus/cpu@2} &{/cpus/cpu@3}>;
1453         };
1454
1455         timer {
1456                 compatible = "arm,armv8-timer";
1457                 interrupts = <GIC_PPI 13
1458                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1459                              <GIC_PPI 14
1460                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1461                              <GIC_PPI 11
1462                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1463                              <GIC_PPI 10
1464                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1465                 interrupt-parent = <&gic>;
1466                 arm,no-tick-in-suspend;
1467         };
1468
1469         soctherm: thermal-sensor@700e2000 {
1470                 compatible = "nvidia,tegra210-soctherm";
1471                 reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */
1472                         0x0 0x60006000 0x0 0x400>; /* CAR reg_base */
1473                 reg-names = "soctherm-reg", "car-reg";
1474                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
1475                              <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1476                 interrupt-names = "thermal", "edp";
1477                 clocks = <&tegra_car TEGRA210_CLK_TSENSOR>,
1478                         <&tegra_car TEGRA210_CLK_SOC_THERM>;
1479                 clock-names = "tsensor", "soctherm";
1480                 resets = <&tegra_car 78>;
1481                 reset-names = "soctherm";
1482                 #thermal-sensor-cells = <1>;
1483
1484                 throttle-cfgs {
1485                         throttle_heavy: heavy {
1486                                 nvidia,priority = <100>;
1487                                 nvidia,cpu-throt-percent = <85>;
1488
1489                                 #cooling-cells = <2>;
1490                         };
1491                 };
1492         };
1493
1494         thermal-zones {
1495                 cpu {
1496                         polling-delay-passive = <1000>;
1497                         polling-delay = <0>;
1498
1499                         thermal-sensors =
1500                                 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
1501
1502                         trips {
1503                                 cpu-shutdown-trip {
1504                                         temperature = <102500>;
1505                                         hysteresis = <0>;
1506                                         type = "critical";
1507                                 };
1508
1509                                 cpu_throttle_trip: throttle-trip {
1510                                         temperature = <98500>;
1511                                         hysteresis = <1000>;
1512                                         type = "hot";
1513                                 };
1514                         };
1515
1516                         cooling-maps {
1517                                 map0 {
1518                                         trip = <&cpu_throttle_trip>;
1519                                         cooling-device = <&throttle_heavy 1 1>;
1520                                 };
1521                         };
1522                 };
1523
1524                 mem {
1525                         polling-delay-passive = <0>;
1526                         polling-delay = <0>;
1527
1528                         thermal-sensors =
1529                                 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>;
1530
1531                         trips {
1532                                 mem-shutdown-trip {
1533                                         temperature = <103000>;
1534                                         hysteresis = <0>;
1535                                         type = "critical";
1536                                 };
1537                         };
1538
1539                         cooling-maps {
1540                                 /*
1541                                  * There are currently no cooling maps,
1542                                  * because there are no cooling devices.
1543                                  */
1544                         };
1545                 };
1546
1547                 gpu {
1548                         polling-delay-passive = <1000>;
1549                         polling-delay = <0>;
1550
1551                         thermal-sensors =
1552                                 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>;
1553
1554                         trips {
1555                                 gpu-shutdown-trip {
1556                                         temperature = <103000>;
1557                                         hysteresis = <0>;
1558                                         type = "critical";
1559                                 };
1560
1561                                 gpu_throttle_trip: throttle-trip {
1562                                         temperature = <100000>;
1563                                         hysteresis = <1000>;
1564                                         type = "hot";
1565                                 };
1566                         };
1567
1568                         cooling-maps {
1569                                 map0 {
1570                                         trip = <&gpu_throttle_trip>;
1571                                         cooling-device = <&throttle_heavy 1 1>;
1572                                 };
1573                         };
1574                 };
1575
1576                 pllx {
1577                         polling-delay-passive = <0>;
1578                         polling-delay = <0>;
1579
1580                         thermal-sensors =
1581                                 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>;
1582
1583                         trips {
1584                                 pllx-shutdown-trip {
1585                                         temperature = <103000>;
1586                                         hysteresis = <0>;
1587                                         type = "critical";
1588                                 };
1589                         };
1590
1591                         cooling-maps {
1592                                 /*
1593                                  * There are currently no cooling maps,
1594                                  * because there are no cooling devices.
1595                                  */
1596                         };
1597                 };
1598         };
1599 };