sys/gnu/dts/arm64/qcom/msm8916.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <dt-bindings/arm/coresight-cti-dt.h>
   7 #include <dt-bindings/interrupt-controller/arm-gic.h>
   8 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
   9 #include <dt-bindings/reset/qcom,gcc-msm8916.h>
  10 #include <dt-bindings/clock/qcom,rpmcc.h>
  11 #include <dt-bindings/thermal/thermal.h>
  12
  13 / {
  14         interrupt-parent = <&intc>;
  15
  16         #address-cells = <2>;
  17         #size-cells = <2>;
  18
  19         aliases {
  20                 sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
  21                 sdhc2 = &sdhc_2; /* SDC2 SD card slot */
  22         };
  23
  24         chosen { };
  25
  26         memory {
  27                 device_type = "memory";
  28                 /* We expect the bootloader to fill in the reg */
  29                 reg = <0 0 0 0>;
  30         };
  31
  32         reserved-memory {
  33                 #address-cells = <2>;
  34                 #size-cells = <2>;
  35                 ranges;
  36
  37                 tz-apps@86000000 {
  38                         reg = <0x0 0x86000000 0x0 0x300000>;
  39                         no-map;
  40                 };
  41
  42                 smem_mem: smem_region@86300000 {
  43                         reg = <0x0 0x86300000 0x0 0x100000>;
  44                         no-map;
  45                 };
  46
  47                 hypervisor@86400000 {
  48                         reg = <0x0 0x86400000 0x0 0x100000>;
  49                         no-map;
  50                 };
  51
  52                 tz@86500000 {
  53                         reg = <0x0 0x86500000 0x0 0x180000>;
  54                         no-map;
  55                 };
  56
  57                 reserved@8668000 {
  58                         reg = <0x0 0x86680000 0x0 0x80000>;
  59                         no-map;
  60                 };
  61
  62                 rmtfs@86700000 {
  63                         compatible = "qcom,rmtfs-mem";
  64                         reg = <0x0 0x86700000 0x0 0xe0000>;
  65                         no-map;
  66
  67                         qcom,client-id = <1>;
  68                 };
  69
  70                 rfsa@867e00000 {
  71                         reg = <0x0 0x867e0000 0x0 0x20000>;
  72                         no-map;
  73                 };
  74
  75                 mpss_mem: mpss@86800000 {
  76                         reg = <0x0 0x86800000 0x0 0x2b00000>;
  77                         no-map;
  78                 };
  79
  80                 wcnss_mem: wcnss@89300000 {
  81                         reg = <0x0 0x89300000 0x0 0x600000>;
  82                         no-map;
  83                 };
  84
  85                 venus_mem: venus@89900000 {
  86                         reg = <0x0 0x89900000 0x0 0x600000>;
  87                         no-map;
  88                 };
  89
  90                 mba_mem: mba@8ea00000 {
  91                         no-map;
  92                         reg = <0 0x8ea00000 0 0x100000>;
  93                 };
  94         };
  95
  96         cpus {
  97                 #address-cells = <1>;
  98                 #size-cells = <0>;
  99
 100                 CPU0: cpu@0 {
 101                         device_type = "cpu";
 102                         compatible = "arm,cortex-a53";
 103                         reg = <0x0>;
 104                         next-level-cache = <&L2_0>;
 105                         enable-method = "psci";
 106                         clocks = <&apcs>;
 107                         operating-points-v2 = <&cpu_opp_table>;
 108                         #cooling-cells = <2>;
 109                         power-domains = <&CPU_PD0>;
 110                         power-domain-names = "psci";
 111                 };
 112
 113                 CPU1: cpu@1 {
 114                         device_type = "cpu";
 115                         compatible = "arm,cortex-a53";
 116                         reg = <0x1>;
 117                         next-level-cache = <&L2_0>;
 118                         enable-method = "psci";
 119                         clocks = <&apcs>;
 120                         operating-points-v2 = <&cpu_opp_table>;
 121                         #cooling-cells = <2>;
 122                         power-domains = <&CPU_PD1>;
 123                         power-domain-names = "psci";
 124                 };
 125
 126                 CPU2: cpu@2 {
 127                         device_type = "cpu";
 128                         compatible = "arm,cortex-a53";
 129                         reg = <0x2>;
 130                         next-level-cache = <&L2_0>;
 131                         enable-method = "psci";
 132                         clocks = <&apcs>;
 133                         operating-points-v2 = <&cpu_opp_table>;
 134                         #cooling-cells = <2>;
 135                         power-domains = <&CPU_PD2>;
 136                         power-domain-names = "psci";
 137                 };
 138
 139                 CPU3: cpu@3 {
 140                         device_type = "cpu";
 141                         compatible = "arm,cortex-a53";
 142                         reg = <0x3>;
 143                         next-level-cache = <&L2_0>;
 144                         enable-method = "psci";
 145                         clocks = <&apcs>;
 146                         operating-points-v2 = <&cpu_opp_table>;
 147                         #cooling-cells = <2>;
 148                         power-domains = <&CPU_PD3>;
 149                         power-domain-names = "psci";
 150                 };
 151
 152                 L2_0: l2-cache {
 153                       compatible = "cache";
 154                       cache-level = <2>;
 155                 };
 156
 157                 idle-states {
 158                         entry-method = "psci";
 159
 160                         CPU_SLEEP_0: cpu-sleep-0 {
 161                                 compatible = "arm,idle-state";
 162                                 idle-state-name = "standalone-power-collapse";
 163                                 arm,psci-suspend-param = <0x40000002>;
 164                                 entry-latency-us = <130>;
 165                                 exit-latency-us = <150>;
 166                                 min-residency-us = <2000>;
 167                                 local-timer-stop;
 168                         };
 169                 };
 170
 171                 domain-idle-states {
 172
 173                         CLUSTER_RET: cluster-retention {
 174                                 compatible = "domain-idle-state";
 175                                 arm,psci-suspend-param = <0x41000012>;
 176                                 entry-latency-us = <500>;
 177                                 exit-latency-us = <500>;
 178                                 min-residency-us = <2000>;
 179                         };
 180
 181                         CLUSTER_PWRDN: cluster-gdhs {
 182                                 compatible = "domain-idle-state";
 183                                 arm,psci-suspend-param = <0x41000032>;
 184                                 entry-latency-us = <2000>;
 185                                 exit-latency-us = <2000>;
 186                                 min-residency-us = <6000>;
 187                         };
 188                 };
 189         };
 190
 191         psci {
 192                 compatible = "arm,psci-1.0";
 193                 method = "smc";
 194
 195                 CPU_PD0: power-domain-cpu0 {
 196                         #power-domain-cells = <0>;
 197                         power-domains = <&CLUSTER_PD>;
 198                         domain-idle-states = <&CPU_SLEEP_0>;
 199                 };
 200
 201                 CPU_PD1: power-domain-cpu1 {
 202                         #power-domain-cells = <0>;
 203                         power-domains = <&CLUSTER_PD>;
 204                         domain-idle-states = <&CPU_SLEEP_0>;
 205                 };
 206
 207                 CPU_PD2: power-domain-cpu2 {
 208                         #power-domain-cells = <0>;
 209                         power-domains = <&CLUSTER_PD>;
 210                         domain-idle-states = <&CPU_SLEEP_0>;
 211                 };
 212
 213                 CPU_PD3: power-domain-cpu3 {
 214                         #power-domain-cells = <0>;
 215                         power-domains = <&CLUSTER_PD>;
 216                         domain-idle-states = <&CPU_SLEEP_0>;
 217                 };
 218
 219                 CLUSTER_PD: power-domain-cluster {
 220                         #power-domain-cells = <0>;
 221                         domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWRDN>;
 222                 };
 223         };
 224
 225         pmu {
 226                 compatible = "arm,cortex-a53-pmu";
 227                 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4)| IRQ_TYPE_LEVEL_HIGH)>;
 228         };
 229
 230         thermal-zones {
 231                 cpu0_1-thermal {
 232                         polling-delay-passive = <250>;
 233                         polling-delay = <1000>;
 234
 235                         thermal-sensors = <&tsens 5>;
 236
 237                         trips {
 238                                 cpu0_1_alert0: trip-point@0 {
 239                                         temperature = <75000>;
 240                                         hysteresis = <2000>;
 241                                         type = "passive";
 242                                 };
 243                                 cpu0_1_crit: cpu_crit {
 244                                         temperature = <110000>;
 245                                         hysteresis = <2000>;
 246                                         type = "critical";
 247                                 };
 248                         };
 249
 250                         cooling-maps {
 251                                 map0 {
 252                                         trip = <&cpu0_1_alert0>;
 253                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 254                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 255                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 256                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 257                                 };
 258                         };
 259                 };
 260
 261                 cpu2_3-thermal {
 262                         polling-delay-passive = <250>;
 263                         polling-delay = <1000>;
 264
 265                         thermal-sensors = <&tsens 4>;
 266
 267                         trips {
 268                                 cpu2_3_alert0: trip-point0 {
 269                                         temperature = <75000>;
 270                                         hysteresis = <2000>;
 271                                         type = "passive";
 272                                 };
 273                                 cpu2_3_crit: cpu_crit {
 274                                         temperature = <110000>;
 275                                         hysteresis = <2000>;
 276                                         type = "critical";
 277                                 };
 278                         };
 279
 280                         cooling-maps {
 281                                 map0 {
 282                                         trip = <&cpu2_3_alert0>;
 283                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 284                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 285                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 286                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 287                                 };
 288                         };
 289                 };
 290
 291                 gpu-thermal {
 292                         polling-delay-passive = <250>;
 293                         polling-delay = <1000>;
 294
 295                         thermal-sensors = <&tsens 2>;
 296
 297                         trips {
 298                                 gpu_alert0: trip-point0 {
 299                                         temperature = <75000>;
 300                                         hysteresis = <2000>;
 301                                         type = "passive";
 302                                 };
 303                                 gpu_crit: gpu_crit {
 304                                         temperature = <95000>;
 305                                         hysteresis = <2000>;
 306                                         type = "critical";
 307                                 };
 308                         };
 309                 };
 310
 311                 camera-thermal {
 312                         polling-delay-passive = <250>;
 313                         polling-delay = <1000>;
 314
 315                         thermal-sensors = <&tsens 1>;
 316
 317                         trips {
 318                                 cam_alert0: trip-point0 {
 319                                         temperature = <75000>;
 320                                         hysteresis = <2000>;
 321                                         type = "hot";
 322                                 };
 323                         };
 324                 };
 325
 326                 modem-thermal {
 327                         polling-delay-passive = <250>;
 328                         polling-delay = <1000>;
 329
 330                         thermal-sensors = <&tsens 0>;
 331
 332                         trips {
 333                                 modem_alert0: trip-point0 {
 334                                         temperature = <85000>;
 335                                         hysteresis = <2000>;
 336                                         type = "hot";
 337                                 };
 338                         };
 339                 };
 340
 341         };
 342
 343         cpu_opp_table: cpu-opp-table {
 344                 compatible = "operating-points-v2";
 345                 opp-shared;
 346
 347                 opp-200000000 {
 348                         opp-hz = /bits/ 64 <200000000>;
 349                 };
 350                 opp-400000000 {
 351                         opp-hz = /bits/ 64 <400000000>;
 352                 };
 353                 opp-800000000 {
 354                         opp-hz = /bits/ 64 <800000000>;
 355                 };
 356                 opp-998400000 {
 357                         opp-hz = /bits/ 64 <998400000>;
 358                 };
 359         };
 360
 361         timer {
 362                 compatible = "arm,armv8-timer";
 363                 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 364                              <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 365                              <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 366                              <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 367         };
 368
 369         clocks {
 370                 xo_board: xo-board {
 371                         compatible = "fixed-clock";
 372                         #clock-cells = <0>;
 373                         clock-frequency = <19200000>;
 374                 };
 375
 376                 sleep_clk: sleep-clk {
 377                         compatible = "fixed-clock";
 378                         #clock-cells = <0>;
 379                         clock-frequency = <32768>;
 380                 };
 381         };
 382
 383         smem {
 384                 compatible = "qcom,smem";
 385
 386                 memory-region = <&smem_mem>;
 387                 qcom,rpm-msg-ram = <&rpm_msg_ram>;
 388
 389                 hwlocks = <&tcsr_mutex 3>;
 390         };
 391
 392         firmware {
 393                 scm: scm {
 394                         compatible = "qcom,scm";
 395                         clocks = <&gcc GCC_CRYPTO_CLK>, <&gcc GCC_CRYPTO_AXI_CLK>, <&gcc GCC_CRYPTO_AHB_CLK>;
 396                         clock-names = "core", "bus", "iface";
 397                         #reset-cells = <1>;
 398
 399                         qcom,dload-mode = <&tcsr 0x6100>;
 400                 };
 401         };
 402
 403         soc: soc {
 404                 #address-cells = <1>;
 405                 #size-cells = <1>;
 406                 ranges = <0 0 0 0xffffffff>;
 407                 compatible = "simple-bus";
 408
 409                 restart@4ab000 {
 410                         compatible = "qcom,pshold";
 411                         reg = <0x4ab000 0x4>;
 412                 };
 413
 414                 msmgpio: pinctrl@1000000 {
 415                         compatible = "qcom,msm8916-pinctrl";
 416                         reg = <0x1000000 0x300000>;
 417                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 418                         gpio-controller;
 419                         gpio-ranges = <&msmgpio 0 0 122>;
 420                         #gpio-cells = <2>;
 421                         interrupt-controller;
 422                         #interrupt-cells = <2>;
 423                 };
 424
 425                 gcc: clock-controller@1800000 {
 426                         compatible = "qcom,gcc-msm8916";
 427                         #clock-cells = <1>;
 428                         #reset-cells = <1>;
 429                         #power-domain-cells = <1>;
 430                         reg = <0x1800000 0x80000>;
 431                 };
 432
 433                 tcsr_mutex_regs: syscon@1905000 {
 434                         compatible = "syscon";
 435                         reg = <0x1905000 0x20000>;
 436                 };
 437
 438                 tcsr: syscon@1937000 {
 439                         compatible = "qcom,tcsr-msm8916", "syscon";
 440                         reg = <0x1937000 0x30000>;
 441                 };
 442
 443                 tcsr_mutex: hwlock {
 444                         compatible = "qcom,tcsr-mutex";
 445                         syscon = <&tcsr_mutex_regs 0 0x1000>;
 446                         #hwlock-cells = <1>;
 447                 };
 448
 449                 rpm_msg_ram: memory@60000 {
 450                         compatible = "qcom,rpm-msg-ram";
 451                         reg = <0x60000 0x8000>;
 452                 };
 453
 454                 blsp1_uart1: serial@78af000 {
 455                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 456                         reg = <0x78af000 0x200>;
 457                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 458                         clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 459                         clock-names = "core", "iface";
 460                         dmas = <&blsp_dma 1>, <&blsp_dma 0>;
 461                         dma-names = "rx", "tx";
 462                         status = "disabled";
 463                 };
 464
 465                 a53pll: clock@b016000 {
 466                         compatible = "qcom,msm8916-a53pll";
 467                         reg = <0xb016000 0x40>;
 468                         #clock-cells = <0>;
 469                 };
 470
 471                 apcs: mailbox@b011000 {
 472                         compatible = "qcom,msm8916-apcs-kpss-global", "syscon";
 473                         reg = <0xb011000 0x1000>;
 474                         #mbox-cells = <1>;
 475                         clocks = <&a53pll>, <&gcc GPLL0_VOTE>;
 476                         clock-names = "pll", "aux";
 477                         #clock-cells = <0>;
 478                 };
 479
 480                 blsp1_uart2: serial@78b0000 {
 481                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 482                         reg = <0x78b0000 0x200>;
 483                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 484                         clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 485                         clock-names = "core", "iface";
 486                         dmas = <&blsp_dma 3>, <&blsp_dma 2>;
 487                         dma-names = "rx", "tx";
 488                         status = "disabled";
 489                 };
 490
 491                 blsp_dma: dma@7884000 {
 492                         compatible = "qcom,bam-v1.7.0";
 493                         reg = <0x07884000 0x23000>;
 494                         interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
 495                         clocks = <&gcc GCC_BLSP1_AHB_CLK>;
 496                         clock-names = "bam_clk";
 497                         #dma-cells = <1>;
 498                         qcom,ee = <0>;
 499                         status = "disabled";
 500                 };
 501
 502                 blsp_spi1: spi@78b5000 {
 503                         compatible = "qcom,spi-qup-v2.2.1";
 504                         reg = <0x078b5000 0x500>;
 505                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 506                         clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
 507                                  <&gcc GCC_BLSP1_AHB_CLK>;
 508                         clock-names = "core", "iface";
 509                         dmas = <&blsp_dma 5>, <&blsp_dma 4>;
 510                         dma-names = "rx", "tx";
 511                         pinctrl-names = "default", "sleep";
 512                         pinctrl-0 = <&spi1_default>;
 513                         pinctrl-1 = <&spi1_sleep>;
 514                         #address-cells = <1>;
 515                         #size-cells = <0>;
 516                         status = "disabled";
 517                 };
 518
 519                 blsp_spi2: spi@78b6000 {
 520                         compatible = "qcom,spi-qup-v2.2.1";
 521                         reg = <0x078b6000 0x500>;
 522                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 523                         clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
 524                                  <&gcc GCC_BLSP1_AHB_CLK>;
 525                         clock-names = "core", "iface";
 526                         dmas = <&blsp_dma 7>, <&blsp_dma 6>;
 527                         dma-names = "rx", "tx";
 528                         pinctrl-names = "default", "sleep";
 529                         pinctrl-0 = <&spi2_default>;
 530                         pinctrl-1 = <&spi2_sleep>;
 531                         #address-cells = <1>;
 532                         #size-cells = <0>;
 533                         status = "disabled";
 534                 };
 535
 536                 blsp_spi3: spi@78b7000 {
 537                         compatible = "qcom,spi-qup-v2.2.1";
 538                         reg = <0x078b7000 0x500>;
 539                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 540                         clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
 541                                  <&gcc GCC_BLSP1_AHB_CLK>;
 542                         clock-names = "core", "iface";
 543                         dmas = <&blsp_dma 9>, <&blsp_dma 8>;
 544                         dma-names = "rx", "tx";
 545                         pinctrl-names = "default", "sleep";
 546                         pinctrl-0 = <&spi3_default>;
 547                         pinctrl-1 = <&spi3_sleep>;
 548                         #address-cells = <1>;
 549                         #size-cells = <0>;
 550                         status = "disabled";
 551                 };
 552
 553                 blsp_spi4: spi@78b8000 {
 554                         compatible = "qcom,spi-qup-v2.2.1";
 555                         reg = <0x078b8000 0x500>;
 556                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 557                         clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
 558                                  <&gcc GCC_BLSP1_AHB_CLK>;
 559                         clock-names = "core", "iface";
 560                         dmas = <&blsp_dma 11>, <&blsp_dma 10>;
 561                         dma-names = "rx", "tx";
 562                         pinctrl-names = "default", "sleep";
 563                         pinctrl-0 = <&spi4_default>;
 564                         pinctrl-1 = <&spi4_sleep>;
 565                         #address-cells = <1>;
 566                         #size-cells = <0>;
 567                         status = "disabled";
 568                 };
 569
 570                 blsp_spi5: spi@78b9000 {
 571                         compatible = "qcom,spi-qup-v2.2.1";
 572                         reg = <0x078b9000 0x500>;
 573                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 574                         clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
 575                                  <&gcc GCC_BLSP1_AHB_CLK>;
 576                         clock-names = "core", "iface";
 577                         dmas = <&blsp_dma 13>, <&blsp_dma 12>;
 578                         dma-names = "rx", "tx";
 579                         pinctrl-names = "default", "sleep";
 580                         pinctrl-0 = <&spi5_default>;
 581                         pinctrl-1 = <&spi5_sleep>;
 582                         #address-cells = <1>;
 583                         #size-cells = <0>;
 584                         status = "disabled";
 585                 };
 586
 587                 blsp_spi6: spi@78ba000 {
 588                         compatible = "qcom,spi-qup-v2.2.1";
 589                         reg = <0x078ba000 0x500>;
 590                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 591                         clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
 592                                  <&gcc GCC_BLSP1_AHB_CLK>;
 593                         clock-names = "core", "iface";
 594                         dmas = <&blsp_dma 15>, <&blsp_dma 14>;
 595                         dma-names = "rx", "tx";
 596                         pinctrl-names = "default", "sleep";
 597                         pinctrl-0 = <&spi6_default>;
 598                         pinctrl-1 = <&spi6_sleep>;
 599                         #address-cells = <1>;
 600                         #size-cells = <0>;
 601                         status = "disabled";
 602                 };
 603
 604                 blsp_i2c1: i2c@78b5000 {
 605                         compatible = "qcom,i2c-qup-v2.2.1";
 606                         reg = <0x078b5000 0x500>;
 607                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 608                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 609                                  <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
 610                         clock-names = "iface", "core";
 611                         pinctrl-names = "default", "sleep";
 612                         pinctrl-0 = <&i2c1_default>;
 613                         pinctrl-1 = <&i2c1_sleep>;
 614                         #address-cells = <1>;
 615                         #size-cells = <0>;
 616                         status = "disabled";
 617                 };
 618
 619                 blsp_i2c2: i2c@78b6000 {
 620                         compatible = "qcom,i2c-qup-v2.2.1";
 621                         reg = <0x078b6000 0x500>;
 622                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 623                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 624                                  <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
 625                         clock-names = "iface", "core";
 626                         pinctrl-names = "default", "sleep";
 627                         pinctrl-0 = <&i2c2_default>;
 628                         pinctrl-1 = <&i2c2_sleep>;
 629                         #address-cells = <1>;
 630                         #size-cells = <0>;
 631                         status = "disabled";
 632                 };
 633
 634                 blsp_i2c4: i2c@78b8000 {
 635                         compatible = "qcom,i2c-qup-v2.2.1";
 636                         reg = <0x078b8000 0x500>;
 637                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 638                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 639                                  <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
 640                         clock-names = "iface", "core";
 641                         pinctrl-names = "default", "sleep";
 642                         pinctrl-0 = <&i2c4_default>;
 643                         pinctrl-1 = <&i2c4_sleep>;
 644                         #address-cells = <1>;
 645                         #size-cells = <0>;
 646                         status = "disabled";
 647                 };
 648
 649                 blsp_i2c5: i2c@78b9000 {
 650                         compatible = "qcom,i2c-qup-v2.2.1";
 651                         reg = <0x078b9000 0x500>;
 652                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 653                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 654                                  <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
 655                         clock-names = "iface", "core";
 656                         pinctrl-names = "default", "sleep";
 657                         pinctrl-0 = <&i2c5_default>;
 658                         pinctrl-1 = <&i2c5_sleep>;
 659                         #address-cells = <1>;
 660                         #size-cells = <0>;
 661                         status = "disabled";
 662                 };
 663
 664                 blsp_i2c6: i2c@78ba000 {
 665                         compatible = "qcom,i2c-qup-v2.2.1";
 666                         reg = <0x078ba000 0x500>;
 667                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 668                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 669                                  <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
 670                         clock-names = "iface", "core";
 671                         pinctrl-names = "default", "sleep";
 672                         pinctrl-0 = <&i2c6_default>;
 673                         pinctrl-1 = <&i2c6_sleep>;
 674                         #address-cells = <1>;
 675                         #size-cells = <0>;
 676                         status = "disabled";
 677                 };
 678
 679                 lpass: lpass@7708000 {
 680                         status = "disabled";
 681                         compatible = "qcom,lpass-cpu-apq8016";
 682                         clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
 683                                  <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>,
 684                                  <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>,
 685                                  <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
 686                                  <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
 687                                  <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
 688                                  <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>;
 689
 690                         clock-names = "ahbix-clk",
 691                                         "pcnoc-mport-clk",
 692                                         "pcnoc-sway-clk",
 693                                         "mi2s-bit-clk0",
 694                                         "mi2s-bit-clk1",
 695                                         "mi2s-bit-clk2",
 696                                         "mi2s-bit-clk3";
 697                         #sound-dai-cells = <1>;
 698
 699                         interrupts = <0 160 IRQ_TYPE_LEVEL_HIGH>;
 700                         interrupt-names = "lpass-irq-lpaif";
 701                         reg = <0x07708000 0x10000>;
 702                         reg-names = "lpass-lpaif";
 703                 };
 704
 705                 lpass_codec: codec{
 706                         compatible = "qcom,msm8916-wcd-digital-codec";
 707                         reg = <0x0771c000 0x400>;
 708                         clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
 709                                  <&gcc GCC_CODEC_DIGCODEC_CLK>;
 710                         clock-names = "ahbix-clk", "mclk";
 711                         #sound-dai-cells = <1>;
 712                 };
 713
 714                 sdhc_1: sdhci@7824000 {
 715                         compatible = "qcom,sdhci-msm-v4";
 716                         reg = <0x07824900 0x11c>, <0x07824000 0x800>;
 717                         reg-names = "hc_mem", "core_mem";
 718
 719                         interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>, <0 138 IRQ_TYPE_LEVEL_HIGH>;
 720                         interrupt-names = "hc_irq", "pwr_irq";
 721                         clocks = <&gcc GCC_SDCC1_APPS_CLK>,
 722                                  <&gcc GCC_SDCC1_AHB_CLK>,
 723                                  <&xo_board>;
 724                         clock-names = "core", "iface", "xo";
 725                         mmc-ddr-1_8v;
 726                         bus-width = <8>;
 727                         non-removable;
 728                         status = "disabled";
 729                 };
 730
 731                 sdhc_2: sdhci@7864000 {
 732                         compatible = "qcom,sdhci-msm-v4";
 733                         reg = <0x07864900 0x11c>, <0x07864000 0x800>;
 734                         reg-names = "hc_mem", "core_mem";
 735
 736                         interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>, <0 221 IRQ_TYPE_LEVEL_HIGH>;
 737                         interrupt-names = "hc_irq", "pwr_irq";
 738                         clocks = <&gcc GCC_SDCC2_APPS_CLK>,
 739                                  <&gcc GCC_SDCC2_AHB_CLK>,
 740                                  <&xo_board>;
 741                         clock-names = "core", "iface", "xo";
 742                         bus-width = <4>;
 743                         status = "disabled";
 744                 };
 745
 746                 otg: usb@78d9000 {
 747                         compatible = "qcom,ci-hdrc";
 748                         reg = <0x78d9000 0x200>,
 749                               <0x78d9200 0x200>;
 750                         interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 751                                      <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
 752                         clocks = <&gcc GCC_USB_HS_AHB_CLK>,
 753                                  <&gcc GCC_USB_HS_SYSTEM_CLK>;
 754                         clock-names = "iface", "core";
 755                         assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
 756                         assigned-clock-rates = <80000000>;
 757                         resets = <&gcc GCC_USB_HS_BCR>;
 758                         reset-names = "core";
 759                         phy_type = "ulpi";
 760                         dr_mode = "otg";
 761                         ahb-burst-config = <0>;
 762                         phy-names = "usb-phy";
 763                         phys = <&usb_hs_phy>;
 764                         status = "disabled";
 765                         #reset-cells = <1>;
 766
 767                         ulpi {
 768                                 usb_hs_phy: phy {
 769                                         compatible = "qcom,usb-hs-phy-msm8916",
 770                                                      "qcom,usb-hs-phy";
 771                                         #phy-cells = <0>;
 772                                         clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
 773                                         clock-names = "ref", "sleep";
 774                                         resets = <&gcc GCC_USB2A_PHY_BCR>, <&otg 0>;
 775                                         reset-names = "phy", "por";
 776                                         qcom,init-seq = /bits/ 8 <0x0 0x44
 777                                                 0x1 0x6b 0x2 0x24 0x3 0x13>;
 778                                 };
 779                         };
 780                 };
 781
 782                 intc: interrupt-controller@b000000 {
 783                         compatible = "qcom,msm-qgic2";
 784                         interrupt-controller;
 785                         #interrupt-cells = <3>;
 786                         reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
 787                 };
 788
 789                 timer@b020000 {
 790                         #address-cells = <1>;
 791                         #size-cells = <1>;
 792                         ranges;
 793                         compatible = "arm,armv7-timer-mem";
 794                         reg = <0xb020000 0x1000>;
 795                         clock-frequency = <19200000>;
 796
 797                         frame@b021000 {
 798                                 frame-number = <0>;
 799                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 800                                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 801                                 reg = <0xb021000 0x1000>,
 802                                       <0xb022000 0x1000>;
 803                         };
 804
 805                         frame@b023000 {
 806                                 frame-number = <1>;
 807                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 808                                 reg = <0xb023000 0x1000>;
 809                                 status = "disabled";
 810                         };
 811
 812                         frame@b024000 {
 813                                 frame-number = <2>;
 814                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 815                                 reg = <0xb024000 0x1000>;
 816                                 status = "disabled";
 817                         };
 818
 819                         frame@b025000 {
 820                                 frame-number = <3>;
 821                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 822                                 reg = <0xb025000 0x1000>;
 823                                 status = "disabled";
 824                         };
 825
 826                         frame@b026000 {
 827                                 frame-number = <4>;
 828                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 829                                 reg = <0xb026000 0x1000>;
 830                                 status = "disabled";
 831                         };
 832
 833                         frame@b027000 {
 834                                 frame-number = <5>;
 835                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 836                                 reg = <0xb027000 0x1000>;
 837                                 status = "disabled";
 838                         };
 839
 840                         frame@b028000 {
 841                                 frame-number = <6>;
 842                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 843                                 reg = <0xb028000 0x1000>;
 844                                 status = "disabled";
 845                         };
 846                 };
 847
 848                 spmi_bus: spmi@200f000 {
 849                         compatible = "qcom,spmi-pmic-arb";
 850                         reg = <0x200f000 0x001000>,
 851                               <0x2400000 0x400000>,
 852                               <0x2c00000 0x400000>,
 853                               <0x3800000 0x200000>,
 854                               <0x200a000 0x002100>;
 855                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
 856                         interrupt-names = "periph_irq";
 857                         interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
 858                         qcom,ee = <0>;
 859                         qcom,channel = <0>;
 860                         #address-cells = <2>;
 861                         #size-cells = <0>;
 862                         interrupt-controller;
 863                         #interrupt-cells = <4>;
 864                 };
 865
 866                 rng@22000 {
 867                         compatible = "qcom,prng";
 868                         reg = <0x00022000 0x200>;
 869                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 870                         clock-names = "core";
 871                 };
 872
 873                 qfprom: qfprom@5c000 {
 874                         compatible = "qcom,qfprom";
 875                         reg = <0x5c000 0x1000>;
 876                         #address-cells = <1>;
 877                         #size-cells = <1>;
 878                         tsens_caldata: caldata@d0 {
 879                                 reg = <0xd0 0x8>;
 880                         };
 881                         tsens_calsel: calsel@ec {
 882                                 reg = <0xec 0x4>;
 883                         };
 884                 };
 885
 886                 tsens: thermal-sensor@4a9000 {
 887                         compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1";
 888                         reg = <0x4a9000 0x1000>, /* TM */
 889                               <0x4a8000 0x1000>; /* SROT */
 890                         nvmem-cells = <&tsens_caldata>, <&tsens_calsel>;
 891                         nvmem-cell-names = "calib", "calib_sel";
 892                         #qcom,sensors = <5>;
 893                         interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
 894                         interrupt-names = "uplow";
 895                         #thermal-sensor-cells = <1>;
 896                 };
 897
 898                 apps_iommu: iommu@1ef0000 {
 899                         #address-cells = <1>;
 900                         #size-cells = <1>;
 901                         #iommu-cells = <1>;
 902                         compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
 903                         ranges = <0 0x1e20000 0x40000>;
 904                         reg = <0x1ef0000 0x3000>;
 905                         clocks = <&gcc GCC_SMMU_CFG_CLK>,
 906                                  <&gcc GCC_APSS_TCU_CLK>;
 907                         clock-names = "iface", "bus";
 908                         qcom,iommu-secure-id = <17>;
 909
 910                         // vfe:
 911                         iommu-ctx@3000 {
 912                                 compatible = "qcom,msm-iommu-v1-sec";
 913                                 reg = <0x3000 0x1000>;
 914                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 915                         };
 916
 917                         // mdp_0:
 918                         iommu-ctx@4000 {
 919                                 compatible = "qcom,msm-iommu-v1-ns";
 920                                 reg = <0x4000 0x1000>;
 921                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 922                         };
 923
 924                         // venus_ns:
 925                         iommu-ctx@5000 {
 926                                 compatible = "qcom,msm-iommu-v1-sec";
 927                                 reg = <0x5000 0x1000>;
 928                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 929                         };
 930                 };
 931
 932                 gpu_iommu: iommu@1f08000 {
 933                         #address-cells = <1>;
 934                         #size-cells = <1>;
 935                         #iommu-cells = <1>;
 936                         compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
 937                         ranges = <0 0x1f08000 0x10000>;
 938                         clocks = <&gcc GCC_SMMU_CFG_CLK>,
 939                                  <&gcc GCC_GFX_TCU_CLK>;
 940                         clock-names = "iface", "bus";
 941                         qcom,iommu-secure-id = <18>;
 942
 943                         // gfx3d_user:
 944                         iommu-ctx@1000 {
 945                                 compatible = "qcom,msm-iommu-v1-ns";
 946                                 reg = <0x1000 0x1000>;
 947                                 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
 948                         };
 949
 950                         // gfx3d_priv:
 951                         iommu-ctx@2000 {
 952                                 compatible = "qcom,msm-iommu-v1-ns";
 953                                 reg = <0x2000 0x1000>;
 954                                 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
 955                         };
 956                 };
 957
 958                 gpu@1c00000 {
 959                         compatible = "qcom,adreno-306.0", "qcom,adreno";
 960                         reg = <0x01c00000 0x20000>;
 961                         reg-names = "kgsl_3d0_reg_memory";
 962                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 963                         interrupt-names = "kgsl_3d0_irq";
 964                         clock-names =
 965                             "core",
 966                             "iface",
 967                             "mem",
 968                             "mem_iface",
 969                             "alt_mem_iface",
 970                             "gfx3d";
 971                         clocks =
 972                             <&gcc GCC_OXILI_GFX3D_CLK>,
 973                             <&gcc GCC_OXILI_AHB_CLK>,
 974                             <&gcc GCC_OXILI_GMEM_CLK>,
 975                             <&gcc GCC_BIMC_GFX_CLK>,
 976                             <&gcc GCC_BIMC_GPU_CLK>,
 977                             <&gcc GFX3D_CLK_SRC>;
 978                         power-domains = <&gcc OXILI_GDSC>;
 979                         operating-points-v2 = <&gpu_opp_table>;
 980                         iommus = <&gpu_iommu 1>, <&gpu_iommu 2>;
 981
 982                         gpu_opp_table: opp-table {
 983                                 compatible = "operating-points-v2";
 984
 985                                 opp-400000000 {
 986                                         opp-hz = /bits/ 64 <400000000>;
 987                                 };
 988                                 opp-19200000 {
 989                                         opp-hz = /bits/ 64 <19200000>;
 990                                 };
 991                         };
 992                 };
 993
 994                 mdss: mdss@1a00000 {
 995                         compatible = "qcom,mdss";
 996                         reg = <0x1a00000 0x1000>,
 997                               <0x1ac8000 0x3000>;
 998                         reg-names = "mdss_phys", "vbif_phys";
 999
1000                         power-domains = <&gcc MDSS_GDSC>;
1001
1002                         clocks = <&gcc GCC_MDSS_AHB_CLK>,
1003                                  <&gcc GCC_MDSS_AXI_CLK>,
1004                                  <&gcc GCC_MDSS_VSYNC_CLK>;
1005                         clock-names = "iface",
1006                                       "bus",
1007                                       "vsync";
1008
1009                         interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;
1010
1011                         interrupt-controller;
1012                         #interrupt-cells = <1>;
1013
1014                         #address-cells = <1>;
1015                         #size-cells = <1>;
1016                         ranges;
1017
1018                         mdp: mdp@1a01000 {
1019                                 compatible = "qcom,mdp5";
1020                                 reg = <0x1a01000 0x89000>;
1021                                 reg-names = "mdp_phys";
1022
1023                                 interrupt-parent = <&mdss>;
1024                                 interrupts = <0 0>;
1025
1026                                 clocks = <&gcc GCC_MDSS_AHB_CLK>,
1027                                          <&gcc GCC_MDSS_AXI_CLK>,
1028                                          <&gcc GCC_MDSS_MDP_CLK>,
1029                                          <&gcc GCC_MDSS_VSYNC_CLK>;
1030                                 clock-names = "iface",
1031                                               "bus",
1032                                               "core",
1033                                               "vsync";
1034
1035                                 iommus = <&apps_iommu 4>;
1036
1037                                 ports {
1038                                         #address-cells = <1>;
1039                                         #size-cells = <0>;
1040
1041                                         port@0 {
1042                                                 reg = <0>;
1043                                                 mdp5_intf1_out: endpoint {
1044                                                         remote-endpoint = <&dsi0_in>;
1045                                                 };
1046                                         };
1047                                 };
1048                         };
1049
1050                         dsi0: dsi@1a98000 {
1051                                 compatible = "qcom,mdss-dsi-ctrl";
1052                                 reg = <0x1a98000 0x25c>;
1053                                 reg-names = "dsi_ctrl";
1054
1055                                 interrupt-parent = <&mdss>;
1056                                 interrupts = <4 0>;
1057
1058                                 assigned-clocks = <&gcc BYTE0_CLK_SRC>,
1059                                                   <&gcc PCLK0_CLK_SRC>;
1060                                 assigned-clock-parents = <&dsi_phy0 0>,
1061                                                          <&dsi_phy0 1>;
1062
1063                                 clocks = <&gcc GCC_MDSS_MDP_CLK>,
1064                                          <&gcc GCC_MDSS_AHB_CLK>,
1065                                          <&gcc GCC_MDSS_AXI_CLK>,
1066                                          <&gcc GCC_MDSS_BYTE0_CLK>,
1067                                          <&gcc GCC_MDSS_PCLK0_CLK>,
1068                                          <&gcc GCC_MDSS_ESC0_CLK>;
1069                                 clock-names = "mdp_core",
1070                                               "iface",
1071                                               "bus",
1072                                               "byte",
1073                                               "pixel",
1074                                               "core";
1075                                 phys = <&dsi_phy0>;
1076                                 phy-names = "dsi-phy";
1077
1078                                 ports {
1079                                         #address-cells = <1>;
1080                                         #size-cells = <0>;
1081
1082                                         port@0 {
1083                                                 reg = <0>;
1084                                                 dsi0_in: endpoint {
1085                                                         remote-endpoint = <&mdp5_intf1_out>;
1086                                                 };
1087                                         };
1088
1089                                         port@1 {
1090                                                 reg = <1>;
1091                                                 dsi0_out: endpoint {
1092                                                 };
1093                                         };
1094                                 };
1095                         };
1096
1097                         dsi_phy0: dsi-phy@1a98300 {
1098                                 compatible = "qcom,dsi-phy-28nm-lp";
1099                                 reg = <0x1a98300 0xd4>,
1100                                       <0x1a98500 0x280>,
1101                                       <0x1a98780 0x30>;
1102                                 reg-names = "dsi_pll",
1103                                             "dsi_phy",
1104                                             "dsi_phy_regulator";
1105
1106                                 #clock-cells = <1>;
1107                                 #phy-cells = <0>;
1108
1109                                 clocks = <&gcc GCC_MDSS_AHB_CLK>,
1110                                          <&xo_board>;
1111                                 clock-names = "iface", "ref";
1112                         };
1113                 };
1114
1115
1116                 hexagon@4080000 {
1117                         compatible = "qcom,q6v5-pil";
1118                         reg = <0x04080000 0x100>,
1119                               <0x04020000 0x040>;
1120
1121                         reg-names = "qdsp6", "rmb";
1122
1123                         interrupts-extended = <&intc 0 24 1>,
1124                                               <&hexagon_smp2p_in 0 0>,
1125                                               <&hexagon_smp2p_in 1 0>,
1126                                               <&hexagon_smp2p_in 2 0>,
1127                                               <&hexagon_smp2p_in 3 0>;
1128                         interrupt-names = "wdog", "fatal", "ready",
1129                                           "handover", "stop-ack";
1130
1131                         clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1132                                  <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
1133                                  <&gcc GCC_BOOT_ROM_AHB_CLK>,
1134                                  <&xo_board>;
1135                         clock-names = "iface", "bus", "mem", "xo";
1136
1137                         qcom,smem-states = <&hexagon_smp2p_out 0>;
1138                         qcom,smem-state-names = "stop";
1139
1140                         resets = <&scm 0>;
1141                         reset-names = "mss_restart";
1142
1143                         cx-supply = <&pm8916_s1>;
1144                         mx-supply = <&pm8916_l3>;
1145                         pll-supply = <&pm8916_l7>;
1146
1147                         qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
1148
1149                         status = "disabled";
1150
1151                         mba {
1152                                 memory-region = <&mba_mem>;
1153                         };
1154
1155                         mpss {
1156                                 memory-region = <&mpss_mem>;
1157                         };
1158
1159                         smd-edge {
1160                                 interrupts = <0 25 IRQ_TYPE_EDGE_RISING>;
1161
1162                                 qcom,smd-edge = <0>;
1163                                 qcom,ipc = <&apcs 8 12>;
1164                                 qcom,remote-pid = <1>;
1165
1166                                 label = "hexagon";
1167
1168                                 fastrpc {
1169                                         compatible = "qcom,fastrpc";
1170                                         qcom,smd-channels = "fastrpcsmd-apps-dsp";
1171                                         label = "adsp";
1172
1173                                         #address-cells = <1>;
1174                                         #size-cells = <0>;
1175
1176                                         cb@1{
1177                                                 compatible = "qcom,fastrpc-compute-cb";
1178                                                 reg = <1>;
1179                                         };
1180                                 };
1181                         };
1182                 };
1183
1184                 pronto: wcnss@a21b000 {
1185                         compatible = "qcom,pronto-v2-pil", "qcom,pronto";
1186                         reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>;
1187                         reg-names = "ccu", "dxe", "pmu";
1188
1189                         memory-region = <&wcnss_mem>;
1190
1191                         interrupts-extended = <&intc 0 149 IRQ_TYPE_EDGE_RISING>,
1192                                               <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1193                                               <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1194                                               <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1195                                               <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1196                         interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
1197
1198                         vddmx-supply = <&pm8916_l3>;
1199                         vddpx-supply = <&pm8916_l7>;
1200
1201                         qcom,state = <&wcnss_smp2p_out 0>;
1202                         qcom,state-names = "stop";
1203
1204                         pinctrl-names = "default";
1205                         pinctrl-0 = <&wcnss_pin_a>;
1206
1207                         status = "disabled";
1208
1209                         iris {
1210                                 compatible = "qcom,wcn3620";
1211
1212                                 clocks = <&rpmcc RPM_SMD_RF_CLK2>;
1213                                 clock-names = "xo";
1214
1215                                 vddxo-supply = <&pm8916_l7>;
1216                                 vddrfa-supply = <&pm8916_s3>;
1217                                 vddpa-supply = <&pm8916_l9>;
1218                                 vdddig-supply = <&pm8916_l5>;
1219                         };
1220
1221                         smd-edge {
1222                                 interrupts = <0 142 1>;
1223
1224                                 qcom,ipc = <&apcs 8 17>;
1225                                 qcom,smd-edge = <6>;
1226                                 qcom,remote-pid = <4>;
1227
1228                                 label = "pronto";
1229
1230                                 wcnss {
1231                                         compatible = "qcom,wcnss";
1232                                         qcom,smd-channels = "WCNSS_CTRL";
1233
1234                                         qcom,mmio = <&pronto>;
1235
1236                                         bt {
1237                                                 compatible = "qcom,wcnss-bt";
1238                                         };
1239
1240                                         wifi {
1241                                                 compatible = "qcom,wcnss-wlan";
1242
1243                                                 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>,
1244                                                              <0 146 IRQ_TYPE_LEVEL_HIGH>;
1245                                                 interrupt-names = "tx", "rx";
1246
1247                                                 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
1248                                                 qcom,smem-state-names = "tx-enable", "tx-rings-empty";
1249                                         };
1250                                 };
1251                         };
1252                 };
1253
1254                 tpiu@820000 {
1255                         compatible = "arm,coresight-tpiu", "arm,primecell";
1256                         reg = <0x820000 0x1000>;
1257
1258                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1259                         clock-names = "apb_pclk", "atclk";
1260
1261                         status = "disabled";
1262
1263                         in-ports {
1264                                 port {
1265                                         tpiu_in: endpoint {
1266                                                 remote-endpoint = <&replicator_out1>;
1267                                         };
1268                                 };
1269                         };
1270                 };
1271
1272                 funnel@821000 {
1273                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1274                         reg = <0x821000 0x1000>;
1275
1276                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1277                         clock-names = "apb_pclk", "atclk";
1278
1279                         status = "disabled";
1280
1281                         in-ports {
1282                                 #address-cells = <1>;
1283                                 #size-cells = <0>;
1284
1285                                 /*
1286                                  * Not described input ports:
1287                                  * 0 - connected to Resource and Power Manger CPU ETM
1288                                  * 1 - not-connected
1289                                  * 2 - connected to Modem CPU ETM
1290                                  * 3 - not-connected
1291                                  * 5 - not-connected
1292                                  * 6 - connected trought funnel to Wireless CPU ETM
1293                                  * 7 - connected to STM component
1294                                  */
1295
1296                                 port@4 {
1297                                         reg = <4>;
1298                                         funnel0_in4: endpoint {
1299                                                 remote-endpoint = <&funnel1_out>;
1300                                         };
1301                                 };
1302                         };
1303
1304                         out-ports {
1305                                 port {
1306                                         funnel0_out: endpoint {
1307                                                 remote-endpoint = <&etf_in>;
1308                                         };
1309                                 };
1310                         };
1311                 };
1312
1313                 replicator@824000 {
1314                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
1315                         reg = <0x824000 0x1000>;
1316
1317                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1318                         clock-names = "apb_pclk", "atclk";
1319
1320                         status = "disabled";
1321
1322                         out-ports {
1323                                 #address-cells = <1>;
1324                                 #size-cells = <0>;
1325
1326                                 port@0 {
1327                                         reg = <0>;
1328                                         replicator_out0: endpoint {
1329                                                 remote-endpoint = <&etr_in>;
1330                                         };
1331                                 };
1332                                 port@1 {
1333                                         reg = <1>;
1334                                         replicator_out1: endpoint {
1335                                                 remote-endpoint = <&tpiu_in>;
1336                                         };
1337                                 };
1338                         };
1339
1340                         in-ports {
1341                                 port {
1342                                         replicator_in: endpoint {
1343                                                 remote-endpoint = <&etf_out>;
1344                                         };
1345                                 };
1346                         };
1347                 };
1348
1349                 etf@825000 {
1350                         compatible = "arm,coresight-tmc", "arm,primecell";
1351                         reg = <0x825000 0x1000>;
1352
1353                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1354                         clock-names = "apb_pclk", "atclk";
1355
1356                         status = "disabled";
1357
1358                         in-ports {
1359                                 port {
1360                                         etf_in: endpoint {
1361                                                 remote-endpoint = <&funnel0_out>;
1362                                         };
1363                                 };
1364                         };
1365
1366                         out-ports {
1367                                 port {
1368                                         etf_out: endpoint {
1369                                                 remote-endpoint = <&replicator_in>;
1370                                         };
1371                                 };
1372                         };
1373                 };
1374
1375                 etr@826000 {
1376                         compatible = "arm,coresight-tmc", "arm,primecell";
1377                         reg = <0x826000 0x1000>;
1378
1379                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1380                         clock-names = "apb_pclk", "atclk";
1381
1382                         status = "disabled";
1383
1384                         in-ports {
1385                                 port {
1386                                         etr_in: endpoint {
1387                                                 remote-endpoint = <&replicator_out0>;
1388                                         };
1389                                 };
1390                         };
1391                 };
1392
1393                 funnel@841000 { /* APSS funnel only 4 inputs are used */
1394                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1395                         reg = <0x841000 0x1000>;
1396
1397                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1398                         clock-names = "apb_pclk", "atclk";
1399
1400                         status = "disabled";
1401
1402                         in-ports {
1403                                 #address-cells = <1>;
1404                                 #size-cells = <0>;
1405
1406                                 port@0 {
1407                                         reg = <0>;
1408                                         funnel1_in0: endpoint {
1409                                                 remote-endpoint = <&etm0_out>;
1410                                         };
1411                                 };
1412                                 port@1 {
1413                                         reg = <1>;
1414                                         funnel1_in1: endpoint {
1415                                                 remote-endpoint = <&etm1_out>;
1416                                         };
1417                                 };
1418                                 port@2 {
1419                                         reg = <2>;
1420                                         funnel1_in2: endpoint {
1421                                                 remote-endpoint = <&etm2_out>;
1422                                         };
1423                                 };
1424                                 port@3 {
1425                                         reg = <3>;
1426                                         funnel1_in3: endpoint {
1427                                                 remote-endpoint = <&etm3_out>;
1428                                         };
1429                                 };
1430                         };
1431
1432                         out-ports {
1433                                 port {
1434                                         funnel1_out: endpoint {
1435                                                 remote-endpoint = <&funnel0_in4>;
1436                                         };
1437                                 };
1438                         };
1439                 };
1440
1441                 debug@850000 {
1442                         compatible = "arm,coresight-cpu-debug","arm,primecell";
1443                         reg = <0x850000 0x1000>;
1444                         clocks = <&rpmcc RPM_QDSS_CLK>;
1445                         clock-names = "apb_pclk";
1446                         cpu = <&CPU0>;
1447                         status = "disabled";
1448                 };
1449
1450                 debug@852000 {
1451                         compatible = "arm,coresight-cpu-debug","arm,primecell";
1452                         reg = <0x852000 0x1000>;
1453                         clocks = <&rpmcc RPM_QDSS_CLK>;
1454                         clock-names = "apb_pclk";
1455                         cpu = <&CPU1>;
1456                         status = "disabled";
1457                 };
1458
1459                 debug@854000 {
1460                         compatible = "arm,coresight-cpu-debug","arm,primecell";
1461                         reg = <0x854000 0x1000>;
1462                         clocks = <&rpmcc RPM_QDSS_CLK>;
1463                         clock-names = "apb_pclk";
1464                         cpu = <&CPU2>;
1465                         status = "disabled";
1466                 };
1467
1468                 debug@856000 {
1469                         compatible = "arm,coresight-cpu-debug","arm,primecell";
1470                         reg = <0x856000 0x1000>;
1471                         clocks = <&rpmcc RPM_QDSS_CLK>;
1472                         clock-names = "apb_pclk";
1473                         cpu = <&CPU3>;
1474                         status = "disabled";
1475                 };
1476
1477                 etm0: etm@85c000 {
1478                         compatible = "arm,coresight-etm4x", "arm,primecell";
1479                         reg = <0x85c000 0x1000>;
1480
1481                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1482                         clock-names = "apb_pclk", "atclk";
1483                         arm,coresight-loses-context-with-cpu;
1484
1485                         cpu = <&CPU0>;
1486
1487                         status = "disabled";
1488
1489                         out-ports {
1490                                 port {
1491                                         etm0_out: endpoint {
1492                                                 remote-endpoint = <&funnel1_in0>;
1493                                         };
1494                                 };
1495                         };
1496                 };
1497
1498                 etm1: etm@85d000 {
1499                         compatible = "arm,coresight-etm4x", "arm,primecell";
1500                         reg = <0x85d000 0x1000>;
1501
1502                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1503                         clock-names = "apb_pclk", "atclk";
1504                         arm,coresight-loses-context-with-cpu;
1505
1506                         cpu = <&CPU1>;
1507
1508                         status = "disabled";
1509
1510                         out-ports {
1511                                 port {
1512                                         etm1_out: endpoint {
1513                                                 remote-endpoint = <&funnel1_in1>;
1514                                         };
1515                                 };
1516                         };
1517                 };
1518
1519                 etm2: etm@85e000 {
1520                         compatible = "arm,coresight-etm4x", "arm,primecell";
1521                         reg = <0x85e000 0x1000>;
1522
1523                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1524                         clock-names = "apb_pclk", "atclk";
1525                         arm,coresight-loses-context-with-cpu;
1526
1527                         cpu = <&CPU2>;
1528
1529                         status = "disabled";
1530
1531                         out-ports {
1532                                 port {
1533                                         etm2_out: endpoint {
1534                                                 remote-endpoint = <&funnel1_in2>;
1535                                         };
1536                                 };
1537                         };
1538                 };
1539
1540                 etm3: etm@85f000 {
1541                         compatible = "arm,coresight-etm4x", "arm,primecell";
1542                         reg = <0x85f000 0x1000>;
1543
1544                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1545                         clock-names = "apb_pclk", "atclk";
1546                         arm,coresight-loses-context-with-cpu;
1547
1548                         cpu = <&CPU3>;
1549
1550                         status = "disabled";
1551
1552                         out-ports {
1553                                 port {
1554                                         etm3_out: endpoint {
1555                                                 remote-endpoint = <&funnel1_in3>;
1556                                         };
1557                                 };
1558                         };
1559                 };
1560
1561                 /* System CTIs */
1562                 /* CTI 0 - TMC connections */
1563                 cti@810000 {
1564                         compatible = "arm,coresight-cti", "arm,primecell";
1565                         reg = <0x810000 0x1000>;
1566
1567                         clocks = <&rpmcc RPM_QDSS_CLK>;
1568                         clock-names = "apb_pclk";
1569
1570                         status = "disabled";
1571                 };
1572
1573                 /* CTI 1 - TPIU connections */
1574                 cti@811000 {
1575                         compatible = "arm,coresight-cti", "arm,primecell";
1576                         reg = <0x811000 0x1000>;
1577
1578                         clocks = <&rpmcc RPM_QDSS_CLK>;
1579                         clock-names = "apb_pclk";
1580
1581                         status = "disabled";
1582                 };
1583
1584                 /* CTIs 2-11 - no information - not instantiated */
1585
1586                 /* Core CTIs; CTIs 12-15 */
1587                 /* CTI - CPU-0 */
1588                 cti@858000 {
1589                         compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
1590                                      "arm,primecell";
1591                         reg = <0x858000 0x1000>;
1592
1593                         clocks = <&rpmcc RPM_QDSS_CLK>;
1594                         clock-names = "apb_pclk";
1595
1596                         cpu = <&CPU0>;
1597                         arm,cs-dev-assoc = <&etm0>;
1598
1599                         status = "disabled";
1600                 };
1601
1602                 /* CTI - CPU-1 */
1603                 cti@859000 {
1604                         compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
1605                                      "arm,primecell";
1606                         reg = <0x859000 0x1000>;
1607
1608                         clocks = <&rpmcc RPM_QDSS_CLK>;
1609                         clock-names = "apb_pclk";
1610
1611                         cpu = <&CPU1>;
1612                         arm,cs-dev-assoc = <&etm1>;
1613
1614                         status = "disabled";
1615                 };
1616
1617                 /* CTI - CPU-2 */
1618                 cti@85a000 {
1619                         compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
1620                                      "arm,primecell";
1621                         reg = <0x85a000 0x1000>;
1622
1623                         clocks = <&rpmcc RPM_QDSS_CLK>;
1624                         clock-names = "apb_pclk";
1625
1626                         cpu = <&CPU2>;
1627                         arm,cs-dev-assoc = <&etm2>;
1628
1629                         status = "disabled";
1630                 };
1631
1632                 /* CTI - CPU-3 */
1633                 cti@85b000 {
1634                         compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
1635                                      "arm,primecell";
1636                         reg = <0x85b000 0x1000>;
1637
1638                         clocks = <&rpmcc RPM_QDSS_CLK>;
1639                         clock-names = "apb_pclk";
1640
1641                         cpu = <&CPU3>;
1642                         arm,cs-dev-assoc = <&etm3>;
1643
1644                         status = "disabled";
1645                 };
1646
1647
1648                 venus: video-codec@1d00000 {
1649                         compatible = "qcom,msm8916-venus";
1650                         reg = <0x01d00000 0xff000>;
1651                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1652                         power-domains = <&gcc VENUS_GDSC>;
1653                         clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>,
1654                                  <&gcc GCC_VENUS0_AHB_CLK>,
1655                                  <&gcc GCC_VENUS0_AXI_CLK>;
1656                         clock-names = "core", "iface", "bus";
1657                         iommus = <&apps_iommu 5>;
1658                         memory-region = <&venus_mem>;
1659                         status = "okay";
1660
1661                         video-decoder {
1662                                 compatible = "venus-decoder";
1663                         };
1664
1665                         video-encoder {
1666                                 compatible = "venus-encoder";
1667                         };
1668                 };
1669
1670                 camss: camss@1b00000 {
1671                         compatible = "qcom,msm8916-camss";
1672                         reg = <0x1b0ac00 0x200>,
1673                                 <0x1b00030 0x4>,
1674                                 <0x1b0b000 0x200>,
1675                                 <0x1b00038 0x4>,
1676                                 <0x1b08000 0x100>,
1677                                 <0x1b08400 0x100>,
1678                                 <0x1b0a000 0x500>,
1679                                 <0x1b00020 0x10>,
1680                                 <0x1b10000 0x1000>;
1681                         reg-names = "csiphy0",
1682                                 "csiphy0_clk_mux",
1683                                 "csiphy1",
1684                                 "csiphy1_clk_mux",
1685                                 "csid0",
1686                                 "csid1",
1687                                 "ispif",
1688                                 "csi_clk_mux",
1689                                 "vfe0";
1690                         interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
1691                                 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
1692                                 <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
1693                                 <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
1694                                 <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
1695                                 <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
1696                         interrupt-names = "csiphy0",
1697                                 "csiphy1",
1698                                 "csid0",
1699                                 "csid1",
1700                                 "ispif",
1701                                 "vfe0";
1702                         power-domains = <&gcc VFE_GDSC>;
1703                         clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
1704                                 <&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
1705                                 <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>,
1706                                 <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>,
1707                                 <&gcc GCC_CAMSS_CSI0_AHB_CLK>,
1708                                 <&gcc GCC_CAMSS_CSI0_CLK>,
1709                                 <&gcc GCC_CAMSS_CSI0PHY_CLK>,
1710                                 <&gcc GCC_CAMSS_CSI0PIX_CLK>,
1711                                 <&gcc GCC_CAMSS_CSI0RDI_CLK>,
1712                                 <&gcc GCC_CAMSS_CSI1_AHB_CLK>,
1713                                 <&gcc GCC_CAMSS_CSI1_CLK>,
1714                                 <&gcc GCC_CAMSS_CSI1PHY_CLK>,
1715                                 <&gcc GCC_CAMSS_CSI1PIX_CLK>,
1716                                 <&gcc GCC_CAMSS_CSI1RDI_CLK>,
1717                                 <&gcc GCC_CAMSS_AHB_CLK>,
1718                                 <&gcc GCC_CAMSS_VFE0_CLK>,
1719                                 <&gcc GCC_CAMSS_CSI_VFE0_CLK>,
1720                                 <&gcc GCC_CAMSS_VFE_AHB_CLK>,
1721                                 <&gcc GCC_CAMSS_VFE_AXI_CLK>;
1722                         clock-names = "top_ahb",
1723                                 "ispif_ahb",
1724                                 "csiphy0_timer",
1725                                 "csiphy1_timer",
1726                                 "csi0_ahb",
1727                                 "csi0",
1728                                 "csi0_phy",
1729                                 "csi0_pix",
1730                                 "csi0_rdi",
1731                                 "csi1_ahb",
1732                                 "csi1",
1733                                 "csi1_phy",
1734                                 "csi1_pix",
1735                                 "csi1_rdi",
1736                                 "ahb",
1737                                 "vfe0",
1738                                 "csi_vfe0",
1739                                 "vfe_ahb",
1740                                 "vfe_axi";
1741                         vdda-supply = <&pm8916_l2>;
1742                         iommus = <&apps_iommu 3>;
1743                         status = "disabled";
1744                         ports {
1745                                 #address-cells = <1>;
1746                                 #size-cells = <0>;
1747                         };
1748                 };
1749
1750                 cci: cci@1b0c000 {
1751                         compatible = "qcom,msm8916-cci";
1752                         #address-cells = <1>;
1753                         #size-cells = <0>;
1754                         reg = <0x1b0c000 0x1000>;
1755                         interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
1756                         clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
1757                                 <&gcc GCC_CAMSS_CCI_AHB_CLK>,
1758                                 <&gcc GCC_CAMSS_CCI_CLK>,
1759                                 <&gcc GCC_CAMSS_AHB_CLK>;
1760                         clock-names = "camss_top_ahb", "cci_ahb",
1761                                           "cci", "camss_ahb";
1762                         assigned-clocks = <&gcc GCC_CAMSS_CCI_AHB_CLK>,
1763                                           <&gcc GCC_CAMSS_CCI_CLK>;
1764                         assigned-clock-rates = <80000000>, <19200000>;
1765                         pinctrl-names = "default";
1766                         pinctrl-0 = <&cci0_default>;
1767                         status = "disabled";
1768
1769                         cci_i2c0: i2c-bus@0 {
1770                                 reg = <0>;
1771                                 clock-frequency = <400000>;
1772                                 #address-cells = <1>;
1773                                 #size-cells = <0>;
1774                         };
1775                 };
1776         };
1777
1778         smd {
1779                 compatible = "qcom,smd";
1780
1781                 rpm {
1782                         interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
1783                         qcom,ipc = <&apcs 8 0>;
1784                         qcom,smd-edge = <15>;
1785
1786                         rpm-requests {
1787                                 compatible = "qcom,rpm-msm8916";
1788                                 qcom,smd-channels = "rpm_requests";
1789
1790                                 rpmcc: qcom,rpmcc {
1791                                         compatible = "qcom,rpmcc-msm8916";
1792                                         #clock-cells = <1>;
1793                                 };
1794
1795                                 smd_rpm_regulators: pm8916-regulators {
1796                                         compatible = "qcom,rpm-pm8916-regulators";
1797
1798                                         pm8916_s1: s1 {};
1799                                         pm8916_s3: s3 {};
1800                                         pm8916_s4: s4 {};
1801
1802                                         pm8916_l1: l1 {};
1803                                         pm8916_l2: l2 {};
1804                                         pm8916_l3: l3 {};
1805                                         pm8916_l4: l4 {};
1806                                         pm8916_l5: l5 {};
1807                                         pm8916_l6: l6 {};
1808                                         pm8916_l7: l7 {};
1809                                         pm8916_l8: l8 {};
1810                                         pm8916_l9: l9 {};
1811                                         pm8916_l10: l10 {};
1812                                         pm8916_l11: l11 {};
1813                                         pm8916_l12: l12 {};
1814                                         pm8916_l13: l13 {};
1815                                         pm8916_l14: l14 {};
1816                                         pm8916_l15: l15 {};
1817                                         pm8916_l16: l16 {};
1818                                         pm8916_l17: l17 {};
1819                                         pm8916_l18: l18 {};
1820                                 };
1821                         };
1822                 };
1823         };
1824
1825         hexagon-smp2p {
1826                 compatible = "qcom,smp2p";
1827                 qcom,smem = <435>, <428>;
1828
1829                 interrupts = <0 27 IRQ_TYPE_EDGE_RISING>;
1830
1831                 qcom,ipc = <&apcs 8 14>;
1832
1833                 qcom,local-pid = <0>;
1834                 qcom,remote-pid = <1>;
1835
1836                 hexagon_smp2p_out: master-kernel {
1837                         qcom,entry-name = "master-kernel";
1838
1839                         #qcom,smem-state-cells = <1>;
1840                 };
1841
1842                 hexagon_smp2p_in: slave-kernel {
1843                         qcom,entry-name = "slave-kernel";
1844
1845                         interrupt-controller;
1846                         #interrupt-cells = <2>;
1847                 };
1848         };
1849
1850         wcnss-smp2p {
1851                 compatible = "qcom,smp2p";
1852                 qcom,smem = <451>, <431>;
1853
1854                 interrupts = <0 143 IRQ_TYPE_EDGE_RISING>;
1855
1856                 qcom,ipc = <&apcs 8 18>;
1857
1858                 qcom,local-pid = <0>;
1859                 qcom,remote-pid = <4>;
1860
1861                 wcnss_smp2p_out: master-kernel {
1862                         qcom,entry-name = "master-kernel";
1863
1864                         #qcom,smem-state-cells = <1>;
1865                 };
1866
1867                 wcnss_smp2p_in: slave-kernel {
1868                         qcom,entry-name = "slave-kernel";
1869
1870                         interrupt-controller;
1871                         #interrupt-cells = <2>;
1872                 };
1873         };
1874
1875         smsm {
1876                 compatible = "qcom,smsm";
1877
1878                 #address-cells = <1>;
1879                 #size-cells = <0>;
1880
1881                 qcom,ipc-1 = <&apcs 8 13>;
1882                 qcom,ipc-3 = <&apcs 8 19>;
1883
1884                 apps_smsm: apps@0 {
1885                         reg = <0>;
1886
1887                         #qcom,smem-state-cells = <1>;
1888                 };
1889
1890                 hexagon_smsm: hexagon@1 {
1891                         reg = <1>;
1892                         interrupts = <0 26 IRQ_TYPE_EDGE_RISING>;
1893
1894                         interrupt-controller;
1895                         #interrupt-cells = <2>;
1896                 };
1897
1898                 wcnss_smsm: wcnss@6 {
1899                         reg = <6>;
1900                         interrupts = <0 144 IRQ_TYPE_EDGE_RISING>;
1901
1902                         interrupt-controller;
1903                         #interrupt-cells = <2>;
1904                 };
1905         };
1906 };
1907
1908 #include "msm8916-pins.dtsi"