sys/gnu/dts/arm64/qcom/msm8996.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
   3  */
   4
   5 #include <dt-bindings/interrupt-controller/arm-gic.h>
   6 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
   7 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
   8 #include <dt-bindings/clock/qcom,rpmcc.h>
   9 #include <dt-bindings/soc/qcom,apr.h>
  10
  11 / {
  12         interrupt-parent = <&intc>;
  13
  14         #address-cells = <2>;
  15         #size-cells = <2>;
  16
  17         chosen { };
  18
  19         clocks {
  20                 xo_board: xo_board {
  21                         compatible = "fixed-clock";
  22                         #clock-cells = <0>;
  23                         clock-frequency = <19200000>;
  24                         clock-output-names = "xo_board";
  25                 };
  26
  27                 sleep_clk: sleep_clk {
  28                         compatible = "fixed-clock";
  29                         #clock-cells = <0>;
  30                         clock-frequency = <32764>;
  31                         clock-output-names = "sleep_clk";
  32                 };
  33         };
  34
  35         cpus {
  36                 #address-cells = <2>;
  37                 #size-cells = <0>;
  38
  39                 CPU0: cpu@0 {
  40                         device_type = "cpu";
  41                         compatible = "qcom,kryo";
  42                         reg = <0x0 0x0>;
  43                         enable-method = "psci";
  44                         cpu-idle-states = <&CPU_SLEEP_0>;
  45                         capacity-dmips-mhz = <1024>;
  46                         next-level-cache = <&L2_0>;
  47                         L2_0: l2-cache {
  48                               compatible = "cache";
  49                               cache-level = <2>;
  50                         };
  51                 };
  52
  53                 CPU1: cpu@1 {
  54                         device_type = "cpu";
  55                         compatible = "qcom,kryo";
  56                         reg = <0x0 0x1>;
  57                         enable-method = "psci";
  58                         cpu-idle-states = <&CPU_SLEEP_0>;
  59                         capacity-dmips-mhz = <1024>;
  60                         next-level-cache = <&L2_0>;
  61                 };
  62
  63                 CPU2: cpu@100 {
  64                         device_type = "cpu";
  65                         compatible = "qcom,kryo";
  66                         reg = <0x0 0x100>;
  67                         enable-method = "psci";
  68                         cpu-idle-states = <&CPU_SLEEP_0>;
  69                         capacity-dmips-mhz = <1024>;
  70                         next-level-cache = <&L2_1>;
  71                         L2_1: l2-cache {
  72                               compatible = "cache";
  73                               cache-level = <2>;
  74                         };
  75                 };
  76
  77                 CPU3: cpu@101 {
  78                         device_type = "cpu";
  79                         compatible = "qcom,kryo";
  80                         reg = <0x0 0x101>;
  81                         enable-method = "psci";
  82                         cpu-idle-states = <&CPU_SLEEP_0>;
  83                         capacity-dmips-mhz = <1024>;
  84                         next-level-cache = <&L2_1>;
  85                 };
  86
  87                 cpu-map {
  88                         cluster0 {
  89                                 core0 {
  90                                         cpu = <&CPU0>;
  91                                 };
  92
  93                                 core1 {
  94                                         cpu = <&CPU1>;
  95                                 };
  96                         };
  97
  98                         cluster1 {
  99                                 core0 {
 100                                         cpu = <&CPU2>;
 101                                 };
 102
 103                                 core1 {
 104                                         cpu = <&CPU3>;
 105                                 };
 106                         };
 107                 };
 108
 109                 idle-states {
 110                         entry-method = "psci";
 111
 112                         CPU_SLEEP_0: cpu-sleep-0 {
 113                                 compatible = "arm,idle-state";
 114                                 idle-state-name = "standalone-power-collapse";
 115                                 arm,psci-suspend-param = <0x00000004>;
 116                                 entry-latency-us = <130>;
 117                                 exit-latency-us = <80>;
 118                                 min-residency-us = <300>;
 119                         };
 120                 };
 121         };
 122
 123         firmware {
 124                 scm {
 125                         compatible = "qcom,scm-msm8996";
 126                         qcom,dload-mode = <&tcsr 0x13000>;
 127                 };
 128         };
 129
 130         tcsr_mutex: hwlock {
 131                 compatible = "qcom,tcsr-mutex";
 132                 syscon = <&tcsr_mutex_regs 0 0x1000>;
 133                 #hwlock-cells = <1>;
 134         };
 135
 136         memory {
 137                 device_type = "memory";
 138                 /* We expect the bootloader to fill in the reg */
 139                 reg = <0 0 0 0>;
 140         };
 141
 142         psci {
 143                 compatible = "arm,psci-1.0";
 144                 method = "smc";
 145         };
 146
 147         reserved-memory {
 148                 #address-cells = <2>;
 149                 #size-cells = <2>;
 150                 ranges;
 151
 152                 mba_region: mba@91500000 {
 153                         reg = <0x0 0x91500000 0x0 0x200000>;
 154                         no-map;
 155                 };
 156
 157                 slpi_region: slpi@90b00000 {
 158                         reg = <0x0 0x90b00000 0x0 0xa00000>;
 159                         no-map;
 160                 };
 161
 162                 venus_region: venus@90400000 {
 163                         reg = <0x0 0x90400000 0x0 0x700000>;
 164                         no-map;
 165                 };
 166
 167                 adsp_region: adsp@8ea00000 {
 168                         reg = <0x0 0x8ea00000 0x0 0x1a00000>;
 169                         no-map;
 170                 };
 171
 172                 mpss_region: mpss@88800000 {
 173                         reg = <0x0 0x88800000 0x0 0x6200000>;
 174                         no-map;
 175                 };
 176
 177                 smem_mem: smem-mem@86000000 {
 178                         reg = <0x0 0x86000000 0x0 0x200000>;
 179                         no-map;
 180                 };
 181
 182                 memory@85800000 {
 183                         reg = <0x0 0x85800000 0x0 0x800000>;
 184                         no-map;
 185                 };
 186
 187                 memory@86200000 {
 188                         reg = <0x0 0x86200000 0x0 0x2600000>;
 189                         no-map;
 190                 };
 191
 192                 rmtfs@86700000 {
 193                         compatible = "qcom,rmtfs-mem";
 194
 195                         size = <0x0 0x200000>;
 196                         alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
 197                         no-map;
 198
 199                         qcom,client-id = <1>;
 200                         qcom,vmid = <15>;
 201                 };
 202
 203                 zap_shader_region: gpu@8f200000 {
 204                         compatible = "shared-dma-pool";
 205                         reg = <0x0 0x90b00000 0x0 0xa00000>;
 206                         no-map;
 207                 };
 208         };
 209
 210         rpm-glink {
 211                 compatible = "qcom,glink-rpm";
 212
 213                 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
 214
 215                 qcom,rpm-msg-ram = <&rpm_msg_ram>;
 216
 217                 mboxes = <&apcs_glb 0>;
 218
 219                 rpm_requests: rpm-requests {
 220                         compatible = "qcom,rpm-msm8996";
 221                         qcom,glink-channels = "rpm_requests";
 222
 223                         rpmcc: qcom,rpmcc {
 224                                 compatible = "qcom,rpmcc-msm8996";
 225                                 #clock-cells = <1>;
 226                         };
 227
 228                         rpmpd: power-controller {
 229                                 compatible = "qcom,msm8996-rpmpd";
 230                                 #power-domain-cells = <1>;
 231                                 operating-points-v2 = <&rpmpd_opp_table>;
 232
 233                                 rpmpd_opp_table: opp-table {
 234                                         compatible = "operating-points-v2";
 235
 236                                         rpmpd_opp1: opp1 {
 237                                                 opp-level = <1>;
 238                                         };
 239
 240                                         rpmpd_opp2: opp2 {
 241                                                 opp-level = <2>;
 242                                         };
 243
 244                                         rpmpd_opp3: opp3 {
 245                                                 opp-level = <3>;
 246                                         };
 247
 248                                         rpmpd_opp4: opp4 {
 249                                                 opp-level = <4>;
 250                                         };
 251
 252                                         rpmpd_opp5: opp5 {
 253                                                 opp-level = <5>;
 254                                         };
 255
 256                                         rpmpd_opp6: opp6 {
 257                                                 opp-level = <6>;
 258                                         };
 259                                 };
 260                         };
 261                 };
 262         };
 263
 264         smem {
 265                 compatible = "qcom,smem";
 266                 memory-region = <&smem_mem>;
 267                 hwlocks = <&tcsr_mutex 3>;
 268         };
 269
 270         smp2p-adsp {
 271                 compatible = "qcom,smp2p";
 272                 qcom,smem = <443>, <429>;
 273
 274                 interrupts = <0 158 IRQ_TYPE_EDGE_RISING>;
 275
 276                 mboxes = <&apcs_glb 10>;
 277
 278                 qcom,local-pid = <0>;
 279                 qcom,remote-pid = <2>;
 280
 281                 smp2p_adsp_out: master-kernel {
 282                         qcom,entry-name = "master-kernel";
 283                         #qcom,smem-state-cells = <1>;
 284                 };
 285
 286                 smp2p_adsp_in: slave-kernel {
 287                         qcom,entry-name = "slave-kernel";
 288
 289                         interrupt-controller;
 290                         #interrupt-cells = <2>;
 291                 };
 292         };
 293
 294         smp2p-modem {
 295                 compatible = "qcom,smp2p";
 296                 qcom,smem = <435>, <428>;
 297
 298                 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
 299
 300                 mboxes = <&apcs_glb 14>;
 301
 302                 qcom,local-pid = <0>;
 303                 qcom,remote-pid = <1>;
 304
 305                 modem_smp2p_out: master-kernel {
 306                         qcom,entry-name = "master-kernel";
 307                         #qcom,smem-state-cells = <1>;
 308                 };
 309
 310                 modem_smp2p_in: slave-kernel {
 311                         qcom,entry-name = "slave-kernel";
 312
 313                         interrupt-controller;
 314                         #interrupt-cells = <2>;
 315                 };
 316         };
 317
 318         smp2p-slpi {
 319                 compatible = "qcom,smp2p";
 320                 qcom,smem = <481>, <430>;
 321
 322                 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
 323
 324                 mboxes = <&apcs_glb 26>;
 325
 326                 qcom,local-pid = <0>;
 327                 qcom,remote-pid = <3>;
 328
 329                 smp2p_slpi_in: slave-kernel {
 330                         qcom,entry-name = "slave-kernel";
 331                         interrupt-controller;
 332                         #interrupt-cells = <2>;
 333                 };
 334
 335                 smp2p_slpi_out: master-kernel {
 336                         qcom,entry-name = "master-kernel";
 337                         #qcom,smem-state-cells = <1>;
 338                 };
 339         };
 340
 341         soc: soc {
 342                 #address-cells = <1>;
 343                 #size-cells = <1>;
 344                 ranges = <0 0 0 0xffffffff>;
 345                 compatible = "simple-bus";
 346
 347                 pcie_phy: phy@34000 {
 348                         compatible = "qcom,msm8996-qmp-pcie-phy";
 349                         reg = <0x00034000 0x488>;
 350                         #clock-cells = <1>;
 351                         #address-cells = <1>;
 352                         #size-cells = <1>;
 353                         ranges;
 354
 355                         clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
 356                                 <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
 357                                 <&gcc GCC_PCIE_CLKREF_CLK>;
 358                         clock-names = "aux", "cfg_ahb", "ref";
 359
 360                         resets = <&gcc GCC_PCIE_PHY_BCR>,
 361                                 <&gcc GCC_PCIE_PHY_COM_BCR>,
 362                                 <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
 363                         reset-names = "phy", "common", "cfg";
 364                         status = "disabled";
 365
 366                         pciephy_0: lane@35000 {
 367                                 reg = <0x00035000 0x130>,
 368                                       <0x00035200 0x200>,
 369                                       <0x00035400 0x1dc>;
 370                                 #phy-cells = <0>;
 371
 372                                 clock-output-names = "pcie_0_pipe_clk_src";
 373                                 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
 374                                 clock-names = "pipe0";
 375                                 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
 376                                 reset-names = "lane0";
 377                         };
 378
 379                         pciephy_1: lane@36000 {
 380                                 reg = <0x00036000 0x130>,
 381                                       <0x00036200 0x200>,
 382                                       <0x00036400 0x1dc>;
 383                                 #phy-cells = <0>;
 384
 385                                 clock-output-names = "pcie_1_pipe_clk_src";
 386                                 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
 387                                 clock-names = "pipe1";
 388                                 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
 389                                 reset-names = "lane1";
 390                         };
 391
 392                         pciephy_2: lane@37000 {
 393                                 reg = <0x00037000 0x130>,
 394                                       <0x00037200 0x200>,
 395                                       <0x00037400 0x1dc>;
 396                                 #phy-cells = <0>;
 397
 398                                 clock-output-names = "pcie_2_pipe_clk_src";
 399                                 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
 400                                 clock-names = "pipe2";
 401                                 resets = <&gcc GCC_PCIE_2_PHY_BCR>;
 402                                 reset-names = "lane2";
 403                         };
 404                 };
 405
 406                 rpm_msg_ram: memory@68000 {
 407                         compatible = "qcom,rpm-msg-ram";
 408                         reg = <0x00068000 0x6000>;
 409                 };
 410
 411                 qfprom@74000 {
 412                         compatible = "qcom,qfprom";
 413                         reg = <0x00074000 0x8ff>;
 414                         #address-cells = <1>;
 415                         #size-cells = <1>;
 416
 417                         qusb2p_hstx_trim: hstx_trim@24e {
 418                                 reg = <0x24e 0x2>;
 419                                 bits = <5 4>;
 420                         };
 421
 422                         qusb2s_hstx_trim: hstx_trim@24f {
 423                                 reg = <0x24f 0x1>;
 424                                 bits = <1 4>;
 425                         };
 426
 427                         gpu_speed_bin: gpu_speed_bin@133 {
 428                                 reg = <0x133 0x1>;
 429                                 bits = <5 3>;
 430                         };
 431                 };
 432
 433                 rng: rng@83000 {
 434                         compatible = "qcom,prng-ee";
 435                         reg = <0x00083000 0x1000>;
 436                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 437                         clock-names = "core";
 438                 };
 439
 440                 gcc: clock-controller@300000 {
 441                         compatible = "qcom,gcc-msm8996";
 442                         #clock-cells = <1>;
 443                         #reset-cells = <1>;
 444                         #power-domain-cells = <1>;
 445                         reg = <0x00300000 0x90000>;
 446                 };
 447
 448                 tsens0: thermal-sensor@4a9000 {
 449                         compatible = "qcom,msm8996-tsens";
 450                         reg = <0x004a9000 0x1000>, /* TM */
 451                               <0x004a8000 0x1000>; /* SROT */
 452                         #qcom,sensors = <13>;
 453                         interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
 454                                      <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
 455                         interrupt-names = "uplow", "critical";
 456                         #thermal-sensor-cells = <1>;
 457                 };
 458
 459                 tsens1: thermal-sensor@4ad000 {
 460                         compatible = "qcom,msm8996-tsens";
 461                         reg = <0x004ad000 0x1000>, /* TM */
 462                               <0x004ac000 0x1000>; /* SROT */
 463                         #qcom,sensors = <8>;
 464                         interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
 465                                      <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
 466                         interrupt-names = "uplow", "critical";
 467                         #thermal-sensor-cells = <1>;
 468                 };
 469
 470                 tcsr_mutex_regs: syscon@740000 {
 471                         compatible = "syscon";
 472                         reg = <0x00740000 0x20000>;
 473                 };
 474
 475                 tcsr: syscon@7a0000 {
 476                         compatible = "qcom,tcsr-msm8996", "syscon";
 477                         reg = <0x007a0000 0x18000>;
 478                 };
 479
 480                 mmcc: clock-controller@8c0000 {
 481                         compatible = "qcom,mmcc-msm8996";
 482                         #clock-cells = <1>;
 483                         #reset-cells = <1>;
 484                         #power-domain-cells = <1>;
 485                         reg = <0x008c0000 0x40000>;
 486                         assigned-clocks = <&mmcc MMPLL9_PLL>,
 487                                           <&mmcc MMPLL1_PLL>,
 488                                           <&mmcc MMPLL3_PLL>,
 489                                           <&mmcc MMPLL4_PLL>,
 490                                           <&mmcc MMPLL5_PLL>;
 491                         assigned-clock-rates = <624000000>,
 492                                                <810000000>,
 493                                                <980000000>,
 494                                                <960000000>,
 495                                                <825000000>;
 496                 };
 497
 498                 mdss: mdss@900000 {
 499                         compatible = "qcom,mdss";
 500
 501                         reg = <0x00900000 0x1000>,
 502                               <0x009b0000 0x1040>,
 503                               <0x009b8000 0x1040>;
 504                         reg-names = "mdss_phys",
 505                                     "vbif_phys",
 506                                     "vbif_nrt_phys";
 507
 508                         power-domains = <&mmcc MDSS_GDSC>;
 509                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 510
 511                         interrupt-controller;
 512                         #interrupt-cells = <1>;
 513
 514                         clocks = <&mmcc MDSS_AHB_CLK>;
 515                         clock-names = "iface";
 516
 517                         #address-cells = <1>;
 518                         #size-cells = <1>;
 519                         ranges;
 520
 521                         mdp: mdp@901000 {
 522                                 compatible = "qcom,mdp5";
 523                                 reg = <0x00901000 0x90000>;
 524                                 reg-names = "mdp_phys";
 525
 526                                 interrupt-parent = <&mdss>;
 527                                 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
 528
 529                                 clocks = <&mmcc MDSS_AHB_CLK>,
 530                                          <&mmcc MDSS_AXI_CLK>,
 531                                          <&mmcc MDSS_MDP_CLK>,
 532                                          <&mmcc SMMU_MDP_AXI_CLK>,
 533                                          <&mmcc MDSS_VSYNC_CLK>;
 534                                 clock-names = "iface",
 535                                               "bus",
 536                                               "core",
 537                                               "iommu",
 538                                               "vsync";
 539
 540                                 iommus = <&mdp_smmu 0>;
 541
 542                                 ports {
 543                                         #address-cells = <1>;
 544                                         #size-cells = <0>;
 545
 546                                         port@0 {
 547                                                 reg = <0>;
 548                                                 mdp5_intf3_out: endpoint {
 549                                                         remote-endpoint = <&hdmi_in>;
 550                                                 };
 551                                         };
 552                                 };
 553                         };
 554
 555                         hdmi: hdmi-tx@9a0000 {
 556                                 compatible = "qcom,hdmi-tx-8996";
 557                                 reg =   <0x009a0000 0x50c>,
 558                                         <0x00070000 0x6158>,
 559                                         <0x009e0000 0xfff>;
 560                                 reg-names = "core_physical",
 561                                             "qfprom_physical",
 562                                             "hdcp_physical";
 563
 564                                 interrupt-parent = <&mdss>;
 565                                 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
 566
 567                                 clocks = <&mmcc MDSS_MDP_CLK>,
 568                                          <&mmcc MDSS_AHB_CLK>,
 569                                          <&mmcc MDSS_HDMI_CLK>,
 570                                          <&mmcc MDSS_HDMI_AHB_CLK>,
 571                                          <&mmcc MDSS_EXTPCLK_CLK>;
 572                                 clock-names =
 573                                         "mdp_core",
 574                                         "iface",
 575                                         "core",
 576                                         "alt_iface",
 577                                         "extp";
 578
 579                                 phys = <&hdmi_phy>;
 580                                 phy-names = "hdmi_phy";
 581                                 #sound-dai-cells = <1>;
 582
 583                                 ports {
 584                                         #address-cells = <1>;
 585                                         #size-cells = <0>;
 586
 587                                         port@0 {
 588                                                 reg = <0>;
 589                                                 hdmi_in: endpoint {
 590                                                         remote-endpoint = <&mdp5_intf3_out>;
 591                                                 };
 592                                         };
 593                                 };
 594                         };
 595
 596                         hdmi_phy: hdmi-phy@9a0600 {
 597                                 #phy-cells = <0>;
 598                                 compatible = "qcom,hdmi-phy-8996";
 599                                 reg = <0x009a0600 0x1c4>,
 600                                       <0x009a0a00 0x124>,
 601                                       <0x009a0c00 0x124>,
 602                                       <0x009a0e00 0x124>,
 603                                       <0x009a1000 0x124>,
 604                                       <0x009a1200 0x0c8>;
 605                                 reg-names = "hdmi_pll",
 606                                             "hdmi_tx_l0",
 607                                             "hdmi_tx_l1",
 608                                             "hdmi_tx_l2",
 609                                             "hdmi_tx_l3",
 610                                             "hdmi_phy";
 611
 612                                 clocks = <&mmcc MDSS_AHB_CLK>,
 613                                          <&gcc GCC_HDMI_CLKREF_CLK>;
 614                                 clock-names = "iface",
 615                                               "ref";
 616                         };
 617                 };
 618                 gpu@b00000 {
 619                         compatible = "qcom,adreno-530.2", "qcom,adreno";
 620                         #stream-id-cells = <16>;
 621
 622                         reg = <0x00b00000 0x3f000>;
 623                         reg-names = "kgsl_3d0_reg_memory";
 624
 625                         interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
 626
 627                         clocks = <&mmcc GPU_GX_GFX3D_CLK>,
 628                                 <&mmcc GPU_AHB_CLK>,
 629                                 <&mmcc GPU_GX_RBBMTIMER_CLK>,
 630                                 <&gcc GCC_BIMC_GFX_CLK>,
 631                                 <&gcc GCC_MMSS_BIMC_GFX_CLK>;
 632
 633                         clock-names = "core",
 634                                 "iface",
 635                                 "rbbmtimer",
 636                                 "mem",
 637                                 "mem_iface";
 638
 639                         power-domains = <&mmcc GPU_GDSC>;
 640                         iommus = <&adreno_smmu 0>;
 641
 642                         nvmem-cells = <&gpu_speed_bin>;
 643                         nvmem-cell-names = "speed_bin";
 644
 645                         qcom,gpu-quirk-two-pass-use-wfi;
 646                         qcom,gpu-quirk-fault-detect-mask;
 647
 648                         operating-points-v2 = <&gpu_opp_table>;
 649
 650                         gpu_opp_table: opp-table {
 651                                 compatible  ="operating-points-v2";
 652
 653                                 /*
 654                                  * 624Mhz and 560Mhz are only available on speed
 655                                  * bin (1 << 0). All the rest are available on
 656                                  * all bins of the hardware
 657                                  */
 658                                 opp-624000000 {
 659                                         opp-hz = /bits/ 64 <624000000>;
 660                                         opp-supported-hw = <0x01>;
 661                                 };
 662                                 opp-560000000 {
 663                                         opp-hz = /bits/ 64 <560000000>;
 664                                         opp-supported-hw = <0x01>;
 665                                 };
 666                                 opp-510000000 {
 667                                         opp-hz = /bits/ 64 <510000000>;
 668                                         opp-supported-hw = <0xFF>;
 669                                 };
 670                                 opp-401800000 {
 671                                         opp-hz = /bits/ 64 <401800000>;
 672                                         opp-supported-hw = <0xFF>;
 673                                 };
 674                                 opp-315000000 {
 675                                         opp-hz = /bits/ 64 <315000000>;
 676                                         opp-supported-hw = <0xFF>;
 677                                 };
 678                                 opp-214000000 {
 679                                         opp-hz = /bits/ 64 <214000000>;
 680                                         opp-supported-hw = <0xFF>;
 681                                 };
 682                                 opp-133000000 {
 683                                         opp-hz = /bits/ 64 <133000000>;
 684                                         opp-supported-hw = <0xFF>;
 685                                 };
 686                         };
 687
 688                         zap-shader {
 689                                 memory-region = <&zap_shader_region>;
 690                         };
 691                 };
 692
 693                 msmgpio: pinctrl@1010000 {
 694                         compatible = "qcom,msm8996-pinctrl";
 695                         reg = <0x01010000 0x300000>;
 696                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 697                         gpio-controller;
 698                         #gpio-cells = <2>;
 699                         interrupt-controller;
 700                         #interrupt-cells = <2>;
 701                 };
 702
 703                 spmi_bus: qcom,spmi@400f000 {
 704                         compatible = "qcom,spmi-pmic-arb";
 705                         reg = <0x0400f000 0x1000>,
 706                               <0x04400000 0x800000>,
 707                               <0x04c00000 0x800000>,
 708                               <0x05800000 0x200000>,
 709                               <0x0400a000 0x002100>;
 710                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
 711                         interrupt-names = "periph_irq";
 712                         interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
 713                         qcom,ee = <0>;
 714                         qcom,channel = <0>;
 715                         #address-cells = <2>;
 716                         #size-cells = <0>;
 717                         interrupt-controller;
 718                         #interrupt-cells = <4>;
 719                 };
 720
 721                 agnoc@0 {
 722                         power-domains = <&gcc AGGRE0_NOC_GDSC>;
 723                         compatible = "simple-pm-bus";
 724                         #address-cells = <1>;
 725                         #size-cells = <1>;
 726                         ranges;
 727
 728                         pcie0: pcie@600000 {
 729                                 compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
 730                                 status = "disabled";
 731                                 power-domains = <&gcc PCIE0_GDSC>;
 732                                 bus-range = <0x00 0xff>;
 733                                 num-lanes = <1>;
 734
 735                                 reg = <0x00600000 0x2000>,
 736                                       <0x0c000000 0xf1d>,
 737                                       <0x0c000f20 0xa8>,
 738                                       <0x0c100000 0x100000>;
 739                                 reg-names = "parf", "dbi", "elbi","config";
 740
 741                                 phys = <&pciephy_0>;
 742                                 phy-names = "pciephy";
 743
 744                                 #address-cells = <3>;
 745                                 #size-cells = <2>;
 746                                 ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>,
 747                                         <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
 748
 749                                 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
 750                                 interrupt-names = "msi";
 751                                 #interrupt-cells = <1>;
 752                                 interrupt-map-mask = <0 0 0 0x7>;
 753                                 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 754                                                 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 755                                                 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 756                                                 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 757
 758                                 pinctrl-names = "default", "sleep";
 759                                 pinctrl-0 = <&pcie0_clkreq_default &pcie0_perst_default &pcie0_wake_default>;
 760                                 pinctrl-1 = <&pcie0_clkreq_sleep &pcie0_perst_default &pcie0_wake_sleep>;
 761
 762                                 linux,pci-domain = <0>;
 763
 764                                 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
 765                                         <&gcc GCC_PCIE_0_AUX_CLK>,
 766                                         <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
 767                                         <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
 768                                         <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
 769
 770                                 clock-names =  "pipe",
 771                                                 "aux",
 772                                                 "cfg",
 773                                                 "bus_master",
 774                                                 "bus_slave";
 775
 776                         };
 777
 778                         pcie1: pcie@608000 {
 779                                 compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
 780                                 power-domains = <&gcc PCIE1_GDSC>;
 781                                 bus-range = <0x00 0xff>;
 782                                 num-lanes = <1>;
 783
 784                                 status  = "disabled";
 785
 786                                 reg = <0x00608000 0x2000>,
 787                                       <0x0d000000 0xf1d>,
 788                                       <0x0d000f20 0xa8>,
 789                                       <0x0d100000 0x100000>;
 790
 791                                 reg-names = "parf", "dbi", "elbi","config";
 792
 793                                 phys = <&pciephy_1>;
 794                                 phy-names = "pciephy";
 795
 796                                 #address-cells = <3>;
 797                                 #size-cells = <2>;
 798                                 ranges = <0x01000000 0x0 0x0d200000 0x0d200000 0x0 0x100000>,
 799                                         <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>;
 800
 801                                 interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
 802                                 interrupt-names = "msi";
 803                                 #interrupt-cells = <1>;
 804                                 interrupt-map-mask = <0 0 0 0x7>;
 805                                 interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 806                                                 <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 807                                                 <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 808                                                 <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 809
 810                                 pinctrl-names = "default", "sleep";
 811                                 pinctrl-0 = <&pcie1_clkreq_default &pcie1_perst_default &pcie1_wake_default>;
 812                                 pinctrl-1 = <&pcie1_clkreq_sleep &pcie1_perst_default &pcie1_wake_sleep>;
 813
 814                                 linux,pci-domain = <1>;
 815
 816                                 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
 817                                         <&gcc GCC_PCIE_1_AUX_CLK>,
 818                                         <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
 819                                         <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
 820                                         <&gcc GCC_PCIE_1_SLV_AXI_CLK>;
 821
 822                                 clock-names =  "pipe",
 823                                                 "aux",
 824                                                 "cfg",
 825                                                 "bus_master",
 826                                                 "bus_slave";
 827                         };
 828
 829                         pcie2: pcie@610000 {
 830                                 compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
 831                                 power-domains = <&gcc PCIE2_GDSC>;
 832                                 bus-range = <0x00 0xff>;
 833                                 num-lanes = <1>;
 834                                 status = "disabled";
 835                                 reg = <0x00610000 0x2000>,
 836                                       <0x0e000000 0xf1d>,
 837                                       <0x0e000f20 0xa8>,
 838                                       <0x0e100000 0x100000>;
 839
 840                                 reg-names = "parf", "dbi", "elbi","config";
 841
 842                                 phys = <&pciephy_2>;
 843                                 phy-names = "pciephy";
 844
 845                                 #address-cells = <3>;
 846                                 #size-cells = <2>;
 847                                 ranges = <0x01000000 0x0 0x0e200000 0x0e200000 0x0 0x100000>,
 848                                         <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>;
 849
 850                                 device_type = "pci";
 851
 852                                 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
 853                                 interrupt-names = "msi";
 854                                 #interrupt-cells = <1>;
 855                                 interrupt-map-mask = <0 0 0 0x7>;
 856                                 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 857                                                 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 858                                                 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 859                                                 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 860
 861                                 pinctrl-names = "default", "sleep";
 862                                 pinctrl-0 = <&pcie2_clkreq_default &pcie2_perst_default &pcie2_wake_default>;
 863                                 pinctrl-1 = <&pcie2_clkreq_sleep &pcie2_perst_default &pcie2_wake_sleep >;
 864
 865                                 linux,pci-domain = <2>;
 866                                 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
 867                                         <&gcc GCC_PCIE_2_AUX_CLK>,
 868                                         <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
 869                                         <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
 870                                         <&gcc GCC_PCIE_2_SLV_AXI_CLK>;
 871
 872                                 clock-names =  "pipe",
 873                                                 "aux",
 874                                                 "cfg",
 875                                                 "bus_master",
 876                                                 "bus_slave";
 877                         };
 878                 };
 879
 880                 ufshc: ufshc@624000 {
 881                         compatible = "qcom,ufshc";
 882                         reg = <0x00624000 0x2500>;
 883                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
 884
 885                         phys = <&ufsphy>;
 886                         phy-names = "ufsphy";
 887
 888                         power-domains = <&gcc UFS_GDSC>;
 889
 890                         clock-names =
 891                                 "core_clk_src",
 892                                 "core_clk",
 893                                 "bus_clk",
 894                                 "bus_aggr_clk",
 895                                 "iface_clk",
 896                                 "core_clk_unipro_src",
 897                                 "core_clk_unipro",
 898                                 "core_clk_ice",
 899                                 "ref_clk",
 900                                 "tx_lane0_sync_clk",
 901                                 "rx_lane0_sync_clk";
 902                         clocks =
 903                                 <&gcc UFS_AXI_CLK_SRC>,
 904                                 <&gcc GCC_UFS_AXI_CLK>,
 905                                 <&gcc GCC_SYS_NOC_UFS_AXI_CLK>,
 906                                 <&gcc GCC_AGGRE2_UFS_AXI_CLK>,
 907                                 <&gcc GCC_UFS_AHB_CLK>,
 908                                 <&gcc UFS_ICE_CORE_CLK_SRC>,
 909                                 <&gcc GCC_UFS_UNIPRO_CORE_CLK>,
 910                                 <&gcc GCC_UFS_ICE_CORE_CLK>,
 911                                 <&rpmcc RPM_SMD_LN_BB_CLK>,
 912                                 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
 913                                 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>;
 914                         freq-table-hz =
 915                                 <100000000 200000000>,
 916                                 <0 0>,
 917                                 <0 0>,
 918                                 <0 0>,
 919                                 <0 0>,
 920                                 <150000000 300000000>,
 921                                 <0 0>,
 922                                 <0 0>,
 923                                 <0 0>,
 924                                 <0 0>,
 925                                 <0 0>;
 926
 927                         lanes-per-direction = <1>;
 928                         #reset-cells = <1>;
 929                         status = "disabled";
 930
 931                         ufs_variant {
 932                                 compatible = "qcom,ufs_variant";
 933                         };
 934                 };
 935
 936                 ufsphy: phy@627000 {
 937                         compatible = "qcom,msm8996-ufs-phy-qmp-14nm";
 938                         reg = <0x00627000 0xda8>;
 939                         reg-names = "phy_mem";
 940                         #phy-cells = <0>;
 941
 942                         clock-names = "ref_clk_src", "ref_clk";
 943                         clocks = <&rpmcc RPM_SMD_LN_BB_CLK>,
 944                                  <&gcc GCC_UFS_CLKREF_CLK>;
 945                         resets = <&ufshc 0>;
 946                         status = "disabled";
 947                 };
 948
 949                 camss: camss@a00000 {
 950                         compatible = "qcom,msm8996-camss";
 951                         reg = <0x00a34000 0x1000>,
 952                               <0x00a00030 0x4>,
 953                               <0x00a35000 0x1000>,
 954                               <0x00a00038 0x4>,
 955                               <0x00a36000 0x1000>,
 956                               <0x00a00040 0x4>,
 957                               <0x00a30000 0x100>,
 958                               <0x00a30400 0x100>,
 959                               <0x00a30800 0x100>,
 960                               <0x00a30c00 0x100>,
 961                               <0x00a31000 0x500>,
 962                               <0x00a00020 0x10>,
 963                               <0x00a10000 0x1000>,
 964                               <0x00a14000 0x1000>;
 965                         reg-names = "csiphy0",
 966                                 "csiphy0_clk_mux",
 967                                 "csiphy1",
 968                                 "csiphy1_clk_mux",
 969                                 "csiphy2",
 970                                 "csiphy2_clk_mux",
 971                                 "csid0",
 972                                 "csid1",
 973                                 "csid2",
 974                                 "csid3",
 975                                 "ispif",
 976                                 "csi_clk_mux",
 977                                 "vfe0",
 978                                 "vfe1";
 979                         interrupts = <GIC_SPI 78 0>,
 980                                 <GIC_SPI 79 0>,
 981                                 <GIC_SPI 80 0>,
 982                                 <GIC_SPI 296 0>,
 983                                 <GIC_SPI 297 0>,
 984                                 <GIC_SPI 298 0>,
 985                                 <GIC_SPI 299 0>,
 986                                 <GIC_SPI 309 0>,
 987                                 <GIC_SPI 314 0>,
 988                                 <GIC_SPI 315 0>;
 989                         interrupt-names = "csiphy0",
 990                                 "csiphy1",
 991                                 "csiphy2",
 992                                 "csid0",
 993                                 "csid1",
 994                                 "csid2",
 995                                 "csid3",
 996                                 "ispif",
 997                                 "vfe0",
 998                                 "vfe1";
 999                         power-domains = <&mmcc VFE0_GDSC>;
1000                         clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
1001                                 <&mmcc CAMSS_ISPIF_AHB_CLK>,
1002                                 <&mmcc CAMSS_CSI0PHYTIMER_CLK>,
1003                                 <&mmcc CAMSS_CSI1PHYTIMER_CLK>,
1004                                 <&mmcc CAMSS_CSI2PHYTIMER_CLK>,
1005                                 <&mmcc CAMSS_CSI0_AHB_CLK>,
1006                                 <&mmcc CAMSS_CSI0_CLK>,
1007                                 <&mmcc CAMSS_CSI0PHY_CLK>,
1008                                 <&mmcc CAMSS_CSI0PIX_CLK>,
1009                                 <&mmcc CAMSS_CSI0RDI_CLK>,
1010                                 <&mmcc CAMSS_CSI1_AHB_CLK>,
1011                                 <&mmcc CAMSS_CSI1_CLK>,
1012                                 <&mmcc CAMSS_CSI1PHY_CLK>,
1013                                 <&mmcc CAMSS_CSI1PIX_CLK>,
1014                                 <&mmcc CAMSS_CSI1RDI_CLK>,
1015                                 <&mmcc CAMSS_CSI2_AHB_CLK>,
1016                                 <&mmcc CAMSS_CSI2_CLK>,
1017                                 <&mmcc CAMSS_CSI2PHY_CLK>,
1018                                 <&mmcc CAMSS_CSI2PIX_CLK>,
1019                                 <&mmcc CAMSS_CSI2RDI_CLK>,
1020                                 <&mmcc CAMSS_CSI3_AHB_CLK>,
1021                                 <&mmcc CAMSS_CSI3_CLK>,
1022                                 <&mmcc CAMSS_CSI3PHY_CLK>,
1023                                 <&mmcc CAMSS_CSI3PIX_CLK>,
1024                                 <&mmcc CAMSS_CSI3RDI_CLK>,
1025                                 <&mmcc CAMSS_AHB_CLK>,
1026                                 <&mmcc CAMSS_VFE0_CLK>,
1027                                 <&mmcc CAMSS_CSI_VFE0_CLK>,
1028                                 <&mmcc CAMSS_VFE0_AHB_CLK>,
1029                                 <&mmcc CAMSS_VFE0_STREAM_CLK>,
1030                                 <&mmcc CAMSS_VFE1_CLK>,
1031                                 <&mmcc CAMSS_CSI_VFE1_CLK>,
1032                                 <&mmcc CAMSS_VFE1_AHB_CLK>,
1033                                 <&mmcc CAMSS_VFE1_STREAM_CLK>,
1034                                 <&mmcc CAMSS_VFE_AHB_CLK>,
1035                                 <&mmcc CAMSS_VFE_AXI_CLK>;
1036                         clock-names = "top_ahb",
1037                                 "ispif_ahb",
1038                                 "csiphy0_timer",
1039                                 "csiphy1_timer",
1040                                 "csiphy2_timer",
1041                                 "csi0_ahb",
1042                                 "csi0",
1043                                 "csi0_phy",
1044                                 "csi0_pix",
1045                                 "csi0_rdi",
1046                                 "csi1_ahb",
1047                                 "csi1",
1048                                 "csi1_phy",
1049                                 "csi1_pix",
1050                                 "csi1_rdi",
1051                                 "csi2_ahb",
1052                                 "csi2",
1053                                 "csi2_phy",
1054                                 "csi2_pix",
1055                                 "csi2_rdi",
1056                                 "csi3_ahb",
1057                                 "csi3",
1058                                 "csi3_phy",
1059                                 "csi3_pix",
1060                                 "csi3_rdi",
1061                                 "ahb",
1062                                 "vfe0",
1063                                 "csi_vfe0",
1064                                 "vfe0_ahb",
1065                                 "vfe0_stream",
1066                                 "vfe1",
1067                                 "csi_vfe1",
1068                                 "vfe1_ahb",
1069                                 "vfe1_stream",
1070                                 "vfe_ahb",
1071                                 "vfe_axi";
1072                         iommus = <&vfe_smmu 0>,
1073                                  <&vfe_smmu 1>,
1074                                  <&vfe_smmu 2>,
1075                                  <&vfe_smmu 3>;
1076                         status = "disabled";
1077                         ports {
1078                                 #address-cells = <1>;
1079                                 #size-cells = <0>;
1080                         };
1081                 };
1082
1083                 adreno_smmu: iommu@b40000 {
1084                         compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
1085                         reg = <0x00b40000 0x10000>;
1086
1087                         #global-interrupts = <1>;
1088                         interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1089                                      <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1090                                      <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
1091                         #iommu-cells = <1>;
1092
1093                         clocks = <&mmcc GPU_AHB_CLK>,
1094                                  <&gcc GCC_MMSS_BIMC_GFX_CLK>;
1095                         clock-names = "iface", "bus";
1096
1097                         power-domains = <&mmcc GPU_GDSC>;
1098                 };
1099
1100                 video-codec@c00000 {
1101                         compatible = "qcom,msm8996-venus";
1102                         reg = <0x00c00000 0xff000>;
1103                         interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
1104                         power-domains = <&mmcc VENUS_GDSC>;
1105                         clocks = <&mmcc VIDEO_CORE_CLK>,
1106                                  <&mmcc VIDEO_AHB_CLK>,
1107                                  <&mmcc VIDEO_AXI_CLK>,
1108                                  <&mmcc VIDEO_MAXI_CLK>;
1109                         clock-names = "core", "iface", "bus", "mbus";
1110                         iommus = <&venus_smmu 0x00>,
1111                                  <&venus_smmu 0x01>,
1112                                  <&venus_smmu 0x0a>,
1113                                  <&venus_smmu 0x07>,
1114                                  <&venus_smmu 0x0e>,
1115                                  <&venus_smmu 0x0f>,
1116                                  <&venus_smmu 0x08>,
1117                                  <&venus_smmu 0x09>,
1118                                  <&venus_smmu 0x0b>,
1119                                  <&venus_smmu 0x0c>,
1120                                  <&venus_smmu 0x0d>,
1121                                  <&venus_smmu 0x10>,
1122                                  <&venus_smmu 0x11>,
1123                                  <&venus_smmu 0x21>,
1124                                  <&venus_smmu 0x28>,
1125                                  <&venus_smmu 0x29>,
1126                                  <&venus_smmu 0x2b>,
1127                                  <&venus_smmu 0x2c>,
1128                                  <&venus_smmu 0x2d>,
1129                                  <&venus_smmu 0x31>;
1130                         memory-region = <&venus_region>;
1131                         status = "okay";
1132
1133                         video-decoder {
1134                                 compatible = "venus-decoder";
1135                                 clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
1136                                 clock-names = "core";
1137                                 power-domains = <&mmcc VENUS_CORE0_GDSC>;
1138                         };
1139
1140                         video-encoder {
1141                                 compatible = "venus-encoder";
1142                                 clocks = <&mmcc VIDEO_SUBCORE1_CLK>;
1143                                 clock-names = "core";
1144                                 power-domains = <&mmcc VENUS_CORE1_GDSC>;
1145                         };
1146                 };
1147
1148                 mdp_smmu: iommu@d00000 {
1149                         compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
1150                         reg = <0x00d00000 0x10000>;
1151
1152                         #global-interrupts = <1>;
1153                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1154                                      <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
1155                                      <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
1156                         #iommu-cells = <1>;
1157                         clocks = <&mmcc SMMU_MDP_AHB_CLK>,
1158                                  <&mmcc SMMU_MDP_AXI_CLK>;
1159                         clock-names = "iface", "bus";
1160
1161                         power-domains = <&mmcc MDSS_GDSC>;
1162                 };
1163
1164                 venus_smmu: iommu@d40000 {
1165                         compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
1166                         reg = <0x00d40000 0x20000>;
1167                         #global-interrupts = <1>;
1168                         interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
1169                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1170                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1171                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
1172                                      <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
1173                                      <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
1174                                      <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
1175                                      <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
1176                         power-domains = <&mmcc MMAGIC_VIDEO_GDSC>;
1177                         clocks = <&mmcc SMMU_VIDEO_AHB_CLK>,
1178                                  <&mmcc SMMU_VIDEO_AXI_CLK>;
1179                         clock-names = "iface", "bus";
1180                         #iommu-cells = <1>;
1181                         status = "okay";
1182                 };
1183
1184                 vfe_smmu: iommu@da0000 {
1185                         compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
1186                         reg = <0x00da0000 0x10000>;
1187
1188                         #global-interrupts = <1>;
1189                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
1190                                      <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
1191                                      <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1192                         power-domains = <&mmcc MMAGIC_CAMSS_GDSC>;
1193                         clocks = <&mmcc SMMU_VFE_AHB_CLK>,
1194                                  <&mmcc SMMU_VFE_AXI_CLK>;
1195                         clock-names = "iface",
1196                                       "bus";
1197                         #iommu-cells = <1>;
1198                 };
1199
1200                 lpass_q6_smmu: iommu@1600000 {
1201                         compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
1202                         reg = <0x01600000 0x20000>;
1203                         #iommu-cells = <1>;
1204                         power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>;
1205
1206                         #global-interrupts = <1>;
1207                         interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
1208                                 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
1209                                 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
1210                                 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
1211                                 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
1212                                 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
1213                                 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
1214                                 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
1215                                 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
1216                                 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
1217                                 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
1218                                 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
1219                                 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>;
1220
1221                         clocks = <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>,
1222                                  <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>;
1223                         clock-names = "iface", "bus";
1224                 };
1225
1226                 stm@3002000 {
1227                         compatible = "arm,coresight-stm", "arm,primecell";
1228                         reg = <0x3002000 0x1000>,
1229                               <0x8280000 0x180000>;
1230                         reg-names = "stm-base", "stm-stimulus-base";
1231
1232                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1233                         clock-names = "apb_pclk", "atclk";
1234
1235                         out-ports {
1236                                 port {
1237                                         stm_out: endpoint {
1238                                                 remote-endpoint =
1239                                                   <&funnel0_in>;
1240                                         };
1241                                 };
1242                         };
1243                 };
1244
1245                 tpiu@3020000 {
1246                         compatible = "arm,coresight-tpiu", "arm,primecell";
1247                         reg = <0x3020000 0x1000>;
1248
1249                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1250                         clock-names = "apb_pclk", "atclk";
1251
1252                         in-ports {
1253                                 port {
1254                                         tpiu_in: endpoint {
1255                                                 remote-endpoint =
1256                                                   <&replicator_out1>;
1257                                         };
1258                                 };
1259                         };
1260                 };
1261
1262                 funnel@3021000 {
1263                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1264                         reg = <0x3021000 0x1000>;
1265
1266                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1267                         clock-names = "apb_pclk", "atclk";
1268
1269                         in-ports {
1270                                 #address-cells = <1>;
1271                                 #size-cells = <0>;
1272
1273                                 port@7 {
1274                                         reg = <7>;
1275                                         funnel0_in: endpoint {
1276                                                 remote-endpoint =
1277                                                   <&stm_out>;
1278                                         };
1279                                 };
1280                         };
1281
1282                         out-ports {
1283                                 port {
1284                                         funnel0_out: endpoint {
1285                                                 remote-endpoint =
1286                                                   <&merge_funnel_in0>;
1287                                         };
1288                                 };
1289                         };
1290                 };
1291
1292                 funnel@3022000 {
1293                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1294                         reg = <0x3022000 0x1000>;
1295
1296                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1297                         clock-names = "apb_pclk", "atclk";
1298
1299                         in-ports {
1300                                 #address-cells = <1>;
1301                                 #size-cells = <0>;
1302
1303                                 port@6 {
1304                                         reg = <6>;
1305                                         funnel1_in: endpoint {
1306                                                 remote-endpoint =
1307                                                   <&apss_merge_funnel_out>;
1308                                         };
1309                                 };
1310                         };
1311
1312                         out-ports {
1313                                 port {
1314                                         funnel1_out: endpoint {
1315                                                 remote-endpoint =
1316                                                   <&merge_funnel_in1>;
1317                                         };
1318                                 };
1319                         };
1320                 };
1321
1322                 funnel@3023000 {
1323                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1324                         reg = <0x3023000 0x1000>;
1325
1326                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1327                         clock-names = "apb_pclk", "atclk";
1328
1329
1330                         out-ports {
1331                                 port {
1332                                         funnel2_out: endpoint {
1333                                                 remote-endpoint =
1334                                                   <&merge_funnel_in2>;
1335                                         };
1336                                 };
1337                         };
1338                 };
1339
1340                 funnel@3025000 {
1341                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1342                         reg = <0x3025000 0x1000>;
1343
1344                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1345                         clock-names = "apb_pclk", "atclk";
1346
1347                         in-ports {
1348                                 #address-cells = <1>;
1349                                 #size-cells = <0>;
1350
1351                                 port@0 {
1352                                         reg = <0>;
1353                                         merge_funnel_in0: endpoint {
1354                                                 remote-endpoint =
1355                                                   <&funnel0_out>;
1356                                         };
1357                                 };
1358
1359                                 port@1 {
1360                                         reg = <1>;
1361                                         merge_funnel_in1: endpoint {
1362                                                 remote-endpoint =
1363                                                   <&funnel1_out>;
1364                                         };
1365                                 };
1366
1367                                 port@2 {
1368                                         reg = <2>;
1369                                         merge_funnel_in2: endpoint {
1370                                                 remote-endpoint =
1371                                                   <&funnel2_out>;
1372                                         };
1373                                 };
1374                         };
1375
1376                         out-ports {
1377                                 port {
1378                                         merge_funnel_out: endpoint {
1379                                                 remote-endpoint =
1380                                                   <&etf_in>;
1381                                         };
1382                                 };
1383                         };
1384                 };
1385
1386                 replicator@3026000 {
1387                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
1388                         reg = <0x3026000 0x1000>;
1389
1390                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1391                         clock-names = "apb_pclk", "atclk";
1392
1393                         in-ports {
1394                                 port {
1395                                         replicator_in: endpoint {
1396                                                 remote-endpoint =
1397                                                   <&etf_out>;
1398                                         };
1399                                 };
1400                         };
1401
1402                         out-ports {
1403                                 #address-cells = <1>;
1404                                 #size-cells = <0>;
1405
1406                                 port@0 {
1407                                         reg = <0>;
1408                                         replicator_out0: endpoint {
1409                                                 remote-endpoint =
1410                                                   <&etr_in>;
1411                                         };
1412                                 };
1413
1414                                 port@1 {
1415                                         reg = <1>;
1416                                         replicator_out1: endpoint {
1417                                                 remote-endpoint =
1418                                                   <&tpiu_in>;
1419                                         };
1420                                 };
1421                         };
1422                 };
1423
1424                 etf@3027000 {
1425                         compatible = "arm,coresight-tmc", "arm,primecell";
1426                         reg = <0x3027000 0x1000>;
1427
1428                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1429                         clock-names = "apb_pclk", "atclk";
1430
1431                         in-ports {
1432                                 port {
1433                                         etf_in: endpoint {
1434                                                 remote-endpoint =
1435                                                   <&merge_funnel_out>;
1436                                         };
1437                                 };
1438                         };
1439
1440                         out-ports {
1441                                 port {
1442                                         etf_out: endpoint {
1443                                                 remote-endpoint =
1444                                                   <&replicator_in>;
1445                                         };
1446                                 };
1447                         };
1448                 };
1449
1450                 etr@3028000 {
1451                         compatible = "arm,coresight-tmc", "arm,primecell";
1452                         reg = <0x3028000 0x1000>;
1453
1454                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1455                         clock-names = "apb_pclk", "atclk";
1456                         arm,scatter-gather;
1457
1458                         in-ports {
1459                                 port {
1460                                         etr_in: endpoint {
1461                                                 remote-endpoint =
1462                                                   <&replicator_out0>;
1463                                         };
1464                                 };
1465                         };
1466                 };
1467
1468                 debug@3810000 {
1469                         compatible = "arm,coresight-cpu-debug", "arm,primecell";
1470                         reg = <0x3810000 0x1000>;
1471
1472                         clocks = <&rpmcc RPM_QDSS_CLK>;
1473                         clock-names = "apb_pclk";
1474
1475                         cpu = <&CPU0>;
1476                 };
1477
1478                 etm@3840000 {
1479                         compatible = "arm,coresight-etm4x", "arm,primecell";
1480                         reg = <0x3840000 0x1000>;
1481
1482                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1483                         clock-names = "apb_pclk", "atclk";
1484
1485                         cpu = <&CPU0>;
1486
1487                         out-ports {
1488                                 port {
1489                                         etm0_out: endpoint {
1490                                                 remote-endpoint =
1491                                                   <&apss_funnel0_in0>;
1492                                         };
1493                                 };
1494                         };
1495                 };
1496
1497                 debug@3910000 {
1498                         compatible = "arm,coresight-cpu-debug", "arm,primecell";
1499                         reg = <0x3910000 0x1000>;
1500
1501                         clocks = <&rpmcc RPM_QDSS_CLK>;
1502                         clock-names = "apb_pclk";
1503
1504                         cpu = <&CPU1>;
1505                 };
1506
1507                 etm@3940000 {
1508                         compatible = "arm,coresight-etm4x", "arm,primecell";
1509                         reg = <0x3940000 0x1000>;
1510
1511                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1512                         clock-names = "apb_pclk", "atclk";
1513
1514                         cpu = <&CPU1>;
1515
1516                         out-ports {
1517                                 port {
1518                                         etm1_out: endpoint {
1519                                                 remote-endpoint =
1520                                                   <&apss_funnel0_in1>;
1521                                         };
1522                                 };
1523                         };
1524                 };
1525
1526                 funnel@39b0000 { /* APSS Funnel 0 */
1527                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1528                         reg = <0x39b0000 0x1000>;
1529
1530                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1531                         clock-names = "apb_pclk", "atclk";
1532
1533                         in-ports {
1534                                 #address-cells = <1>;
1535                                 #size-cells = <0>;
1536
1537                                 port@0 {
1538                                         reg = <0>;
1539                                         apss_funnel0_in0: endpoint {
1540                                                 remote-endpoint = <&etm0_out>;
1541                                         };
1542                                 };
1543
1544                                 port@1 {
1545                                         reg = <1>;
1546                                         apss_funnel0_in1: endpoint {
1547                                                 remote-endpoint = <&etm1_out>;
1548                                         };
1549                                 };
1550                         };
1551
1552                         out-ports {
1553                                 port {
1554                                         apss_funnel0_out: endpoint {
1555                                                 remote-endpoint =
1556                                                   <&apss_merge_funnel_in0>;
1557                                         };
1558                                 };
1559                         };
1560                 };
1561
1562                 debug@3a10000 {
1563                         compatible = "arm,coresight-cpu-debug", "arm,primecell";
1564                         reg = <0x3a10000 0x1000>;
1565
1566                         clocks = <&rpmcc RPM_QDSS_CLK>;
1567                         clock-names = "apb_pclk";
1568
1569                         cpu = <&CPU2>;
1570                 };
1571
1572                 etm@3a40000 {
1573                         compatible = "arm,coresight-etm4x", "arm,primecell";
1574                         reg = <0x3a40000 0x1000>;
1575
1576                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1577                         clock-names = "apb_pclk", "atclk";
1578
1579                         cpu = <&CPU2>;
1580
1581                         out-ports {
1582                                 port {
1583                                         etm2_out: endpoint {
1584                                                 remote-endpoint =
1585                                                   <&apss_funnel1_in0>;
1586                                         };
1587                                 };
1588                         };
1589                 };
1590
1591                 debug@3b10000 {
1592                         compatible = "arm,coresight-cpu-debug", "arm,primecell";
1593                         reg = <0x3b10000 0x1000>;
1594
1595                         clocks = <&rpmcc RPM_QDSS_CLK>;
1596                         clock-names = "apb_pclk";
1597
1598                         cpu = <&CPU3>;
1599                 };
1600
1601                 etm@3b40000 {
1602                         compatible = "arm,coresight-etm4x", "arm,primecell";
1603                         reg = <0x3b40000 0x1000>;
1604
1605                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1606                         clock-names = "apb_pclk", "atclk";
1607
1608                         cpu = <&CPU3>;
1609
1610                         out-ports {
1611                                 port {
1612                                         etm3_out: endpoint {
1613                                                 remote-endpoint =
1614                                                   <&apss_funnel1_in1>;
1615                                         };
1616                                 };
1617                         };
1618                 };
1619
1620                 funnel@3bb0000 { /* APSS Funnel 1 */
1621                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1622                         reg = <0x3bb0000 0x1000>;
1623
1624                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1625                         clock-names = "apb_pclk", "atclk";
1626
1627                         in-ports {
1628                                 #address-cells = <1>;
1629                                 #size-cells = <0>;
1630
1631                                 port@0 {
1632                                         reg = <0>;
1633                                         apss_funnel1_in0: endpoint {
1634                                                 remote-endpoint = <&etm2_out>;
1635                                         };
1636                                 };
1637
1638                                 port@1 {
1639                                         reg = <1>;
1640                                         apss_funnel1_in1: endpoint {
1641                                                 remote-endpoint = <&etm3_out>;
1642                                         };
1643                                 };
1644                         };
1645
1646                         out-ports {
1647                                 port {
1648                                         apss_funnel1_out: endpoint {
1649                                                 remote-endpoint =
1650                                                   <&apss_merge_funnel_in1>;
1651                                         };
1652                                 };
1653                         };
1654                 };
1655
1656                 funnel@3bc0000 {
1657                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1658                         reg = <0x3bc0000 0x1000>;
1659
1660                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1661                         clock-names = "apb_pclk", "atclk";
1662
1663                         in-ports {
1664                                 #address-cells = <1>;
1665                                 #size-cells = <0>;
1666
1667                                 port@0 {
1668                                         reg = <0>;
1669                                         apss_merge_funnel_in0: endpoint {
1670                                                 remote-endpoint =
1671                                                   <&apss_funnel0_out>;
1672                                         };
1673                                 };
1674
1675                                 port@1 {
1676                                         reg = <1>;
1677                                         apss_merge_funnel_in1: endpoint {
1678                                                 remote-endpoint =
1679                                                   <&apss_funnel1_out>;
1680                                         };
1681                                 };
1682                         };
1683
1684                         out-ports {
1685                                 port {
1686                                         apss_merge_funnel_out: endpoint {
1687                                                 remote-endpoint =
1688                                                   <&funnel1_in>;
1689                                         };
1690                                 };
1691                         };
1692                 };
1693                 kryocc: clock-controller@6400000 {
1694                         compatible = "qcom,apcc-msm8996";
1695                         reg = <0x06400000 0x90000>;
1696                         #clock-cells = <1>;
1697                 };
1698
1699                 usb3: usb@6af8800 {
1700                         compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
1701                         reg = <0x06af8800 0x400>;
1702                         #address-cells = <1>;
1703                         #size-cells = <1>;
1704                         ranges;
1705
1706                         clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
1707                                 <&gcc GCC_USB30_MASTER_CLK>,
1708                                 <&gcc GCC_AGGRE2_USB3_AXI_CLK>,
1709                                 <&gcc GCC_USB30_MOCK_UTMI_CLK>,
1710                                 <&gcc GCC_USB30_SLEEP_CLK>,
1711                                 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
1712
1713                         assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
1714                                           <&gcc GCC_USB30_MASTER_CLK>;
1715                         assigned-clock-rates = <19200000>, <120000000>;
1716
1717                         power-domains = <&gcc USB30_GDSC>;
1718                         status = "disabled";
1719
1720                         dwc3@6a00000 {
1721                                 compatible = "snps,dwc3";
1722                                 reg = <0x06a00000 0xcc00>;
1723                                 interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
1724                                 phys = <&hsusb_phy1>, <&ssusb_phy_0>;
1725                                 phy-names = "usb2-phy", "usb3-phy";
1726                                 snps,dis_u2_susphy_quirk;
1727                                 snps,dis_enblslpm_quirk;
1728                         };
1729                 };
1730
1731                 usb3phy: phy@7410000 {
1732                         compatible = "qcom,msm8996-qmp-usb3-phy";
1733                         reg = <0x07410000 0x1c4>;
1734                         #clock-cells = <1>;
1735                         #address-cells = <1>;
1736                         #size-cells = <1>;
1737                         ranges;
1738
1739                         clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
1740                                 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1741                                 <&gcc GCC_USB3_CLKREF_CLK>;
1742                         clock-names = "aux", "cfg_ahb", "ref";
1743
1744                         resets = <&gcc GCC_USB3_PHY_BCR>,
1745                                 <&gcc GCC_USB3PHY_PHY_BCR>;
1746                         reset-names = "phy", "common";
1747                         status = "disabled";
1748
1749                         ssusb_phy_0: lane@7410200 {
1750                                 reg = <0x07410200 0x200>,
1751                                       <0x07410400 0x130>,
1752                                       <0x07410600 0x1a8>;
1753                                 #phy-cells = <0>;
1754
1755                                 clock-output-names = "usb3_phy_pipe_clk_src";
1756                                 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
1757                                 clock-names = "pipe0";
1758                         };
1759                 };
1760
1761                 hsusb_phy1: phy@7411000 {
1762                         compatible = "qcom,msm8996-qusb2-phy";
1763                         reg = <0x07411000 0x180>;
1764                         #phy-cells = <0>;
1765
1766                         clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1767                                 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
1768                         clock-names = "cfg_ahb", "ref";
1769
1770                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
1771                         nvmem-cells = <&qusb2p_hstx_trim>;
1772                         status = "disabled";
1773                 };
1774
1775                 hsusb_phy2: phy@7412000 {
1776                         compatible = "qcom,msm8996-qusb2-phy";
1777                         reg = <0x07412000 0x180>;
1778                         #phy-cells = <0>;
1779
1780                         clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1781                                 <&gcc GCC_RX2_USB2_CLKREF_CLK>;
1782                         clock-names = "cfg_ahb", "ref";
1783
1784                         resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
1785                         nvmem-cells = <&qusb2s_hstx_trim>;
1786                         status = "disabled";
1787                 };
1788
1789                 sdhc2: sdhci@74a4900 {
1790                          status = "disabled";
1791                          compatible = "qcom,sdhci-msm-v4";
1792                          reg = <0x074a4900 0x314>, <0x074a4000 0x800>;
1793                          reg-names = "hc_mem", "core_mem";
1794
1795                          interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>,
1796                                       <0 221 IRQ_TYPE_LEVEL_HIGH>;
1797                          interrupt-names = "hc_irq", "pwr_irq";
1798
1799                          clock-names = "iface", "core", "xo";
1800                          clocks = <&gcc GCC_SDCC2_AHB_CLK>,
1801                          <&gcc GCC_SDCC2_APPS_CLK>,
1802                          <&xo_board>;
1803                          bus-width = <4>;
1804                  };
1805
1806                 blsp1_uart1: serial@7570000 {
1807                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1808                         reg = <0x07570000 0x1000>;
1809                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1810                         clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
1811                                  <&gcc GCC_BLSP1_AHB_CLK>;
1812                         clock-names = "core", "iface";
1813                         status = "disabled";
1814                 };
1815
1816                 blsp1_spi0: spi@7575000 {
1817                         compatible = "qcom,spi-qup-v2.2.1";
1818                         reg = <0x07575000 0x600>;
1819                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1820                         clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
1821                                  <&gcc GCC_BLSP1_AHB_CLK>;
1822                         clock-names = "core", "iface";
1823                         pinctrl-names = "default", "sleep";
1824                         pinctrl-0 = <&blsp1_spi0_default>;
1825                         pinctrl-1 = <&blsp1_spi0_sleep>;
1826                         #address-cells = <1>;
1827                         #size-cells = <0>;
1828                         status = "disabled";
1829                 };
1830
1831                 blsp1_i2c2: i2c@7577000 {
1832                         compatible = "qcom,i2c-qup-v2.2.1";
1833                         reg = <0x07577000 0x1000>;
1834                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1835                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
1836                                 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
1837                         clock-names = "iface", "core";
1838                         pinctrl-names = "default", "sleep";
1839                         pinctrl-0 = <&blsp1_i2c2_default>;
1840                         pinctrl-1 = <&blsp1_i2c2_sleep>;
1841                         #address-cells = <1>;
1842                         #size-cells = <0>;
1843                         status = "disabled";
1844                 };
1845
1846                 blsp2_uart1: serial@75b0000 {
1847                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1848                         reg = <0x075b0000 0x1000>;
1849                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
1850                         clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
1851                                  <&gcc GCC_BLSP2_AHB_CLK>;
1852                         clock-names = "core", "iface";
1853                         status = "disabled";
1854                 };
1855
1856                 blsp2_uart2: serial@75b1000 {
1857                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1858                         reg = <0x075b1000 0x1000>;
1859                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
1860                         clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>,
1861                                  <&gcc GCC_BLSP2_AHB_CLK>;
1862                         clock-names = "core", "iface";
1863                         status = "disabled";
1864                 };
1865
1866                 blsp2_i2c0: i2c@75b5000 {
1867                         compatible = "qcom,i2c-qup-v2.2.1";
1868                         reg = <0x075b5000 0x1000>;
1869                         interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1870                         clocks = <&gcc GCC_BLSP2_AHB_CLK>,
1871                                 <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
1872                         clock-names = "iface", "core";
1873                         pinctrl-names = "default", "sleep";
1874                         pinctrl-0 = <&blsp2_i2c0_default>;
1875                         pinctrl-1 = <&blsp2_i2c0_sleep>;
1876                         #address-cells = <1>;
1877                         #size-cells = <0>;
1878                         status = "disabled";
1879                 };
1880
1881                 blsp2_i2c1: i2c@75b6000 {
1882                         compatible = "qcom,i2c-qup-v2.2.1";
1883                         reg = <0x075b6000 0x1000>;
1884                         interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1885                         clocks = <&gcc GCC_BLSP2_AHB_CLK>,
1886                                 <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>;
1887                         clock-names = "iface", "core";
1888                         pinctrl-names = "default", "sleep";
1889                         pinctrl-0 = <&blsp2_i2c1_default>;
1890                         pinctrl-1 = <&blsp2_i2c1_sleep>;
1891                         #address-cells = <1>;
1892                         #size-cells = <0>;
1893                         status = "disabled";
1894                 };
1895
1896                 blsp2_spi5: spi@75ba000{
1897                         compatible = "qcom,spi-qup-v2.2.1";
1898                         reg = <0x075ba000 0x600>;
1899                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
1900                         clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>,
1901                                  <&gcc GCC_BLSP2_AHB_CLK>;
1902                         clock-names = "core", "iface";
1903                         pinctrl-names = "default", "sleep";
1904                         pinctrl-0 = <&blsp2_spi5_default>;
1905                         pinctrl-1 = <&blsp2_spi5_sleep>;
1906                         #address-cells = <1>;
1907                         #size-cells = <0>;
1908                         status = "disabled";
1909                 };
1910
1911                 usb2: usb@76f8800 {
1912                         compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
1913                         reg = <0x076f8800 0x400>;
1914                         #address-cells = <1>;
1915                         #size-cells = <1>;
1916                         ranges;
1917
1918                         clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>,
1919                                 <&gcc GCC_USB20_MASTER_CLK>,
1920                                 <&gcc GCC_USB20_MOCK_UTMI_CLK>,
1921                                 <&gcc GCC_USB20_SLEEP_CLK>,
1922                                 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
1923
1924                         assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
1925                                           <&gcc GCC_USB20_MASTER_CLK>;
1926                         assigned-clock-rates = <19200000>, <60000000>;
1927
1928                         power-domains = <&gcc USB30_GDSC>;
1929                         status = "disabled";
1930
1931                         dwc3@7600000 {
1932                                 compatible = "snps,dwc3";
1933                                 reg = <0x07600000 0xcc00>;
1934                                 interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>;
1935                                 phys = <&hsusb_phy2>;
1936                                 phy-names = "usb2-phy";
1937                                 snps,dis_u2_susphy_quirk;
1938                                 snps,dis_enblslpm_quirk;
1939                         };
1940                 };
1941
1942                 slimbam: dma@9184000 {
1943                         compatible = "qcom,bam-v1.7.0";
1944                         qcom,controlled-remotely;
1945                         reg = <0x09184000 0x32000>;
1946                         num-channels  = <31>;
1947                         interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>;
1948                         #dma-cells = <1>;
1949                         qcom,ee = <1>;
1950                         qcom,num-ees = <2>;
1951                 };
1952
1953                 slim_msm: slim@91c0000 {
1954                         compatible = "qcom,slim-ngd-v1.5.0";
1955                         reg = <0x091c0000 0x2C000>;
1956                         reg-names = "ctrl";
1957                         interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>;
1958                         dmas =  <&slimbam 3>, <&slimbam 4>,
1959                                 <&slimbam 5>, <&slimbam 6>;
1960                         dma-names = "rx", "tx", "tx2", "rx2";
1961                         #address-cells = <1>;
1962                         #size-cells = <0>;
1963                         ngd@1 {
1964                                 reg = <1>;
1965                                 #address-cells = <1>;
1966                                 #size-cells = <1>;
1967
1968                                 tasha_ifd: tas-ifd {
1969                                         compatible = "slim217,1a0";
1970                                         reg  = <0 0>;
1971                                 };
1972
1973                                 wcd9335: codec@1{
1974                                         pinctrl-0 = <&cdc_reset_active &wcd_intr_default>;
1975                                         pinctrl-names = "default";
1976
1977                                         compatible = "slim217,1a0";
1978                                         reg  = <1 0>;
1979
1980                                         interrupt-parent = <&msmgpio>;
1981                                         interrupts = <54 IRQ_TYPE_LEVEL_HIGH>,
1982                                                      <53 IRQ_TYPE_LEVEL_HIGH>;
1983                                         interrupt-names  = "intr1", "intr2";
1984                                         interrupt-controller;
1985                                         #interrupt-cells = <1>;
1986                                         reset-gpios = <&msmgpio 64 0>;
1987
1988                                         slim-ifc-dev  = <&tasha_ifd>;
1989
1990                                         #sound-dai-cells = <1>;
1991                                 };
1992                         };
1993                 };
1994
1995                 adsp_pil: remoteproc@9300000 {
1996                         compatible = "qcom,msm8996-adsp-pil";
1997                         reg = <0x09300000 0x80000>;
1998
1999                         interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
2000                                               <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
2001                                               <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
2002                                               <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
2003                                               <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
2004                         interrupt-names = "wdog", "fatal", "ready",
2005                                           "handover", "stop-ack";
2006
2007                         clocks = <&xo_board>;
2008                         clock-names = "xo";
2009
2010                         memory-region = <&adsp_region>;
2011
2012                         qcom,smem-states = <&smp2p_adsp_out 0>;
2013                         qcom,smem-state-names = "stop";
2014
2015                         smd-edge {
2016                                 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
2017
2018                                 label = "lpass";
2019                                 mboxes = <&apcs_glb 8>;
2020                                 qcom,smd-edge = <1>;
2021                                 qcom,remote-pid = <2>;
2022                                 #address-cells = <1>;
2023                                 #size-cells = <0>;
2024                                 apr {
2025                                         power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>;
2026                                         compatible = "qcom,apr-v2";
2027                                         qcom,smd-channels = "apr_audio_svc";
2028                                         qcom,apr-domain = <APR_DOMAIN_ADSP>;
2029                                         #address-cells = <1>;
2030                                         #size-cells = <0>;
2031
2032                                         q6core {
2033                                                 reg = <APR_SVC_ADSP_CORE>;
2034                                                 compatible = "qcom,q6core";
2035                                         };
2036
2037                                         q6afe: q6afe {
2038                                                 compatible = "qcom,q6afe";
2039                                                 reg = <APR_SVC_AFE>;
2040                                                 q6afedai: dais {
2041                                                         compatible = "qcom,q6afe-dais";
2042                                                         #address-cells = <1>;
2043                                                         #size-cells = <0>;
2044                                                         #sound-dai-cells = <1>;
2045                                                         hdmi@1 {
2046                                                                 reg = <1>;
2047                                                         };
2048                                                 };
2049                                         };
2050
2051                                         q6asm: q6asm {
2052                                                 compatible = "qcom,q6asm";
2053                                                 reg = <APR_SVC_ASM>;
2054                                                 q6asmdai: dais {
2055                                                         compatible = "qcom,q6asm-dais";
2056                                                         #sound-dai-cells = <1>;
2057                                                         iommus = <&lpass_q6_smmu 1>;
2058                                                 };
2059                                         };
2060
2061                                         q6adm: q6adm {
2062                                                 compatible = "qcom,q6adm";
2063                                                 reg = <APR_SVC_ADM>;
2064                                                 q6routing: routing {
2065                                                         compatible = "qcom,q6adm-routing";
2066                                                         #sound-dai-cells = <0>;
2067                                                 };
2068                                         };
2069                                 };
2070
2071                         };
2072                 };
2073
2074                 apcs_glb: mailbox@9820000 {
2075                         compatible = "qcom,msm8996-apcs-hmss-global";
2076                         reg = <0x09820000 0x1000>;
2077
2078                         #mbox-cells = <1>;
2079                 };
2080
2081                 timer@9840000 {
2082                         #address-cells = <1>;
2083                         #size-cells = <1>;
2084                         ranges;
2085                         compatible = "arm,armv7-timer-mem";
2086                         reg = <0x09840000 0x1000>;
2087                         clock-frequency = <19200000>;
2088
2089                         frame@9850000 {
2090                                 frame-number = <0>;
2091                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
2092                                              <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
2093                                 reg = <0x09850000 0x1000>,
2094                                       <0x09860000 0x1000>;
2095                         };
2096
2097                         frame@9870000 {
2098                                 frame-number = <1>;
2099                                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
2100                                 reg = <0x09870000 0x1000>;
2101                                 status = "disabled";
2102                         };
2103
2104                         frame@9880000 {
2105                                 frame-number = <2>;
2106                                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
2107                                 reg = <0x09880000 0x1000>;
2108                                 status = "disabled";
2109                         };
2110
2111                         frame@9890000 {
2112                                 frame-number = <3>;
2113                                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
2114                                 reg = <0x09890000 0x1000>;
2115                                 status = "disabled";
2116                         };
2117
2118                         frame@98a0000 {
2119                                 frame-number = <4>;
2120                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
2121                                 reg = <0x098a0000 0x1000>;
2122                                 status = "disabled";
2123                         };
2124
2125                         frame@98b0000 {
2126                                 frame-number = <5>;
2127                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
2128                                 reg = <0x098b0000 0x1000>;
2129                                 status = "disabled";
2130                         };
2131
2132                         frame@98c0000 {
2133                                 frame-number = <6>;
2134                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
2135                                 reg = <0x098c0000 0x1000>;
2136                                 status = "disabled";
2137                         };
2138                 };
2139
2140                 saw3: syscon@9a10000 {
2141                         compatible = "syscon";
2142                         reg = <0x09a10000 0x1000>;
2143                 };
2144
2145                 intc: interrupt-controller@9bc0000 {
2146                         compatible = "qcom,msm8996-gic-v3", "arm,gic-v3";
2147                         #interrupt-cells = <3>;
2148                         interrupt-controller;
2149                         #redistributor-regions = <1>;
2150                         redistributor-stride = <0x0 0x40000>;
2151                         reg = <0x09bc0000 0x10000>,
2152                               <0x09c00000 0x100000>;
2153                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
2154                 };
2155         };
2156
2157         sound: sound {
2158         };
2159
2160         thermal-zones {
2161                 cpu0-thermal {
2162                         polling-delay-passive = <250>;
2163                         polling-delay = <1000>;
2164
2165                         thermal-sensors = <&tsens0 3>;
2166
2167                         trips {
2168                                 cpu0_alert0: trip-point@0 {
2169                                         temperature = <75000>;
2170                                         hysteresis = <2000>;
2171                                         type = "passive";
2172                                 };
2173
2174                                 cpu0_crit: cpu_crit {
2175                                         temperature = <110000>;
2176                                         hysteresis = <2000>;
2177                                         type = "critical";
2178                                 };
2179                         };
2180                 };
2181
2182                 cpu1-thermal {
2183                         polling-delay-passive = <250>;
2184                         polling-delay = <1000>;
2185
2186                         thermal-sensors = <&tsens0 5>;
2187
2188                         trips {
2189                                 cpu1_alert0: trip-point@0 {
2190                                         temperature = <75000>;
2191                                         hysteresis = <2000>;
2192                                         type = "passive";
2193                                 };
2194
2195                                 cpu1_crit: cpu_crit {
2196                                         temperature = <110000>;
2197                                         hysteresis = <2000>;
2198                                         type = "critical";
2199                                 };
2200                         };
2201                 };
2202
2203                 cpu2-thermal {
2204                         polling-delay-passive = <250>;
2205                         polling-delay = <1000>;
2206
2207                         thermal-sensors = <&tsens0 8>;
2208
2209                         trips {
2210                                 cpu2_alert0: trip-point@0 {
2211                                         temperature = <75000>;
2212                                         hysteresis = <2000>;
2213                                         type = "passive";
2214                                 };
2215
2216                                 cpu2_crit: cpu_crit {
2217                                         temperature = <110000>;
2218                                         hysteresis = <2000>;
2219                                         type = "critical";
2220                                 };
2221                         };
2222                 };
2223
2224                 cpu3-thermal {
2225                         polling-delay-passive = <250>;
2226                         polling-delay = <1000>;
2227
2228                         thermal-sensors = <&tsens0 10>;
2229
2230                         trips {
2231                                 cpu3_alert0: trip-point@0 {
2232                                         temperature = <75000>;
2233                                         hysteresis = <2000>;
2234                                         type = "passive";
2235                                 };
2236
2237                                 cpu3_crit: cpu_crit {
2238                                         temperature = <110000>;
2239                                         hysteresis = <2000>;
2240                                         type = "critical";
2241                                 };
2242                         };
2243                 };
2244
2245                 gpu-thermal-top {
2246                         polling-delay-passive = <250>;
2247                         polling-delay = <1000>;
2248
2249                         thermal-sensors = <&tsens1 6>;
2250
2251                         trips {
2252                                 gpu1_alert0: trip-point@0 {
2253                                         temperature = <90000>;
2254                                         hysteresis = <2000>;
2255                                         type = "hot";
2256                                 };
2257                         };
2258                 };
2259
2260                 gpu-thermal-bottom {
2261                         polling-delay-passive = <250>;
2262                         polling-delay = <1000>;
2263
2264                         thermal-sensors = <&tsens1 7>;
2265
2266                         trips {
2267                                 gpu2_alert0: trip-point@0 {
2268                                         temperature = <90000>;
2269                                         hysteresis = <2000>;
2270                                         type = "hot";
2271                                 };
2272                         };
2273                 };
2274
2275                 m4m-thermal {
2276                         polling-delay-passive = <250>;
2277                         polling-delay = <1000>;
2278
2279                         thermal-sensors = <&tsens0 1>;
2280
2281                         trips {
2282                                 m4m_alert0: trip-point@0 {
2283                                         temperature = <90000>;
2284                                         hysteresis = <2000>;
2285                                         type = "hot";
2286                                 };
2287                         };
2288                 };
2289
2290                 l3-or-venus-thermal {
2291                         polling-delay-passive = <250>;
2292                         polling-delay = <1000>;
2293
2294                         thermal-sensors = <&tsens0 2>;
2295
2296                         trips {
2297                                 l3_or_venus_alert0: trip-point@0 {
2298                                         temperature = <90000>;
2299                                         hysteresis = <2000>;
2300                                         type = "hot";
2301                                 };
2302                         };
2303                 };
2304
2305                 cluster0-l2-thermal {
2306                         polling-delay-passive = <250>;
2307                         polling-delay = <1000>;
2308
2309                         thermal-sensors = <&tsens0 7>;
2310
2311                         trips {
2312                                 cluster0_l2_alert0: trip-point@0 {
2313                                         temperature = <90000>;
2314                                         hysteresis = <2000>;
2315                                         type = "hot";
2316                                 };
2317                         };
2318                 };
2319
2320                 cluster1-l2-thermal {
2321                         polling-delay-passive = <250>;
2322                         polling-delay = <1000>;
2323
2324                         thermal-sensors = <&tsens0 12>;
2325
2326                         trips {
2327                                 cluster1_l2_alert0: trip-point@0 {
2328                                         temperature = <90000>;
2329                                         hysteresis = <2000>;
2330                                         type = "hot";
2331                                 };
2332                         };
2333                 };
2334
2335                 camera-thermal {
2336                         polling-delay-passive = <250>;
2337                         polling-delay = <1000>;
2338
2339                         thermal-sensors = <&tsens1 1>;
2340
2341                         trips {
2342                                 camera_alert0: trip-point@0 {
2343                                         temperature = <90000>;
2344                                         hysteresis = <2000>;
2345                                         type = "hot";
2346                                 };
2347                         };
2348                 };
2349
2350                 q6-dsp-thermal {
2351                         polling-delay-passive = <250>;
2352                         polling-delay = <1000>;
2353
2354                         thermal-sensors = <&tsens1 2>;
2355
2356                         trips {
2357                                 q6_dsp_alert0: trip-point@0 {
2358                                         temperature = <90000>;
2359                                         hysteresis = <2000>;
2360                                         type = "hot";
2361                                 };
2362                         };
2363                 };
2364
2365                 mem-thermal {
2366                         polling-delay-passive = <250>;
2367                         polling-delay = <1000>;
2368
2369                         thermal-sensors = <&tsens1 3>;
2370
2371                         trips {
2372                                 mem_alert0: trip-point@0 {
2373                                         temperature = <90000>;
2374                                         hysteresis = <2000>;
2375                                         type = "hot";
2376                                 };
2377                         };
2378                 };
2379
2380                 modemtx-thermal {
2381                         polling-delay-passive = <250>;
2382                         polling-delay = <1000>;
2383
2384                         thermal-sensors = <&tsens1 4>;
2385
2386                         trips {
2387                                 modemtx_alert0: trip-point@0 {
2388                                         temperature = <90000>;
2389                                         hysteresis = <2000>;
2390                                         type = "hot";
2391                                 };
2392                         };
2393                 };
2394         };
2395
2396         timer {
2397                 compatible = "arm,armv8-timer";
2398                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
2399                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
2400                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
2401                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
2402         };
2403 };
2404 #include "msm8996-pins.dtsi"