1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/soc/qcom,apr.h>
12 interrupt-parent = <&intc>;
21 compatible = "fixed-clock";
23 clock-frequency = <19200000>;
24 clock-output-names = "xo_board";
27 sleep_clk: sleep_clk {
28 compatible = "fixed-clock";
30 clock-frequency = <32764>;
31 clock-output-names = "sleep_clk";
41 compatible = "qcom,kryo";
43 enable-method = "psci";
44 cpu-idle-states = <&CPU_SLEEP_0>;
45 capacity-dmips-mhz = <1024>;
46 next-level-cache = <&L2_0>;
55 compatible = "qcom,kryo";
57 enable-method = "psci";
58 cpu-idle-states = <&CPU_SLEEP_0>;
59 capacity-dmips-mhz = <1024>;
60 next-level-cache = <&L2_0>;
65 compatible = "qcom,kryo";
67 enable-method = "psci";
68 cpu-idle-states = <&CPU_SLEEP_0>;
69 capacity-dmips-mhz = <1024>;
70 next-level-cache = <&L2_1>;
79 compatible = "qcom,kryo";
81 enable-method = "psci";
82 cpu-idle-states = <&CPU_SLEEP_0>;
83 capacity-dmips-mhz = <1024>;
84 next-level-cache = <&L2_1>;
110 entry-method = "psci";
112 CPU_SLEEP_0: cpu-sleep-0 {
113 compatible = "arm,idle-state";
114 idle-state-name = "standalone-power-collapse";
115 arm,psci-suspend-param = <0x00000004>;
116 entry-latency-us = <130>;
117 exit-latency-us = <80>;
118 min-residency-us = <300>;
125 compatible = "qcom,scm-msm8996";
126 qcom,dload-mode = <&tcsr 0x13000>;
131 compatible = "qcom,tcsr-mutex";
132 syscon = <&tcsr_mutex_regs 0 0x1000>;
137 device_type = "memory";
138 /* We expect the bootloader to fill in the reg */
143 compatible = "arm,psci-1.0";
148 #address-cells = <2>;
152 mba_region: mba@91500000 {
153 reg = <0x0 0x91500000 0x0 0x200000>;
157 slpi_region: slpi@90b00000 {
158 reg = <0x0 0x90b00000 0x0 0xa00000>;
162 venus_region: venus@90400000 {
163 reg = <0x0 0x90400000 0x0 0x700000>;
167 adsp_region: adsp@8ea00000 {
168 reg = <0x0 0x8ea00000 0x0 0x1a00000>;
172 mpss_region: mpss@88800000 {
173 reg = <0x0 0x88800000 0x0 0x6200000>;
177 smem_mem: smem-mem@86000000 {
178 reg = <0x0 0x86000000 0x0 0x200000>;
183 reg = <0x0 0x85800000 0x0 0x800000>;
188 reg = <0x0 0x86200000 0x0 0x2600000>;
193 compatible = "qcom,rmtfs-mem";
195 size = <0x0 0x200000>;
196 alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
199 qcom,client-id = <1>;
203 zap_shader_region: gpu@8f200000 {
204 compatible = "shared-dma-pool";
205 reg = <0x0 0x90b00000 0x0 0xa00000>;
211 compatible = "qcom,glink-rpm";
213 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
215 qcom,rpm-msg-ram = <&rpm_msg_ram>;
217 mboxes = <&apcs_glb 0>;
219 rpm_requests: rpm-requests {
220 compatible = "qcom,rpm-msm8996";
221 qcom,glink-channels = "rpm_requests";
224 compatible = "qcom,rpmcc-msm8996";
228 rpmpd: power-controller {
229 compatible = "qcom,msm8996-rpmpd";
230 #power-domain-cells = <1>;
231 operating-points-v2 = <&rpmpd_opp_table>;
233 rpmpd_opp_table: opp-table {
234 compatible = "operating-points-v2";
265 compatible = "qcom,smem";
266 memory-region = <&smem_mem>;
267 hwlocks = <&tcsr_mutex 3>;
271 compatible = "qcom,smp2p";
272 qcom,smem = <443>, <429>;
274 interrupts = <0 158 IRQ_TYPE_EDGE_RISING>;
276 mboxes = <&apcs_glb 10>;
278 qcom,local-pid = <0>;
279 qcom,remote-pid = <2>;
281 smp2p_adsp_out: master-kernel {
282 qcom,entry-name = "master-kernel";
283 #qcom,smem-state-cells = <1>;
286 smp2p_adsp_in: slave-kernel {
287 qcom,entry-name = "slave-kernel";
289 interrupt-controller;
290 #interrupt-cells = <2>;
295 compatible = "qcom,smp2p";
296 qcom,smem = <435>, <428>;
298 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
300 mboxes = <&apcs_glb 14>;
302 qcom,local-pid = <0>;
303 qcom,remote-pid = <1>;
305 modem_smp2p_out: master-kernel {
306 qcom,entry-name = "master-kernel";
307 #qcom,smem-state-cells = <1>;
310 modem_smp2p_in: slave-kernel {
311 qcom,entry-name = "slave-kernel";
313 interrupt-controller;
314 #interrupt-cells = <2>;
319 compatible = "qcom,smp2p";
320 qcom,smem = <481>, <430>;
322 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
324 mboxes = <&apcs_glb 26>;
326 qcom,local-pid = <0>;
327 qcom,remote-pid = <3>;
329 smp2p_slpi_in: slave-kernel {
330 qcom,entry-name = "slave-kernel";
331 interrupt-controller;
332 #interrupt-cells = <2>;
335 smp2p_slpi_out: master-kernel {
336 qcom,entry-name = "master-kernel";
337 #qcom,smem-state-cells = <1>;
342 #address-cells = <1>;
344 ranges = <0 0 0 0xffffffff>;
345 compatible = "simple-bus";
347 pcie_phy: phy@34000 {
348 compatible = "qcom,msm8996-qmp-pcie-phy";
349 reg = <0x00034000 0x488>;
351 #address-cells = <1>;
355 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
356 <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
357 <&gcc GCC_PCIE_CLKREF_CLK>;
358 clock-names = "aux", "cfg_ahb", "ref";
360 resets = <&gcc GCC_PCIE_PHY_BCR>,
361 <&gcc GCC_PCIE_PHY_COM_BCR>,
362 <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
363 reset-names = "phy", "common", "cfg";
366 pciephy_0: lane@35000 {
367 reg = <0x00035000 0x130>,
372 clock-output-names = "pcie_0_pipe_clk_src";
373 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
374 clock-names = "pipe0";
375 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
376 reset-names = "lane0";
379 pciephy_1: lane@36000 {
380 reg = <0x00036000 0x130>,
385 clock-output-names = "pcie_1_pipe_clk_src";
386 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
387 clock-names = "pipe1";
388 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
389 reset-names = "lane1";
392 pciephy_2: lane@37000 {
393 reg = <0x00037000 0x130>,
398 clock-output-names = "pcie_2_pipe_clk_src";
399 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
400 clock-names = "pipe2";
401 resets = <&gcc GCC_PCIE_2_PHY_BCR>;
402 reset-names = "lane2";
406 rpm_msg_ram: memory@68000 {
407 compatible = "qcom,rpm-msg-ram";
408 reg = <0x00068000 0x6000>;
412 compatible = "qcom,qfprom";
413 reg = <0x00074000 0x8ff>;
414 #address-cells = <1>;
417 qusb2p_hstx_trim: hstx_trim@24e {
422 qusb2s_hstx_trim: hstx_trim@24f {
427 gpu_speed_bin: gpu_speed_bin@133 {
434 compatible = "qcom,prng-ee";
435 reg = <0x00083000 0x1000>;
436 clocks = <&gcc GCC_PRNG_AHB_CLK>;
437 clock-names = "core";
440 gcc: clock-controller@300000 {
441 compatible = "qcom,gcc-msm8996";
444 #power-domain-cells = <1>;
445 reg = <0x00300000 0x90000>;
447 clocks = <&rpmcc RPM_SMD_LN_BB_CLK>;
448 clock-names = "cxo2";
451 tsens0: thermal-sensor@4a9000 {
452 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
453 reg = <0x004a9000 0x1000>, /* TM */
454 <0x004a8000 0x1000>; /* SROT */
455 #qcom,sensors = <13>;
456 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
457 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
458 interrupt-names = "uplow", "critical";
459 #thermal-sensor-cells = <1>;
462 tsens1: thermal-sensor@4ad000 {
463 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
464 reg = <0x004ad000 0x1000>, /* TM */
465 <0x004ac000 0x1000>; /* SROT */
467 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
468 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
469 interrupt-names = "uplow", "critical";
470 #thermal-sensor-cells = <1>;
473 tcsr_mutex_regs: syscon@740000 {
474 compatible = "syscon";
475 reg = <0x00740000 0x20000>;
478 tcsr: syscon@7a0000 {
479 compatible = "qcom,tcsr-msm8996", "syscon";
480 reg = <0x007a0000 0x18000>;
483 mmcc: clock-controller@8c0000 {
484 compatible = "qcom,mmcc-msm8996";
487 #power-domain-cells = <1>;
488 reg = <0x008c0000 0x40000>;
489 assigned-clocks = <&mmcc MMPLL9_PLL>,
494 assigned-clock-rates = <624000000>,
502 compatible = "qcom,mdss";
504 reg = <0x00900000 0x1000>,
507 reg-names = "mdss_phys",
511 power-domains = <&mmcc MDSS_GDSC>;
512 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
514 interrupt-controller;
515 #interrupt-cells = <1>;
517 clocks = <&mmcc MDSS_AHB_CLK>;
518 clock-names = "iface";
520 #address-cells = <1>;
525 compatible = "qcom,mdp5";
526 reg = <0x00901000 0x90000>;
527 reg-names = "mdp_phys";
529 interrupt-parent = <&mdss>;
530 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
532 clocks = <&mmcc MDSS_AHB_CLK>,
533 <&mmcc MDSS_AXI_CLK>,
534 <&mmcc MDSS_MDP_CLK>,
535 <&mmcc SMMU_MDP_AXI_CLK>,
536 <&mmcc MDSS_VSYNC_CLK>;
537 clock-names = "iface",
543 iommus = <&mdp_smmu 0>;
546 #address-cells = <1>;
551 mdp5_intf3_out: endpoint {
552 remote-endpoint = <&hdmi_in>;
558 hdmi: hdmi-tx@9a0000 {
559 compatible = "qcom,hdmi-tx-8996";
560 reg = <0x009a0000 0x50c>,
563 reg-names = "core_physical",
567 interrupt-parent = <&mdss>;
568 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
570 clocks = <&mmcc MDSS_MDP_CLK>,
571 <&mmcc MDSS_AHB_CLK>,
572 <&mmcc MDSS_HDMI_CLK>,
573 <&mmcc MDSS_HDMI_AHB_CLK>,
574 <&mmcc MDSS_EXTPCLK_CLK>;
583 phy-names = "hdmi_phy";
584 #sound-dai-cells = <1>;
587 #address-cells = <1>;
593 remote-endpoint = <&mdp5_intf3_out>;
599 hdmi_phy: hdmi-phy@9a0600 {
601 compatible = "qcom,hdmi-phy-8996";
602 reg = <0x009a0600 0x1c4>,
608 reg-names = "hdmi_pll",
615 clocks = <&mmcc MDSS_AHB_CLK>,
616 <&gcc GCC_HDMI_CLKREF_CLK>;
617 clock-names = "iface",
622 compatible = "qcom,adreno-530.2", "qcom,adreno";
623 #stream-id-cells = <16>;
625 reg = <0x00b00000 0x3f000>;
626 reg-names = "kgsl_3d0_reg_memory";
628 interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
630 clocks = <&mmcc GPU_GX_GFX3D_CLK>,
632 <&mmcc GPU_GX_RBBMTIMER_CLK>,
633 <&gcc GCC_BIMC_GFX_CLK>,
634 <&gcc GCC_MMSS_BIMC_GFX_CLK>;
636 clock-names = "core",
642 power-domains = <&mmcc GPU_GX_GDSC>;
643 iommus = <&adreno_smmu 0>;
645 nvmem-cells = <&gpu_speed_bin>;
646 nvmem-cell-names = "speed_bin";
648 qcom,gpu-quirk-two-pass-use-wfi;
649 qcom,gpu-quirk-fault-detect-mask;
651 operating-points-v2 = <&gpu_opp_table>;
653 gpu_opp_table: opp-table {
654 compatible ="operating-points-v2";
657 * 624Mhz and 560Mhz are only available on speed
658 * bin (1 << 0). All the rest are available on
659 * all bins of the hardware
662 opp-hz = /bits/ 64 <624000000>;
663 opp-supported-hw = <0x01>;
666 opp-hz = /bits/ 64 <560000000>;
667 opp-supported-hw = <0x01>;
670 opp-hz = /bits/ 64 <510000000>;
671 opp-supported-hw = <0xFF>;
674 opp-hz = /bits/ 64 <401800000>;
675 opp-supported-hw = <0xFF>;
678 opp-hz = /bits/ 64 <315000000>;
679 opp-supported-hw = <0xFF>;
682 opp-hz = /bits/ 64 <214000000>;
683 opp-supported-hw = <0xFF>;
686 opp-hz = /bits/ 64 <133000000>;
687 opp-supported-hw = <0xFF>;
692 memory-region = <&zap_shader_region>;
696 msmgpio: pinctrl@1010000 {
697 compatible = "qcom,msm8996-pinctrl";
698 reg = <0x01010000 0x300000>;
699 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
701 gpio-ranges = <&msmgpio 0 0 150>;
703 interrupt-controller;
704 #interrupt-cells = <2>;
707 spmi_bus: qcom,spmi@400f000 {
708 compatible = "qcom,spmi-pmic-arb";
709 reg = <0x0400f000 0x1000>,
710 <0x04400000 0x800000>,
711 <0x04c00000 0x800000>,
712 <0x05800000 0x200000>,
713 <0x0400a000 0x002100>;
714 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
715 interrupt-names = "periph_irq";
716 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
719 #address-cells = <2>;
721 interrupt-controller;
722 #interrupt-cells = <4>;
726 power-domains = <&gcc AGGRE0_NOC_GDSC>;
727 compatible = "simple-pm-bus";
728 #address-cells = <1>;
733 compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
735 power-domains = <&gcc PCIE0_GDSC>;
736 bus-range = <0x00 0xff>;
739 reg = <0x00600000 0x2000>,
742 <0x0c100000 0x100000>;
743 reg-names = "parf", "dbi", "elbi","config";
746 phy-names = "pciephy";
748 #address-cells = <3>;
750 ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>,
751 <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
753 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
754 interrupt-names = "msi";
755 #interrupt-cells = <1>;
756 interrupt-map-mask = <0 0 0 0x7>;
757 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
758 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
759 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
760 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
762 pinctrl-names = "default", "sleep";
763 pinctrl-0 = <&pcie0_clkreq_default &pcie0_perst_default &pcie0_wake_default>;
764 pinctrl-1 = <&pcie0_clkreq_sleep &pcie0_perst_default &pcie0_wake_sleep>;
766 linux,pci-domain = <0>;
768 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
769 <&gcc GCC_PCIE_0_AUX_CLK>,
770 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
771 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
772 <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
774 clock-names = "pipe",
783 compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
784 power-domains = <&gcc PCIE1_GDSC>;
785 bus-range = <0x00 0xff>;
790 reg = <0x00608000 0x2000>,
793 <0x0d100000 0x100000>;
795 reg-names = "parf", "dbi", "elbi","config";
798 phy-names = "pciephy";
800 #address-cells = <3>;
802 ranges = <0x01000000 0x0 0x0d200000 0x0d200000 0x0 0x100000>,
803 <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>;
805 interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
806 interrupt-names = "msi";
807 #interrupt-cells = <1>;
808 interrupt-map-mask = <0 0 0 0x7>;
809 interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
810 <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
811 <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
812 <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
814 pinctrl-names = "default", "sleep";
815 pinctrl-0 = <&pcie1_clkreq_default &pcie1_perst_default &pcie1_wake_default>;
816 pinctrl-1 = <&pcie1_clkreq_sleep &pcie1_perst_default &pcie1_wake_sleep>;
818 linux,pci-domain = <1>;
820 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
821 <&gcc GCC_PCIE_1_AUX_CLK>,
822 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
823 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
824 <&gcc GCC_PCIE_1_SLV_AXI_CLK>;
826 clock-names = "pipe",
834 compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
835 power-domains = <&gcc PCIE2_GDSC>;
836 bus-range = <0x00 0xff>;
839 reg = <0x00610000 0x2000>,
842 <0x0e100000 0x100000>;
844 reg-names = "parf", "dbi", "elbi","config";
847 phy-names = "pciephy";
849 #address-cells = <3>;
851 ranges = <0x01000000 0x0 0x0e200000 0x0e200000 0x0 0x100000>,
852 <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>;
856 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
857 interrupt-names = "msi";
858 #interrupt-cells = <1>;
859 interrupt-map-mask = <0 0 0 0x7>;
860 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
861 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
862 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
863 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
865 pinctrl-names = "default", "sleep";
866 pinctrl-0 = <&pcie2_clkreq_default &pcie2_perst_default &pcie2_wake_default>;
867 pinctrl-1 = <&pcie2_clkreq_sleep &pcie2_perst_default &pcie2_wake_sleep >;
869 linux,pci-domain = <2>;
870 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
871 <&gcc GCC_PCIE_2_AUX_CLK>,
872 <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
873 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
874 <&gcc GCC_PCIE_2_SLV_AXI_CLK>;
876 clock-names = "pipe",
884 ufshc: ufshc@624000 {
885 compatible = "qcom,ufshc";
886 reg = <0x00624000 0x2500>;
887 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
889 phys = <&ufsphy_lane>;
890 phy-names = "ufsphy";
892 power-domains = <&gcc UFS_GDSC>;
900 "core_clk_unipro_src",
907 <&gcc UFS_AXI_CLK_SRC>,
908 <&gcc GCC_UFS_AXI_CLK>,
909 <&gcc GCC_SYS_NOC_UFS_AXI_CLK>,
910 <&gcc GCC_AGGRE2_UFS_AXI_CLK>,
911 <&gcc GCC_UFS_AHB_CLK>,
912 <&gcc UFS_ICE_CORE_CLK_SRC>,
913 <&gcc GCC_UFS_UNIPRO_CORE_CLK>,
914 <&gcc GCC_UFS_ICE_CORE_CLK>,
915 <&rpmcc RPM_SMD_LN_BB_CLK>,
916 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
917 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>;
919 <100000000 200000000>,
924 <150000000 300000000>,
931 lanes-per-direction = <1>;
936 compatible = "qcom,ufs_variant";
941 compatible = "qcom,msm8996-qmp-ufs-phy";
942 reg = <0x00627000 0x1c4>;
943 #address-cells = <1>;
947 clocks = <&gcc GCC_UFS_CLKREF_CLK>;
951 reset-names = "ufsphy";
954 ufsphy_lane: lanes@627400 {
955 reg = <0x627400 0x12c>,
962 camss: camss@a00000 {
963 compatible = "qcom,msm8996-camss";
964 reg = <0x00a34000 0x1000>,
978 reg-names = "csiphy0",
992 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
993 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
994 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
995 <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
996 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
997 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
998 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
999 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>,
1000 <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
1001 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>;
1002 interrupt-names = "csiphy0",
1012 power-domains = <&mmcc VFE0_GDSC>;
1013 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
1014 <&mmcc CAMSS_ISPIF_AHB_CLK>,
1015 <&mmcc CAMSS_CSI0PHYTIMER_CLK>,
1016 <&mmcc CAMSS_CSI1PHYTIMER_CLK>,
1017 <&mmcc CAMSS_CSI2PHYTIMER_CLK>,
1018 <&mmcc CAMSS_CSI0_AHB_CLK>,
1019 <&mmcc CAMSS_CSI0_CLK>,
1020 <&mmcc CAMSS_CSI0PHY_CLK>,
1021 <&mmcc CAMSS_CSI0PIX_CLK>,
1022 <&mmcc CAMSS_CSI0RDI_CLK>,
1023 <&mmcc CAMSS_CSI1_AHB_CLK>,
1024 <&mmcc CAMSS_CSI1_CLK>,
1025 <&mmcc CAMSS_CSI1PHY_CLK>,
1026 <&mmcc CAMSS_CSI1PIX_CLK>,
1027 <&mmcc CAMSS_CSI1RDI_CLK>,
1028 <&mmcc CAMSS_CSI2_AHB_CLK>,
1029 <&mmcc CAMSS_CSI2_CLK>,
1030 <&mmcc CAMSS_CSI2PHY_CLK>,
1031 <&mmcc CAMSS_CSI2PIX_CLK>,
1032 <&mmcc CAMSS_CSI2RDI_CLK>,
1033 <&mmcc CAMSS_CSI3_AHB_CLK>,
1034 <&mmcc CAMSS_CSI3_CLK>,
1035 <&mmcc CAMSS_CSI3PHY_CLK>,
1036 <&mmcc CAMSS_CSI3PIX_CLK>,
1037 <&mmcc CAMSS_CSI3RDI_CLK>,
1038 <&mmcc CAMSS_AHB_CLK>,
1039 <&mmcc CAMSS_VFE0_CLK>,
1040 <&mmcc CAMSS_CSI_VFE0_CLK>,
1041 <&mmcc CAMSS_VFE0_AHB_CLK>,
1042 <&mmcc CAMSS_VFE0_STREAM_CLK>,
1043 <&mmcc CAMSS_VFE1_CLK>,
1044 <&mmcc CAMSS_CSI_VFE1_CLK>,
1045 <&mmcc CAMSS_VFE1_AHB_CLK>,
1046 <&mmcc CAMSS_VFE1_STREAM_CLK>,
1047 <&mmcc CAMSS_VFE_AHB_CLK>,
1048 <&mmcc CAMSS_VFE_AXI_CLK>;
1049 clock-names = "top_ahb",
1085 iommus = <&vfe_smmu 0>,
1089 status = "disabled";
1091 #address-cells = <1>;
1097 compatible = "qcom,msm8996-cci";
1098 #address-cells = <1>;
1100 reg = <0xa0c000 0x1000>;
1101 interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>;
1102 power-domains = <&mmcc CAMSS_GDSC>;
1103 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
1104 <&mmcc CAMSS_CCI_AHB_CLK>,
1105 <&mmcc CAMSS_CCI_CLK>,
1106 <&mmcc CAMSS_AHB_CLK>;
1107 clock-names = "camss_top_ahb",
1111 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>,
1112 <&mmcc CAMSS_CCI_CLK>;
1113 assigned-clock-rates = <80000000>, <37500000>;
1114 pinctrl-names = "default";
1115 pinctrl-0 = <&cci0_default &cci1_default>;
1116 status = "disabled";
1118 cci_i2c0: i2c-bus@0 {
1120 clock-frequency = <400000>;
1121 #address-cells = <1>;
1125 cci_i2c1: i2c-bus@1 {
1127 clock-frequency = <400000>;
1128 #address-cells = <1>;
1133 adreno_smmu: iommu@b40000 {
1134 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
1135 reg = <0x00b40000 0x10000>;
1137 #global-interrupts = <1>;
1138 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1139 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1140 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
1143 clocks = <&mmcc GPU_AHB_CLK>,
1144 <&gcc GCC_MMSS_BIMC_GFX_CLK>;
1145 clock-names = "iface", "bus";
1147 power-domains = <&mmcc GPU_GDSC>;
1150 video-codec@c00000 {
1151 compatible = "qcom,msm8996-venus";
1152 reg = <0x00c00000 0xff000>;
1153 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
1154 power-domains = <&mmcc VENUS_GDSC>;
1155 clocks = <&mmcc VIDEO_CORE_CLK>,
1156 <&mmcc VIDEO_AHB_CLK>,
1157 <&mmcc VIDEO_AXI_CLK>,
1158 <&mmcc VIDEO_MAXI_CLK>;
1159 clock-names = "core", "iface", "bus", "mbus";
1160 iommus = <&venus_smmu 0x00>,
1180 memory-region = <&venus_region>;
1184 compatible = "venus-decoder";
1185 clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
1186 clock-names = "core";
1187 power-domains = <&mmcc VENUS_CORE0_GDSC>;
1191 compatible = "venus-encoder";
1192 clocks = <&mmcc VIDEO_SUBCORE1_CLK>;
1193 clock-names = "core";
1194 power-domains = <&mmcc VENUS_CORE1_GDSC>;
1198 mdp_smmu: iommu@d00000 {
1199 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
1200 reg = <0x00d00000 0x10000>;
1202 #global-interrupts = <1>;
1203 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1204 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
1205 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
1207 clocks = <&mmcc SMMU_MDP_AHB_CLK>,
1208 <&mmcc SMMU_MDP_AXI_CLK>;
1209 clock-names = "iface", "bus";
1211 power-domains = <&mmcc MDSS_GDSC>;
1214 venus_smmu: iommu@d40000 {
1215 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
1216 reg = <0x00d40000 0x20000>;
1217 #global-interrupts = <1>;
1218 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
1219 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1220 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1221 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
1222 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
1223 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
1224 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
1225 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
1226 power-domains = <&mmcc MMAGIC_VIDEO_GDSC>;
1227 clocks = <&mmcc SMMU_VIDEO_AHB_CLK>,
1228 <&mmcc SMMU_VIDEO_AXI_CLK>;
1229 clock-names = "iface", "bus";
1234 vfe_smmu: iommu@da0000 {
1235 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
1236 reg = <0x00da0000 0x10000>;
1238 #global-interrupts = <1>;
1239 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
1240 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
1241 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1242 power-domains = <&mmcc MMAGIC_CAMSS_GDSC>;
1243 clocks = <&mmcc SMMU_VFE_AHB_CLK>,
1244 <&mmcc SMMU_VFE_AXI_CLK>;
1245 clock-names = "iface",
1250 lpass_q6_smmu: iommu@1600000 {
1251 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
1252 reg = <0x01600000 0x20000>;
1254 power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>;
1256 #global-interrupts = <1>;
1257 interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
1258 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
1259 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
1260 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
1261 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
1262 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
1263 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
1264 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
1265 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
1266 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
1267 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
1268 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
1269 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>;
1271 clocks = <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>,
1272 <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>;
1273 clock-names = "iface", "bus";
1277 compatible = "arm,coresight-stm", "arm,primecell";
1278 reg = <0x3002000 0x1000>,
1279 <0x8280000 0x180000>;
1280 reg-names = "stm-base", "stm-stimulus-base";
1282 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1283 clock-names = "apb_pclk", "atclk";
1296 compatible = "arm,coresight-tpiu", "arm,primecell";
1297 reg = <0x3020000 0x1000>;
1299 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1300 clock-names = "apb_pclk", "atclk";
1313 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1314 reg = <0x3021000 0x1000>;
1316 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1317 clock-names = "apb_pclk", "atclk";
1320 #address-cells = <1>;
1325 funnel0_in: endpoint {
1334 funnel0_out: endpoint {
1336 <&merge_funnel_in0>;
1343 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1344 reg = <0x3022000 0x1000>;
1346 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1347 clock-names = "apb_pclk", "atclk";
1350 #address-cells = <1>;
1355 funnel1_in: endpoint {
1357 <&apss_merge_funnel_out>;
1364 funnel1_out: endpoint {
1366 <&merge_funnel_in1>;
1373 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1374 reg = <0x3023000 0x1000>;
1376 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1377 clock-names = "apb_pclk", "atclk";
1382 funnel2_out: endpoint {
1384 <&merge_funnel_in2>;
1391 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1392 reg = <0x3025000 0x1000>;
1394 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1395 clock-names = "apb_pclk", "atclk";
1398 #address-cells = <1>;
1403 merge_funnel_in0: endpoint {
1411 merge_funnel_in1: endpoint {
1419 merge_funnel_in2: endpoint {
1428 merge_funnel_out: endpoint {
1436 replicator@3026000 {
1437 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
1438 reg = <0x3026000 0x1000>;
1440 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1441 clock-names = "apb_pclk", "atclk";
1445 replicator_in: endpoint {
1453 #address-cells = <1>;
1458 replicator_out0: endpoint {
1466 replicator_out1: endpoint {
1475 compatible = "arm,coresight-tmc", "arm,primecell";
1476 reg = <0x3027000 0x1000>;
1478 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1479 clock-names = "apb_pclk", "atclk";
1485 <&merge_funnel_out>;
1501 compatible = "arm,coresight-tmc", "arm,primecell";
1502 reg = <0x3028000 0x1000>;
1504 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1505 clock-names = "apb_pclk", "atclk";
1519 compatible = "arm,coresight-cpu-debug", "arm,primecell";
1520 reg = <0x3810000 0x1000>;
1522 clocks = <&rpmcc RPM_QDSS_CLK>;
1523 clock-names = "apb_pclk";
1529 compatible = "arm,coresight-etm4x", "arm,primecell";
1530 reg = <0x3840000 0x1000>;
1532 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1533 clock-names = "apb_pclk", "atclk";
1539 etm0_out: endpoint {
1541 <&apss_funnel0_in0>;
1548 compatible = "arm,coresight-cpu-debug", "arm,primecell";
1549 reg = <0x3910000 0x1000>;
1551 clocks = <&rpmcc RPM_QDSS_CLK>;
1552 clock-names = "apb_pclk";
1558 compatible = "arm,coresight-etm4x", "arm,primecell";
1559 reg = <0x3940000 0x1000>;
1561 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1562 clock-names = "apb_pclk", "atclk";
1568 etm1_out: endpoint {
1570 <&apss_funnel0_in1>;
1576 funnel@39b0000 { /* APSS Funnel 0 */
1577 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1578 reg = <0x39b0000 0x1000>;
1580 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1581 clock-names = "apb_pclk", "atclk";
1584 #address-cells = <1>;
1589 apss_funnel0_in0: endpoint {
1590 remote-endpoint = <&etm0_out>;
1596 apss_funnel0_in1: endpoint {
1597 remote-endpoint = <&etm1_out>;
1604 apss_funnel0_out: endpoint {
1606 <&apss_merge_funnel_in0>;
1613 compatible = "arm,coresight-cpu-debug", "arm,primecell";
1614 reg = <0x3a10000 0x1000>;
1616 clocks = <&rpmcc RPM_QDSS_CLK>;
1617 clock-names = "apb_pclk";
1623 compatible = "arm,coresight-etm4x", "arm,primecell";
1624 reg = <0x3a40000 0x1000>;
1626 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1627 clock-names = "apb_pclk", "atclk";
1633 etm2_out: endpoint {
1635 <&apss_funnel1_in0>;
1642 compatible = "arm,coresight-cpu-debug", "arm,primecell";
1643 reg = <0x3b10000 0x1000>;
1645 clocks = <&rpmcc RPM_QDSS_CLK>;
1646 clock-names = "apb_pclk";
1652 compatible = "arm,coresight-etm4x", "arm,primecell";
1653 reg = <0x3b40000 0x1000>;
1655 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1656 clock-names = "apb_pclk", "atclk";
1662 etm3_out: endpoint {
1664 <&apss_funnel1_in1>;
1670 funnel@3bb0000 { /* APSS Funnel 1 */
1671 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1672 reg = <0x3bb0000 0x1000>;
1674 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1675 clock-names = "apb_pclk", "atclk";
1678 #address-cells = <1>;
1683 apss_funnel1_in0: endpoint {
1684 remote-endpoint = <&etm2_out>;
1690 apss_funnel1_in1: endpoint {
1691 remote-endpoint = <&etm3_out>;
1698 apss_funnel1_out: endpoint {
1700 <&apss_merge_funnel_in1>;
1707 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1708 reg = <0x3bc0000 0x1000>;
1710 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1711 clock-names = "apb_pclk", "atclk";
1714 #address-cells = <1>;
1719 apss_merge_funnel_in0: endpoint {
1721 <&apss_funnel0_out>;
1727 apss_merge_funnel_in1: endpoint {
1729 <&apss_funnel1_out>;
1736 apss_merge_funnel_out: endpoint {
1743 kryocc: clock-controller@6400000 {
1744 compatible = "qcom,apcc-msm8996";
1745 reg = <0x06400000 0x90000>;
1750 compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
1751 reg = <0x06af8800 0x400>;
1752 #address-cells = <1>;
1756 clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
1757 <&gcc GCC_USB30_MASTER_CLK>,
1758 <&gcc GCC_AGGRE2_USB3_AXI_CLK>,
1759 <&gcc GCC_USB30_MOCK_UTMI_CLK>,
1760 <&gcc GCC_USB30_SLEEP_CLK>,
1761 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
1763 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
1764 <&gcc GCC_USB30_MASTER_CLK>;
1765 assigned-clock-rates = <19200000>, <120000000>;
1767 power-domains = <&gcc USB30_GDSC>;
1768 status = "disabled";
1771 compatible = "snps,dwc3";
1772 reg = <0x06a00000 0xcc00>;
1773 interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
1774 phys = <&hsusb_phy1>, <&ssusb_phy_0>;
1775 phy-names = "usb2-phy", "usb3-phy";
1776 snps,dis_u2_susphy_quirk;
1777 snps,dis_enblslpm_quirk;
1781 usb3phy: phy@7410000 {
1782 compatible = "qcom,msm8996-qmp-usb3-phy";
1783 reg = <0x07410000 0x1c4>;
1785 #address-cells = <1>;
1789 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
1790 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1791 <&gcc GCC_USB3_CLKREF_CLK>;
1792 clock-names = "aux", "cfg_ahb", "ref";
1794 resets = <&gcc GCC_USB3_PHY_BCR>,
1795 <&gcc GCC_USB3PHY_PHY_BCR>;
1796 reset-names = "phy", "common";
1797 status = "disabled";
1799 ssusb_phy_0: lane@7410200 {
1800 reg = <0x07410200 0x200>,
1805 clock-output-names = "usb3_phy_pipe_clk_src";
1806 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
1807 clock-names = "pipe0";
1811 hsusb_phy1: phy@7411000 {
1812 compatible = "qcom,msm8996-qusb2-phy";
1813 reg = <0x07411000 0x180>;
1816 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1817 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
1818 clock-names = "cfg_ahb", "ref";
1820 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
1821 nvmem-cells = <&qusb2p_hstx_trim>;
1822 status = "disabled";
1825 hsusb_phy2: phy@7412000 {
1826 compatible = "qcom,msm8996-qusb2-phy";
1827 reg = <0x07412000 0x180>;
1830 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1831 <&gcc GCC_RX2_USB2_CLKREF_CLK>;
1832 clock-names = "cfg_ahb", "ref";
1834 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
1835 nvmem-cells = <&qusb2s_hstx_trim>;
1836 status = "disabled";
1839 sdhc2: sdhci@74a4900 {
1840 status = "disabled";
1841 compatible = "qcom,sdhci-msm-v4";
1842 reg = <0x074a4900 0x314>, <0x074a4000 0x800>;
1843 reg-names = "hc_mem", "core_mem";
1845 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>,
1846 <0 221 IRQ_TYPE_LEVEL_HIGH>;
1847 interrupt-names = "hc_irq", "pwr_irq";
1849 clock-names = "iface", "core", "xo";
1850 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
1851 <&gcc GCC_SDCC2_APPS_CLK>,
1856 blsp1_uart1: serial@7570000 {
1857 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1858 reg = <0x07570000 0x1000>;
1859 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1860 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
1861 <&gcc GCC_BLSP1_AHB_CLK>;
1862 clock-names = "core", "iface";
1863 status = "disabled";
1866 blsp1_spi0: spi@7575000 {
1867 compatible = "qcom,spi-qup-v2.2.1";
1868 reg = <0x07575000 0x600>;
1869 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1870 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
1871 <&gcc GCC_BLSP1_AHB_CLK>;
1872 clock-names = "core", "iface";
1873 pinctrl-names = "default", "sleep";
1874 pinctrl-0 = <&blsp1_spi0_default>;
1875 pinctrl-1 = <&blsp1_spi0_sleep>;
1876 #address-cells = <1>;
1878 status = "disabled";
1881 blsp1_i2c2: i2c@7577000 {
1882 compatible = "qcom,i2c-qup-v2.2.1";
1883 reg = <0x07577000 0x1000>;
1884 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1885 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
1886 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
1887 clock-names = "iface", "core";
1888 pinctrl-names = "default", "sleep";
1889 pinctrl-0 = <&blsp1_i2c2_default>;
1890 pinctrl-1 = <&blsp1_i2c2_sleep>;
1891 #address-cells = <1>;
1893 status = "disabled";
1896 blsp2_uart1: serial@75b0000 {
1897 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1898 reg = <0x075b0000 0x1000>;
1899 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
1900 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
1901 <&gcc GCC_BLSP2_AHB_CLK>;
1902 clock-names = "core", "iface";
1903 status = "disabled";
1906 blsp2_uart2: serial@75b1000 {
1907 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1908 reg = <0x075b1000 0x1000>;
1909 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
1910 clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>,
1911 <&gcc GCC_BLSP2_AHB_CLK>;
1912 clock-names = "core", "iface";
1913 status = "disabled";
1916 blsp2_i2c0: i2c@75b5000 {
1917 compatible = "qcom,i2c-qup-v2.2.1";
1918 reg = <0x075b5000 0x1000>;
1919 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1920 clocks = <&gcc GCC_BLSP2_AHB_CLK>,
1921 <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
1922 clock-names = "iface", "core";
1923 pinctrl-names = "default", "sleep";
1924 pinctrl-0 = <&blsp2_i2c0_default>;
1925 pinctrl-1 = <&blsp2_i2c0_sleep>;
1926 #address-cells = <1>;
1928 status = "disabled";
1931 blsp2_i2c1: i2c@75b6000 {
1932 compatible = "qcom,i2c-qup-v2.2.1";
1933 reg = <0x075b6000 0x1000>;
1934 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1935 clocks = <&gcc GCC_BLSP2_AHB_CLK>,
1936 <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>;
1937 clock-names = "iface", "core";
1938 pinctrl-names = "default", "sleep";
1939 pinctrl-0 = <&blsp2_i2c1_default>;
1940 pinctrl-1 = <&blsp2_i2c1_sleep>;
1941 #address-cells = <1>;
1943 status = "disabled";
1946 blsp2_spi5: spi@75ba000{
1947 compatible = "qcom,spi-qup-v2.2.1";
1948 reg = <0x075ba000 0x600>;
1949 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
1950 clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>,
1951 <&gcc GCC_BLSP2_AHB_CLK>;
1952 clock-names = "core", "iface";
1953 pinctrl-names = "default", "sleep";
1954 pinctrl-0 = <&blsp2_spi5_default>;
1955 pinctrl-1 = <&blsp2_spi5_sleep>;
1956 #address-cells = <1>;
1958 status = "disabled";
1962 compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
1963 reg = <0x076f8800 0x400>;
1964 #address-cells = <1>;
1968 clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>,
1969 <&gcc GCC_USB20_MASTER_CLK>,
1970 <&gcc GCC_USB20_MOCK_UTMI_CLK>,
1971 <&gcc GCC_USB20_SLEEP_CLK>,
1972 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
1974 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
1975 <&gcc GCC_USB20_MASTER_CLK>;
1976 assigned-clock-rates = <19200000>, <60000000>;
1978 power-domains = <&gcc USB30_GDSC>;
1979 status = "disabled";
1982 compatible = "snps,dwc3";
1983 reg = <0x07600000 0xcc00>;
1984 interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>;
1985 phys = <&hsusb_phy2>;
1986 phy-names = "usb2-phy";
1987 snps,dis_u2_susphy_quirk;
1988 snps,dis_enblslpm_quirk;
1992 slimbam: dma@9184000 {
1993 compatible = "qcom,bam-v1.7.0";
1994 qcom,controlled-remotely;
1995 reg = <0x09184000 0x32000>;
1996 num-channels = <31>;
1997 interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>;
2003 slim_msm: slim@91c0000 {
2004 compatible = "qcom,slim-ngd-v1.5.0";
2005 reg = <0x091c0000 0x2C000>;
2007 interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>;
2008 dmas = <&slimbam 3>, <&slimbam 4>,
2009 <&slimbam 5>, <&slimbam 6>;
2010 dma-names = "rx", "tx", "tx2", "rx2";
2011 #address-cells = <1>;
2015 #address-cells = <1>;
2018 tasha_ifd: tas-ifd {
2019 compatible = "slim217,1a0";
2024 pinctrl-0 = <&cdc_reset_active &wcd_intr_default>;
2025 pinctrl-names = "default";
2027 compatible = "slim217,1a0";
2030 interrupt-parent = <&msmgpio>;
2031 interrupts = <54 IRQ_TYPE_LEVEL_HIGH>,
2032 <53 IRQ_TYPE_LEVEL_HIGH>;
2033 interrupt-names = "intr1", "intr2";
2034 interrupt-controller;
2035 #interrupt-cells = <1>;
2036 reset-gpios = <&msmgpio 64 0>;
2038 slim-ifc-dev = <&tasha_ifd>;
2040 #sound-dai-cells = <1>;
2045 adsp_pil: remoteproc@9300000 {
2046 compatible = "qcom,msm8996-adsp-pil";
2047 reg = <0x09300000 0x80000>;
2049 interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
2050 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
2051 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
2052 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
2053 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
2054 interrupt-names = "wdog", "fatal", "ready",
2055 "handover", "stop-ack";
2057 clocks = <&xo_board>;
2060 memory-region = <&adsp_region>;
2062 qcom,smem-states = <&smp2p_adsp_out 0>;
2063 qcom,smem-state-names = "stop";
2066 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
2069 mboxes = <&apcs_glb 8>;
2070 qcom,smd-edge = <1>;
2071 qcom,remote-pid = <2>;
2072 #address-cells = <1>;
2075 power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>;
2076 compatible = "qcom,apr-v2";
2077 qcom,smd-channels = "apr_audio_svc";
2078 qcom,apr-domain = <APR_DOMAIN_ADSP>;
2079 #address-cells = <1>;
2083 reg = <APR_SVC_ADSP_CORE>;
2084 compatible = "qcom,q6core";
2088 compatible = "qcom,q6afe";
2089 reg = <APR_SVC_AFE>;
2091 compatible = "qcom,q6afe-dais";
2092 #address-cells = <1>;
2094 #sound-dai-cells = <1>;
2102 compatible = "qcom,q6asm";
2103 reg = <APR_SVC_ASM>;
2105 compatible = "qcom,q6asm-dais";
2106 #address-cells = <1>;
2108 #sound-dai-cells = <1>;
2109 iommus = <&lpass_q6_smmu 1>;
2114 compatible = "qcom,q6adm";
2115 reg = <APR_SVC_ADM>;
2116 q6routing: routing {
2117 compatible = "qcom,q6adm-routing";
2118 #sound-dai-cells = <0>;
2126 apcs_glb: mailbox@9820000 {
2127 compatible = "qcom,msm8996-apcs-hmss-global";
2128 reg = <0x09820000 0x1000>;
2134 #address-cells = <1>;
2137 compatible = "arm,armv7-timer-mem";
2138 reg = <0x09840000 0x1000>;
2139 clock-frequency = <19200000>;
2143 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
2144 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
2145 reg = <0x09850000 0x1000>,
2146 <0x09860000 0x1000>;
2151 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
2152 reg = <0x09870000 0x1000>;
2153 status = "disabled";
2158 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
2159 reg = <0x09880000 0x1000>;
2160 status = "disabled";
2165 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
2166 reg = <0x09890000 0x1000>;
2167 status = "disabled";
2172 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
2173 reg = <0x098a0000 0x1000>;
2174 status = "disabled";
2179 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
2180 reg = <0x098b0000 0x1000>;
2181 status = "disabled";
2186 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
2187 reg = <0x098c0000 0x1000>;
2188 status = "disabled";
2192 saw3: syscon@9a10000 {
2193 compatible = "syscon";
2194 reg = <0x09a10000 0x1000>;
2197 intc: interrupt-controller@9bc0000 {
2198 compatible = "qcom,msm8996-gic-v3", "arm,gic-v3";
2199 #interrupt-cells = <3>;
2200 interrupt-controller;
2201 #redistributor-regions = <1>;
2202 redistributor-stride = <0x0 0x40000>;
2203 reg = <0x09bc0000 0x10000>,
2204 <0x09c00000 0x100000>;
2205 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
2214 polling-delay-passive = <250>;
2215 polling-delay = <1000>;
2217 thermal-sensors = <&tsens0 3>;
2220 cpu0_alert0: trip-point0 {
2221 temperature = <75000>;
2222 hysteresis = <2000>;
2226 cpu0_crit: cpu_crit {
2227 temperature = <110000>;
2228 hysteresis = <2000>;
2235 polling-delay-passive = <250>;
2236 polling-delay = <1000>;
2238 thermal-sensors = <&tsens0 5>;
2241 cpu1_alert0: trip-point0 {
2242 temperature = <75000>;
2243 hysteresis = <2000>;
2247 cpu1_crit: cpu_crit {
2248 temperature = <110000>;
2249 hysteresis = <2000>;
2256 polling-delay-passive = <250>;
2257 polling-delay = <1000>;
2259 thermal-sensors = <&tsens0 8>;
2262 cpu2_alert0: trip-point0 {
2263 temperature = <75000>;
2264 hysteresis = <2000>;
2268 cpu2_crit: cpu_crit {
2269 temperature = <110000>;
2270 hysteresis = <2000>;
2277 polling-delay-passive = <250>;
2278 polling-delay = <1000>;
2280 thermal-sensors = <&tsens0 10>;
2283 cpu3_alert0: trip-point0 {
2284 temperature = <75000>;
2285 hysteresis = <2000>;
2289 cpu3_crit: cpu_crit {
2290 temperature = <110000>;
2291 hysteresis = <2000>;
2298 polling-delay-passive = <250>;
2299 polling-delay = <1000>;
2301 thermal-sensors = <&tsens1 6>;
2304 gpu1_alert0: trip-point0 {
2305 temperature = <90000>;
2306 hysteresis = <2000>;
2312 gpu-thermal-bottom {
2313 polling-delay-passive = <250>;
2314 polling-delay = <1000>;
2316 thermal-sensors = <&tsens1 7>;
2319 gpu2_alert0: trip-point0 {
2320 temperature = <90000>;
2321 hysteresis = <2000>;
2328 polling-delay-passive = <250>;
2329 polling-delay = <1000>;
2331 thermal-sensors = <&tsens0 1>;
2334 m4m_alert0: trip-point0 {
2335 temperature = <90000>;
2336 hysteresis = <2000>;
2342 l3-or-venus-thermal {
2343 polling-delay-passive = <250>;
2344 polling-delay = <1000>;
2346 thermal-sensors = <&tsens0 2>;
2349 l3_or_venus_alert0: trip-point0 {
2350 temperature = <90000>;
2351 hysteresis = <2000>;
2357 cluster0-l2-thermal {
2358 polling-delay-passive = <250>;
2359 polling-delay = <1000>;
2361 thermal-sensors = <&tsens0 7>;
2364 cluster0_l2_alert0: trip-point0 {
2365 temperature = <90000>;
2366 hysteresis = <2000>;
2372 cluster1-l2-thermal {
2373 polling-delay-passive = <250>;
2374 polling-delay = <1000>;
2376 thermal-sensors = <&tsens0 12>;
2379 cluster1_l2_alert0: trip-point0 {
2380 temperature = <90000>;
2381 hysteresis = <2000>;
2388 polling-delay-passive = <250>;
2389 polling-delay = <1000>;
2391 thermal-sensors = <&tsens1 1>;
2394 camera_alert0: trip-point0 {
2395 temperature = <90000>;
2396 hysteresis = <2000>;
2403 polling-delay-passive = <250>;
2404 polling-delay = <1000>;
2406 thermal-sensors = <&tsens1 2>;
2409 q6_dsp_alert0: trip-point0 {
2410 temperature = <90000>;
2411 hysteresis = <2000>;
2418 polling-delay-passive = <250>;
2419 polling-delay = <1000>;
2421 thermal-sensors = <&tsens1 3>;
2424 mem_alert0: trip-point0 {
2425 temperature = <90000>;
2426 hysteresis = <2000>;
2433 polling-delay-passive = <250>;
2434 polling-delay = <1000>;
2436 thermal-sensors = <&tsens1 4>;
2439 modemtx_alert0: trip-point0 {
2440 temperature = <90000>;
2441 hysteresis = <2000>;
2449 compatible = "arm,armv8-timer";
2450 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
2451 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
2452 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
2453 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
2456 #include "msm8996-pins.dtsi"