1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2016, The Linux Foundation. All rights reserved. */
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-msm8998.h>
6 #include <dt-bindings/clock/qcom,rpmcc.h>
7 #include <dt-bindings/gpio/gpio.h>
10 interrupt-parent = <&intc>;
12 qcom,msm-id = <292 0x0>;
20 device_type = "memory";
21 /* We expect the bootloader to fill in the reg */
31 reg = <0x0 0x85800000 0x0 0x800000>;
35 smem_mem: smem-mem@86000000 {
36 reg = <0x0 0x86000000 0x0 0x200000>;
41 reg = <0x0 0x86200000 0x0 0x2d00000>;
46 compatible = "qcom,rmtfs-mem";
48 size = <0x0 0x200000>;
49 alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
59 compatible = "fixed-clock";
61 clock-frequency = <19200000>;
62 clock-output-names = "xo_board";
66 compatible = "fixed-clock";
68 clock-frequency = <32764>;
78 compatible = "arm,armv8";
80 enable-method = "psci";
82 next-level-cache = <&L2_0>;
84 compatible = "arm,arch-cache";
88 compatible = "arm,arch-cache";
91 compatible = "arm,arch-cache";
97 compatible = "arm,armv8";
99 enable-method = "psci";
101 next-level-cache = <&L2_0>;
103 compatible = "arm,arch-cache";
106 compatible = "arm,arch-cache";
112 compatible = "arm,armv8";
114 enable-method = "psci";
116 next-level-cache = <&L2_0>;
118 compatible = "arm,arch-cache";
121 compatible = "arm,arch-cache";
127 compatible = "arm,armv8";
129 enable-method = "psci";
131 next-level-cache = <&L2_0>;
133 compatible = "arm,arch-cache";
136 compatible = "arm,arch-cache";
142 compatible = "arm,armv8";
144 enable-method = "psci";
146 next-level-cache = <&L2_1>;
148 compatible = "arm,arch-cache";
151 L1_I_100: l1-icache {
152 compatible = "arm,arch-cache";
154 L1_D_100: l1-dcache {
155 compatible = "arm,arch-cache";
161 compatible = "arm,armv8";
163 enable-method = "psci";
165 next-level-cache = <&L2_1>;
166 L1_I_101: l1-icache {
167 compatible = "arm,arch-cache";
169 L1_D_101: l1-dcache {
170 compatible = "arm,arch-cache";
176 compatible = "arm,armv8";
178 enable-method = "psci";
180 next-level-cache = <&L2_1>;
181 L1_I_102: l1-icache {
182 compatible = "arm,arch-cache";
184 L1_D_102: l1-dcache {
185 compatible = "arm,arch-cache";
191 compatible = "arm,armv8";
193 enable-method = "psci";
195 next-level-cache = <&L2_1>;
196 L1_I_103: l1-icache {
197 compatible = "arm,arch-cache";
199 L1_D_103: l1-dcache {
200 compatible = "arm,arch-cache";
245 compatible = "qcom,scm-msm8998", "qcom,scm";
250 compatible = "qcom,tcsr-mutex";
251 syscon = <&tcsr_mutex_regs 0 0x1000>;
256 compatible = "arm,psci-1.0";
261 compatible = "qcom,glink-rpm";
263 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
264 qcom,rpm-msg-ram = <&rpm_msg_ram>;
265 mboxes = <&apcs_glb 0>;
267 rpm_requests: rpm-requests {
268 compatible = "qcom,rpm-msm8998";
269 qcom,glink-channels = "rpm_requests";
271 rpmcc: clock-controller {
272 compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc";
279 compatible = "qcom,smem";
280 memory-region = <&smem_mem>;
281 hwlocks = <&tcsr_mutex 3>;
285 compatible = "qcom,smp2p";
286 qcom,smem = <443>, <429>;
288 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
290 mboxes = <&apcs_glb 10>;
292 qcom,local-pid = <0>;
293 qcom,remote-pid = <2>;
295 adsp_smp2p_out: master-kernel {
296 qcom,entry-name = "master-kernel";
297 #qcom,smem-state-cells = <1>;
300 adsp_smp2p_in: slave-kernel {
301 qcom,entry-name = "slave-kernel";
303 interrupt-controller;
304 #interrupt-cells = <2>;
309 compatible = "qcom,smp2p";
310 qcom,smem = <435>, <428>;
311 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
312 mboxes = <&apcs_glb 14>;
313 qcom,local-pid = <0>;
314 qcom,remote-pid = <1>;
316 modem_smp2p_out: master-kernel {
317 qcom,entry-name = "master-kernel";
318 #qcom,smem-state-cells = <1>;
321 modem_smp2p_in: slave-kernel {
322 qcom,entry-name = "slave-kernel";
323 interrupt-controller;
324 #interrupt-cells = <2>;
329 compatible = "qcom,smp2p";
330 qcom,smem = <481>, <430>;
331 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
332 mboxes = <&apcs_glb 26>;
333 qcom,local-pid = <0>;
334 qcom,remote-pid = <3>;
336 slpi_smp2p_out: master-kernel {
337 qcom,entry-name = "master-kernel";
338 #qcom,smem-state-cells = <1>;
341 slpi_smp2p_in: slave-kernel {
342 qcom,entry-name = "slave-kernel";
343 interrupt-controller;
344 #interrupt-cells = <2>;
350 polling-delay-passive = <250>;
351 polling-delay = <1000>;
353 thermal-sensors = <&tsens0 6>;
357 temperature = <75000>;
363 temperature = <110000>;
371 polling-delay-passive = <250>;
372 polling-delay = <1000>;
374 thermal-sensors = <&tsens0 7>;
378 temperature = <75000>;
384 temperature = <110000>;
392 polling-delay-passive = <250>;
393 polling-delay = <1000>;
395 thermal-sensors = <&tsens0 8>;
399 temperature = <75000>;
405 temperature = <110000>;
413 polling-delay-passive = <250>;
414 polling-delay = <1000>;
416 thermal-sensors = <&tsens0 9>;
420 temperature = <75000>;
426 temperature = <110000>;
434 polling-delay-passive = <250>;
435 polling-delay = <1000>;
437 thermal-sensors = <&tsens0 10>;
441 temperature = <75000>;
447 temperature = <110000>;
455 polling-delay-passive = <250>;
456 polling-delay = <1000>;
458 thermal-sensors = <&tsens0 11>;
462 temperature = <75000>;
468 temperature = <110000>;
476 polling-delay-passive = <250>;
477 polling-delay = <1000>;
479 thermal-sensors = <&tsens1 0>;
483 temperature = <75000>;
489 temperature = <110000>;
497 polling-delay-passive = <250>;
498 polling-delay = <1000>;
500 thermal-sensors = <&tsens1 1>;
504 temperature = <75000>;
510 temperature = <110000>;
518 polling-delay-passive = <250>;
519 polling-delay = <1000>;
521 thermal-sensors = <&tsens1 3>;
526 compatible = "arm,armv8-timer";
527 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
528 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
529 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
530 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
534 #address-cells = <1>;
536 ranges = <0 0 0 0xffffffff>;
537 compatible = "simple-bus";
539 rpm_msg_ram: memory@68000 {
540 compatible = "qcom,rpm-msg-ram";
541 reg = <0x778000 0x7000>;
544 qfprom: qfprom@780000 {
545 compatible = "qcom,qfprom";
546 reg = <0x780000 0x621c>;
547 #address-cells = <1>;
550 qusb2_hstx_trim: hstx-trim@423a {
556 gcc: clock-controller@100000 {
557 compatible = "qcom,gcc-msm8998";
560 #power-domain-cells = <1>;
561 reg = <0x100000 0xb0000>;
564 tlmm: pinctrl@3400000 {
565 compatible = "qcom,msm8998-pinctrl";
566 reg = <0x3400000 0xc00000>;
567 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
570 interrupt-controller;
571 #interrupt-cells = <0x2>;
574 spmi_bus: spmi@800f000 {
575 compatible = "qcom,spmi-pmic-arb";
576 reg = <0x800f000 0x1000>,
577 <0x8400000 0x1000000>,
578 <0x9400000 0x1000000>,
579 <0xa400000 0x220000>,
581 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
582 interrupt-names = "periph_irq";
583 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
586 #address-cells = <2>;
588 interrupt-controller;
589 #interrupt-cells = <4>;
593 tsens0: thermal@10aa000 {
594 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
595 reg = <0x10aa000 0x2000>;
597 #qcom,sensors = <12>;
598 #thermal-sensor-cells = <1>;
601 tsens1: thermal@10ad000 {
602 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
603 reg = <0x10ad000 0x2000>;
606 #thermal-sensor-cells = <1>;
609 tcsr_mutex_regs: syscon@1f40000 {
610 compatible = "syscon";
611 reg = <0x1f40000 0x20000>;
614 apcs_glb: mailbox@9820000 {
615 compatible = "qcom,msm8998-apcs-hmss-global";
616 reg = <0x17911000 0x1000>;
622 compatible = "qcom,msm8998-dwc3", "qcom,dwc3";
623 reg = <0x0a8f8800 0x400>;
625 #address-cells = <1>;
629 clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>,
630 <&gcc GCC_USB30_MASTER_CLK>,
631 <&gcc GCC_AGGRE1_USB3_AXI_CLK>,
632 <&gcc GCC_USB30_MOCK_UTMI_CLK>,
633 <&gcc GCC_USB30_SLEEP_CLK>;
634 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
637 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
638 <&gcc GCC_USB30_MASTER_CLK>;
639 assigned-clock-rates = <19200000>, <120000000>;
641 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
642 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
643 interrupt-names = "hs_phy_irq", "ss_phy_irq";
645 power-domains = <&gcc USB_30_GDSC>;
647 resets = <&gcc GCC_USB_30_BCR>;
649 usb3_dwc3: dwc3@a800000 {
650 compatible = "snps,dwc3";
651 reg = <0x0a800000 0xcd00>;
652 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
653 snps,dis_u2_susphy_quirk;
654 snps,dis_enblslpm_quirk;
655 phys = <&qusb2phy>, <&usb1_ssphy>;
656 phy-names = "usb2-phy", "usb3-phy";
657 snps,has-lpm-erratum;
658 snps,hird-threshold = /bits/ 8 <0x10>;
662 usb3phy: phy@c010000 {
663 compatible = "qcom,msm8998-qmp-usb3-phy";
664 reg = <0x0c010000 0x18c>;
667 #address-cells = <1>;
671 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
672 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
673 <&gcc GCC_USB3_CLKREF_CLK>;
674 clock-names = "aux", "cfg_ahb", "ref";
676 resets = <&gcc GCC_USB3_PHY_BCR>,
677 <&gcc GCC_USB3PHY_PHY_BCR>;
678 reset-names = "phy", "common";
680 usb1_ssphy: lane@c010200 {
681 reg = <0xc010200 0x128>,
687 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
688 clock-names = "pipe0";
689 clock-output-names = "usb3_phy_pipe_clk_src";
693 qusb2phy: phy@c012000 {
694 compatible = "qcom,msm8998-qusb2-phy";
695 reg = <0x0c012000 0x2a8>;
699 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
700 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
701 clock-names = "cfg_ahb", "ref";
703 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
705 nvmem-cells = <&qusb2_hstx_trim>;
708 sdhc2: sdhci@c0a4900 {
709 compatible = "qcom,sdhci-msm-v4";
710 reg = <0xc0a4900 0x314>, <0xc0a4000 0x800>;
711 reg-names = "hc_mem", "core_mem";
713 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
714 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
715 interrupt-names = "hc_irq", "pwr_irq";
717 clock-names = "iface", "core", "xo";
718 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
719 <&gcc GCC_SDCC2_APPS_CLK>,
725 blsp1_i2c1: i2c@c175000 {
726 compatible = "qcom,i2c-qup-v2.2.1";
727 reg = <0x0c175000 0x600>;
728 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
730 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
731 <&gcc GCC_BLSP1_AHB_CLK>;
732 clock-names = "core", "iface";
733 clock-frequency = <400000>;
736 #address-cells = <1>;
740 blsp1_i2c2: i2c@c176000 {
741 compatible = "qcom,i2c-qup-v2.2.1";
742 reg = <0x0c176000 0x600>;
743 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
745 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
746 <&gcc GCC_BLSP1_AHB_CLK>;
747 clock-names = "core", "iface";
748 clock-frequency = <400000>;
751 #address-cells = <1>;
755 blsp1_i2c3: i2c@c177000 {
756 compatible = "qcom,i2c-qup-v2.2.1";
757 reg = <0x0c177000 0x600>;
758 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
760 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
761 <&gcc GCC_BLSP1_AHB_CLK>;
762 clock-names = "core", "iface";
763 clock-frequency = <400000>;
766 #address-cells = <1>;
770 blsp1_i2c4: i2c@c178000 {
771 compatible = "qcom,i2c-qup-v2.2.1";
772 reg = <0x0c178000 0x600>;
773 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
775 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
776 <&gcc GCC_BLSP1_AHB_CLK>;
777 clock-names = "core", "iface";
778 clock-frequency = <400000>;
781 #address-cells = <1>;
785 blsp1_i2c5: i2c@c179000 {
786 compatible = "qcom,i2c-qup-v2.2.1";
787 reg = <0x0c179000 0x600>;
788 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
790 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
791 <&gcc GCC_BLSP1_AHB_CLK>;
792 clock-names = "core", "iface";
793 clock-frequency = <400000>;
796 #address-cells = <1>;
800 blsp1_i2c6: i2c@c17a000 {
801 compatible = "qcom,i2c-qup-v2.2.1";
802 reg = <0x0c17a000 0x600>;
803 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
805 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
806 <&gcc GCC_BLSP1_AHB_CLK>;
807 clock-names = "core", "iface";
808 clock-frequency = <400000>;
811 #address-cells = <1>;
815 blsp2_i2c0: i2c@c1b5000 {
816 compatible = "qcom,i2c-qup-v2.2.1";
817 reg = <0x0c1b5000 0x600>;
818 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
820 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
821 <&gcc GCC_BLSP2_AHB_CLK>;
822 clock-names = "core", "iface";
823 clock-frequency = <400000>;
826 #address-cells = <1>;
830 blsp2_i2c1: i2c@c1b6000 {
831 compatible = "qcom,i2c-qup-v2.2.1";
832 reg = <0x0c1b6000 0x600>;
833 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
835 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
836 <&gcc GCC_BLSP2_AHB_CLK>;
837 clock-names = "core", "iface";
838 clock-frequency = <400000>;
841 #address-cells = <1>;
845 blsp2_i2c2: i2c@c1b7000 {
846 compatible = "qcom,i2c-qup-v2.2.1";
847 reg = <0x0c1b7000 0x600>;
848 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
850 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
851 <&gcc GCC_BLSP2_AHB_CLK>;
852 clock-names = "core", "iface";
853 clock-frequency = <400000>;
856 #address-cells = <1>;
860 blsp2_i2c3: i2c@c1b8000 {
861 compatible = "qcom,i2c-qup-v2.2.1";
862 reg = <0x0c1b8000 0x600>;
863 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
865 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>,
866 <&gcc GCC_BLSP2_AHB_CLK>;
867 clock-names = "core", "iface";
868 clock-frequency = <400000>;
871 #address-cells = <1>;
875 blsp2_i2c4: i2c@c1b9000 {
876 compatible = "qcom,i2c-qup-v2.2.1";
877 reg = <0x0c1b9000 0x600>;
878 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
880 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
881 <&gcc GCC_BLSP2_AHB_CLK>;
882 clock-names = "core", "iface";
883 clock-frequency = <400000>;
886 #address-cells = <1>;
890 blsp2_i2c5: i2c@c1ba000 {
891 compatible = "qcom,i2c-qup-v2.2.1";
892 reg = <0x0c175000 0x600>;
893 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
895 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>,
896 <&gcc GCC_BLSP2_AHB_CLK>;
897 clock-names = "core", "iface";
898 clock-frequency = <400000>;
901 #address-cells = <1>;
905 blsp2_uart1: serial@c1b0000 {
906 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
907 reg = <0xc1b0000 0x1000>;
908 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
909 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
910 <&gcc GCC_BLSP2_AHB_CLK>;
911 clock-names = "core", "iface";
916 #address-cells = <1>;
919 compatible = "arm,armv7-timer-mem";
920 reg = <0x17920000 0x1000>;
924 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
925 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
926 reg = <0x17921000 0x1000>,
932 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
933 reg = <0x17923000 0x1000>;
939 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
940 reg = <0x17924000 0x1000>;
946 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
947 reg = <0x17925000 0x1000>;
953 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
954 reg = <0x17926000 0x1000>;
960 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
961 reg = <0x17927000 0x1000>;
967 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
968 reg = <0x17928000 0x1000>;
973 intc: interrupt-controller@17a00000 {
974 compatible = "arm,gic-v3";
975 reg = <0x17a00000 0x10000>, /* GICD */
976 <0x17b00000 0x100000>; /* GICR * 8 */
977 #interrupt-cells = <3>;
978 #address-cells = <1>;
981 interrupt-controller;
982 #redistributor-regions = <1>;
983 redistributor-stride = <0x0 0x20000>;
984 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
989 #include "msm8998-pins.dtsi"