sys/gnu/dts/arm64/qcom/msm8998.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright (c) 2016, The Linux Foundation. All rights reserved. */
   3
   4 #include <dt-bindings/interrupt-controller/arm-gic.h>
   5 #include <dt-bindings/clock/qcom,gcc-msm8998.h>
   6 #include <dt-bindings/clock/qcom,rpmcc.h>
   7 #include <dt-bindings/power/qcom-rpmpd.h>
   8 #include <dt-bindings/gpio/gpio.h>
   9
  10 / {
  11         interrupt-parent = <&intc>;
  12
  13         qcom,msm-id = <292 0x0>;
  14
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         chosen { };
  19
  20         memory {
  21                 device_type = "memory";
  22                 /* We expect the bootloader to fill in the reg */
  23                 reg = <0 0 0 0>;
  24         };
  25
  26         reserved-memory {
  27                 #address-cells = <2>;
  28                 #size-cells = <2>;
  29                 ranges;
  30
  31                 memory@85800000 {
  32                         reg = <0x0 0x85800000 0x0 0x800000>;
  33                         no-map;
  34                 };
  35
  36                 smem_mem: smem-mem@86000000 {
  37                         reg = <0x0 0x86000000 0x0 0x200000>;
  38                         no-map;
  39                 };
  40
  41                 memory@86200000 {
  42                         reg = <0x0 0x86200000 0x0 0x2d00000>;
  43                         no-map;
  44                 };
  45
  46                 rmtfs {
  47                         compatible = "qcom,rmtfs-mem";
  48
  49                         size = <0x0 0x200000>;
  50                         alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
  51                         no-map;
  52
  53                         qcom,client-id = <1>;
  54                         qcom,vmid = <15>;
  55                 };
  56         };
  57
  58         clocks {
  59                 xo: xo-board {
  60                         compatible = "fixed-clock";
  61                         #clock-cells = <0>;
  62                         clock-frequency = <19200000>;
  63                         clock-output-names = "xo_board";
  64                 };
  65
  66                 sleep_clk {
  67                         compatible = "fixed-clock";
  68                         #clock-cells = <0>;
  69                         clock-frequency = <32764>;
  70                 };
  71         };
  72
  73         cpus {
  74                 #address-cells = <2>;
  75                 #size-cells = <0>;
  76
  77                 CPU0: cpu@0 {
  78                         device_type = "cpu";
  79                         compatible = "arm,armv8";
  80                         reg = <0x0 0x0>;
  81                         enable-method = "psci";
  82                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
  83                         next-level-cache = <&L2_0>;
  84                         L2_0: l2-cache {
  85                                 compatible = "arm,arch-cache";
  86                                 cache-level = <2>;
  87                         };
  88                         L1_I_0: l1-icache {
  89                                 compatible = "arm,arch-cache";
  90                         };
  91                         L1_D_0: l1-dcache {
  92                                 compatible = "arm,arch-cache";
  93                         };
  94                 };
  95
  96                 CPU1: cpu@1 {
  97                         device_type = "cpu";
  98                         compatible = "arm,armv8";
  99                         reg = <0x0 0x1>;
 100                         enable-method = "psci";
 101                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
 102                         next-level-cache = <&L2_0>;
 103                         L1_I_1: l1-icache {
 104                                 compatible = "arm,arch-cache";
 105                         };
 106                         L1_D_1: l1-dcache {
 107                                 compatible = "arm,arch-cache";
 108                         };
 109                 };
 110
 111                 CPU2: cpu@2 {
 112                         device_type = "cpu";
 113                         compatible = "arm,armv8";
 114                         reg = <0x0 0x2>;
 115                         enable-method = "psci";
 116                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
 117                         next-level-cache = <&L2_0>;
 118                         L1_I_2: l1-icache {
 119                                 compatible = "arm,arch-cache";
 120                         };
 121                         L1_D_2: l1-dcache {
 122                                 compatible = "arm,arch-cache";
 123                         };
 124                 };
 125
 126                 CPU3: cpu@3 {
 127                         device_type = "cpu";
 128                         compatible = "arm,armv8";
 129                         reg = <0x0 0x3>;
 130                         enable-method = "psci";
 131                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
 132                         next-level-cache = <&L2_0>;
 133                         L1_I_3: l1-icache {
 134                                 compatible = "arm,arch-cache";
 135                         };
 136                         L1_D_3: l1-dcache {
 137                                 compatible = "arm,arch-cache";
 138                         };
 139                 };
 140
 141                 CPU4: cpu@100 {
 142                         device_type = "cpu";
 143                         compatible = "arm,armv8";
 144                         reg = <0x0 0x100>;
 145                         enable-method = "psci";
 146                         cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
 147                         next-level-cache = <&L2_1>;
 148                         L2_1: l2-cache {
 149                                 compatible = "arm,arch-cache";
 150                                 cache-level = <2>;
 151                         };
 152                         L1_I_100: l1-icache {
 153                                 compatible = "arm,arch-cache";
 154                         };
 155                         L1_D_100: l1-dcache {
 156                                 compatible = "arm,arch-cache";
 157                         };
 158                 };
 159
 160                 CPU5: cpu@101 {
 161                         device_type = "cpu";
 162                         compatible = "arm,armv8";
 163                         reg = <0x0 0x101>;
 164                         enable-method = "psci";
 165                         cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
 166                         next-level-cache = <&L2_1>;
 167                         L1_I_101: l1-icache {
 168                                 compatible = "arm,arch-cache";
 169                         };
 170                         L1_D_101: l1-dcache {
 171                                 compatible = "arm,arch-cache";
 172                         };
 173                 };
 174
 175                 CPU6: cpu@102 {
 176                         device_type = "cpu";
 177                         compatible = "arm,armv8";
 178                         reg = <0x0 0x102>;
 179                         enable-method = "psci";
 180                         cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
 181                         next-level-cache = <&L2_1>;
 182                         L1_I_102: l1-icache {
 183                                 compatible = "arm,arch-cache";
 184                         };
 185                         L1_D_102: l1-dcache {
 186                                 compatible = "arm,arch-cache";
 187                         };
 188                 };
 189
 190                 CPU7: cpu@103 {
 191                         device_type = "cpu";
 192                         compatible = "arm,armv8";
 193                         reg = <0x0 0x103>;
 194                         enable-method = "psci";
 195                         cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
 196                         next-level-cache = <&L2_1>;
 197                         L1_I_103: l1-icache {
 198                                 compatible = "arm,arch-cache";
 199                         };
 200                         L1_D_103: l1-dcache {
 201                                 compatible = "arm,arch-cache";
 202                         };
 203                 };
 204
 205                 cpu-map {
 206                         cluster0 {
 207                                 core0 {
 208                                         cpu = <&CPU0>;
 209                                 };
 210
 211                                 core1 {
 212                                         cpu = <&CPU1>;
 213                                 };
 214
 215                                 core2 {
 216                                         cpu = <&CPU2>;
 217                                 };
 218
 219                                 core3 {
 220                                         cpu = <&CPU3>;
 221                                 };
 222                         };
 223
 224                         cluster1 {
 225                                 core0 {
 226                                         cpu = <&CPU4>;
 227                                 };
 228
 229                                 core1 {
 230                                         cpu = <&CPU5>;
 231                                 };
 232
 233                                 core2 {
 234                                         cpu = <&CPU6>;
 235                                 };
 236
 237                                 core3 {
 238                                         cpu = <&CPU7>;
 239                                 };
 240                         };
 241                 };
 242
 243                 idle-states {
 244                         entry-method = "psci";
 245
 246                         LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
 247                                 compatible = "arm,idle-state";
 248                                 idle-state-name = "little-retention";
 249                                 arm,psci-suspend-param = <0x00000002>;
 250                                 entry-latency-us = <81>;
 251                                 exit-latency-us = <86>;
 252                                 min-residency-us = <200>;
 253                         };
 254
 255                         LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
 256                                 compatible = "arm,idle-state";
 257                                 idle-state-name = "little-power-collapse";
 258                                 arm,psci-suspend-param = <0x40000003>;
 259                                 entry-latency-us = <273>;
 260                                 exit-latency-us = <612>;
 261                                 min-residency-us = <1000>;
 262                                 local-timer-stop;
 263                         };
 264
 265                         BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
 266                                 compatible = "arm,idle-state";
 267                                 idle-state-name = "big-retention";
 268                                 arm,psci-suspend-param = <0x00000002>;
 269                                 entry-latency-us = <79>;
 270                                 exit-latency-us = <82>;
 271                                 min-residency-us = <200>;
 272                         };
 273
 274                         BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
 275                                 compatible = "arm,idle-state";
 276                                 idle-state-name = "big-power-collapse";
 277                                 arm,psci-suspend-param = <0x40000003>;
 278                                 entry-latency-us = <336>;
 279                                 exit-latency-us = <525>;
 280                                 min-residency-us = <1000>;
 281                                 local-timer-stop;
 282                         };
 283                 };
 284         };
 285
 286         firmware {
 287                 scm {
 288                         compatible = "qcom,scm-msm8998", "qcom,scm";
 289                 };
 290         };
 291
 292         tcsr_mutex: hwlock {
 293                 compatible = "qcom,tcsr-mutex";
 294                 syscon = <&tcsr_mutex_regs 0 0x1000>;
 295                 #hwlock-cells = <1>;
 296         };
 297
 298         psci {
 299                 compatible = "arm,psci-1.0";
 300                 method = "smc";
 301         };
 302
 303         rpm-glink {
 304                 compatible = "qcom,glink-rpm";
 305
 306                 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
 307                 qcom,rpm-msg-ram = <&rpm_msg_ram>;
 308                 mboxes = <&apcs_glb 0>;
 309
 310                 rpm_requests: rpm-requests {
 311                         compatible = "qcom,rpm-msm8998";
 312                         qcom,glink-channels = "rpm_requests";
 313
 314                         rpmcc: clock-controller {
 315                                 compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc";
 316                                 #clock-cells = <1>;
 317                         };
 318
 319                         rpmpd: power-controller {
 320                                 compatible = "qcom,msm8998-rpmpd";
 321                                 #power-domain-cells = <1>;
 322                                 operating-points-v2 = <&rpmpd_opp_table>;
 323
 324                                 rpmpd_opp_table: opp-table {
 325                                         compatible = "operating-points-v2";
 326
 327                                         rpmpd_opp_ret: opp1 {
 328                                                 opp-level = <16>;
 329                                         };
 330
 331                                         rpmpd_opp_ret_plus: opp2 {
 332                                                 opp-level = <32>;
 333                                         };
 334
 335                                         rpmpd_opp_min_svs: opp3 {
 336                                                 opp-level = <48>;
 337                                         };
 338
 339                                         rpmpd_opp_low_svs: opp4 {
 340                                                 opp-level = <64>;
 341                                         };
 342
 343                                         rpmpd_opp_svs: opp5 {
 344                                                 opp-level = <128>;
 345                                         };
 346
 347                                         rpmpd_opp_svs_plus: opp6 {
 348                                                 opp-level = <192>;
 349                                         };
 350
 351                                         rpmpd_opp_nom: opp7 {
 352                                                 opp-level = <256>;
 353                                         };
 354
 355                                         rpmpd_opp_nom_plus: opp8 {
 356                                                 opp-level = <320>;
 357                                         };
 358
 359                                         rpmpd_opp_turbo: opp9 {
 360                                                 opp-level = <384>;
 361                                         };
 362
 363                                         rpmpd_opp_turbo_plus: opp10 {
 364                                                 opp-level = <512>;
 365                                         };
 366                                 };
 367                         };
 368                 };
 369         };
 370
 371         smem {
 372                 compatible = "qcom,smem";
 373                 memory-region = <&smem_mem>;
 374                 hwlocks = <&tcsr_mutex 3>;
 375         };
 376
 377         smp2p-lpass {
 378                 compatible = "qcom,smp2p";
 379                 qcom,smem = <443>, <429>;
 380
 381                 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
 382
 383                 mboxes = <&apcs_glb 10>;
 384
 385                 qcom,local-pid = <0>;
 386                 qcom,remote-pid = <2>;
 387
 388                 adsp_smp2p_out: master-kernel {
 389                         qcom,entry-name = "master-kernel";
 390                         #qcom,smem-state-cells = <1>;
 391                 };
 392
 393                 adsp_smp2p_in: slave-kernel {
 394                         qcom,entry-name = "slave-kernel";
 395
 396                         interrupt-controller;
 397                         #interrupt-cells = <2>;
 398                 };
 399         };
 400
 401         smp2p-mpss {
 402                 compatible = "qcom,smp2p";
 403                 qcom,smem = <435>, <428>;
 404                 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
 405                 mboxes = <&apcs_glb 14>;
 406                 qcom,local-pid = <0>;
 407                 qcom,remote-pid = <1>;
 408
 409                 modem_smp2p_out: master-kernel {
 410                         qcom,entry-name = "master-kernel";
 411                         #qcom,smem-state-cells = <1>;
 412                 };
 413
 414                 modem_smp2p_in: slave-kernel {
 415                         qcom,entry-name = "slave-kernel";
 416                         interrupt-controller;
 417                         #interrupt-cells = <2>;
 418                 };
 419         };
 420
 421         smp2p-slpi {
 422                 compatible = "qcom,smp2p";
 423                 qcom,smem = <481>, <430>;
 424                 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
 425                 mboxes = <&apcs_glb 26>;
 426                 qcom,local-pid = <0>;
 427                 qcom,remote-pid = <3>;
 428
 429                 slpi_smp2p_out: master-kernel {
 430                         qcom,entry-name = "master-kernel";
 431                         #qcom,smem-state-cells = <1>;
 432                 };
 433
 434                 slpi_smp2p_in: slave-kernel {
 435                         qcom,entry-name = "slave-kernel";
 436                         interrupt-controller;
 437                         #interrupt-cells = <2>;
 438                 };
 439         };
 440
 441         thermal-zones {
 442                 cpu0-thermal {
 443                         polling-delay-passive = <250>;
 444                         polling-delay = <1000>;
 445
 446                         thermal-sensors = <&tsens0 1>;
 447
 448                         trips {
 449                                 cpu0_alert0: trip-point@0 {
 450                                         temperature = <75000>;
 451                                         hysteresis = <2000>;
 452                                         type = "passive";
 453                                 };
 454
 455                                 cpu0_crit: cpu_crit {
 456                                         temperature = <110000>;
 457                                         hysteresis = <2000>;
 458                                         type = "critical";
 459                                 };
 460                         };
 461                 };
 462
 463                 cpu1-thermal {
 464                         polling-delay-passive = <250>;
 465                         polling-delay = <1000>;
 466
 467                         thermal-sensors = <&tsens0 2>;
 468
 469                         trips {
 470                                 cpu1_alert0: trip-point@0 {
 471                                         temperature = <75000>;
 472                                         hysteresis = <2000>;
 473                                         type = "passive";
 474                                 };
 475
 476                                 cpu1_crit: cpu_crit {
 477                                         temperature = <110000>;
 478                                         hysteresis = <2000>;
 479                                         type = "critical";
 480                                 };
 481                         };
 482                 };
 483
 484                 cpu2-thermal {
 485                         polling-delay-passive = <250>;
 486                         polling-delay = <1000>;
 487
 488                         thermal-sensors = <&tsens0 3>;
 489
 490                         trips {
 491                                 cpu2_alert0: trip-point@0 {
 492                                         temperature = <75000>;
 493                                         hysteresis = <2000>;
 494                                         type = "passive";
 495                                 };
 496
 497                                 cpu2_crit: cpu_crit {
 498                                         temperature = <110000>;
 499                                         hysteresis = <2000>;
 500                                         type = "critical";
 501                                 };
 502                         };
 503                 };
 504
 505                 cpu3-thermal {
 506                         polling-delay-passive = <250>;
 507                         polling-delay = <1000>;
 508
 509                         thermal-sensors = <&tsens0 4>;
 510
 511                         trips {
 512                                 cpu3_alert0: trip-point@0 {
 513                                         temperature = <75000>;
 514                                         hysteresis = <2000>;
 515                                         type = "passive";
 516                                 };
 517
 518                                 cpu3_crit: cpu_crit {
 519                                         temperature = <110000>;
 520                                         hysteresis = <2000>;
 521                                         type = "critical";
 522                                 };
 523                         };
 524                 };
 525
 526                 cpu4-thermal {
 527                         polling-delay-passive = <250>;
 528                         polling-delay = <1000>;
 529
 530                         thermal-sensors = <&tsens0 7>;
 531
 532                         trips {
 533                                 cpu4_alert0: trip-point@0 {
 534                                         temperature = <75000>;
 535                                         hysteresis = <2000>;
 536                                         type = "passive";
 537                                 };
 538
 539                                 cpu4_crit: cpu_crit {
 540                                         temperature = <110000>;
 541                                         hysteresis = <2000>;
 542                                         type = "critical";
 543                                 };
 544                         };
 545                 };
 546
 547                 cpu5-thermal {
 548                         polling-delay-passive = <250>;
 549                         polling-delay = <1000>;
 550
 551                         thermal-sensors = <&tsens0 8>;
 552
 553                         trips {
 554                                 cpu5_alert0: trip-point@0 {
 555                                         temperature = <75000>;
 556                                         hysteresis = <2000>;
 557                                         type = "passive";
 558                                 };
 559
 560                                 cpu5_crit: cpu_crit {
 561                                         temperature = <110000>;
 562                                         hysteresis = <2000>;
 563                                         type = "critical";
 564                                 };
 565                         };
 566                 };
 567
 568                 cpu6-thermal {
 569                         polling-delay-passive = <250>;
 570                         polling-delay = <1000>;
 571
 572                         thermal-sensors = <&tsens0 9>;
 573
 574                         trips {
 575                                 cpu6_alert0: trip-point@0 {
 576                                         temperature = <75000>;
 577                                         hysteresis = <2000>;
 578                                         type = "passive";
 579                                 };
 580
 581                                 cpu6_crit: cpu_crit {
 582                                         temperature = <110000>;
 583                                         hysteresis = <2000>;
 584                                         type = "critical";
 585                                 };
 586                         };
 587                 };
 588
 589                 cpu7-thermal {
 590                         polling-delay-passive = <250>;
 591                         polling-delay = <1000>;
 592
 593                         thermal-sensors = <&tsens0 10>;
 594
 595                         trips {
 596                                 cpu7_alert0: trip-point@0 {
 597                                         temperature = <75000>;
 598                                         hysteresis = <2000>;
 599                                         type = "passive";
 600                                 };
 601
 602                                 cpu7_crit: cpu_crit {
 603                                         temperature = <110000>;
 604                                         hysteresis = <2000>;
 605                                         type = "critical";
 606                                 };
 607                         };
 608                 };
 609
 610                 gpu-thermal-bottom {
 611                         polling-delay-passive = <250>;
 612                         polling-delay = <1000>;
 613
 614                         thermal-sensors = <&tsens0 12>;
 615
 616                         trips {
 617                                 gpu1_alert0: trip-point@0 {
 618                                         temperature = <90000>;
 619                                         hysteresis = <2000>;
 620                                         type = "hot";
 621                                 };
 622                         };
 623                 };
 624
 625                 gpu-thermal-top {
 626                         polling-delay-passive = <250>;
 627                         polling-delay = <1000>;
 628
 629                         thermal-sensors = <&tsens0 13>;
 630
 631                         trips {
 632                                 gpu2_alert0: trip-point@0 {
 633                                         temperature = <90000>;
 634                                         hysteresis = <2000>;
 635                                         type = "hot";
 636                                 };
 637                         };
 638                 };
 639
 640                 clust0-mhm-thermal {
 641                         polling-delay-passive = <250>;
 642                         polling-delay = <1000>;
 643
 644                         thermal-sensors = <&tsens0 5>;
 645
 646                         trips {
 647                                 cluster0_mhm_alert0: trip-point@0 {
 648                                         temperature = <90000>;
 649                                         hysteresis = <2000>;
 650                                         type = "hot";
 651                                 };
 652                         };
 653                 };
 654
 655                 clust1-mhm-thermal {
 656                         polling-delay-passive = <250>;
 657                         polling-delay = <1000>;
 658
 659                         thermal-sensors = <&tsens0 6>;
 660
 661                         trips {
 662                                 cluster1_mhm_alert0: trip-point@0 {
 663                                         temperature = <90000>;
 664                                         hysteresis = <2000>;
 665                                         type = "hot";
 666                                 };
 667                         };
 668                 };
 669
 670                 cluster1-l2-thermal {
 671                         polling-delay-passive = <250>;
 672                         polling-delay = <1000>;
 673
 674                         thermal-sensors = <&tsens0 11>;
 675
 676                         trips {
 677                                 cluster1_l2_alert0: trip-point@0 {
 678                                         temperature = <90000>;
 679                                         hysteresis = <2000>;
 680                                         type = "hot";
 681                                 };
 682                         };
 683                 };
 684
 685                 modem-thermal {
 686                         polling-delay-passive = <250>;
 687                         polling-delay = <1000>;
 688
 689                         thermal-sensors = <&tsens1 1>;
 690
 691                         trips {
 692                                 modem_alert0: trip-point@0 {
 693                                         temperature = <90000>;
 694                                         hysteresis = <2000>;
 695                                         type = "hot";
 696                                 };
 697                         };
 698                 };
 699
 700                 mem-thermal {
 701                         polling-delay-passive = <250>;
 702                         polling-delay = <1000>;
 703
 704                         thermal-sensors = <&tsens1 2>;
 705
 706                         trips {
 707                                 mem_alert0: trip-point@0 {
 708                                         temperature = <90000>;
 709                                         hysteresis = <2000>;
 710                                         type = "hot";
 711                                 };
 712                         };
 713                 };
 714
 715                 wlan-thermal {
 716                         polling-delay-passive = <250>;
 717                         polling-delay = <1000>;
 718
 719                         thermal-sensors = <&tsens1 3>;
 720
 721                         trips {
 722                                 wlan_alert0: trip-point@0 {
 723                                         temperature = <90000>;
 724                                         hysteresis = <2000>;
 725                                         type = "hot";
 726                                 };
 727                         };
 728                 };
 729
 730                 q6-dsp-thermal {
 731                         polling-delay-passive = <250>;
 732                         polling-delay = <1000>;
 733
 734                         thermal-sensors = <&tsens1 4>;
 735
 736                         trips {
 737                                 q6_dsp_alert0: trip-point@0 {
 738                                         temperature = <90000>;
 739                                         hysteresis = <2000>;
 740                                         type = "hot";
 741                                 };
 742                         };
 743                 };
 744
 745                 camera-thermal {
 746                         polling-delay-passive = <250>;
 747                         polling-delay = <1000>;
 748
 749                         thermal-sensors = <&tsens1 5>;
 750
 751                         trips {
 752                                 camera_alert0: trip-point@0 {
 753                                         temperature = <90000>;
 754                                         hysteresis = <2000>;
 755                                         type = "hot";
 756                                 };
 757                         };
 758                 };
 759
 760                 multimedia-thermal {
 761                         polling-delay-passive = <250>;
 762                         polling-delay = <1000>;
 763
 764                         thermal-sensors = <&tsens1 6>;
 765
 766                         trips {
 767                                 multimedia_alert0: trip-point@0 {
 768                                         temperature = <90000>;
 769                                         hysteresis = <2000>;
 770                                         type = "hot";
 771                                 };
 772                         };
 773                 };
 774         };
 775
 776         timer {
 777                 compatible = "arm,armv8-timer";
 778                 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
 779                              <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
 780                              <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
 781                              <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
 782         };
 783
 784         soc: soc {
 785                 #address-cells = <1>;
 786                 #size-cells = <1>;
 787                 ranges = <0 0 0 0xffffffff>;
 788                 compatible = "simple-bus";
 789
 790                 gcc: clock-controller@100000 {
 791                         compatible = "qcom,gcc-msm8998";
 792                         #clock-cells = <1>;
 793                         #reset-cells = <1>;
 794                         #power-domain-cells = <1>;
 795                         reg = <0x00100000 0xb0000>;
 796                 };
 797
 798                 rpm_msg_ram: memory@778000 {
 799                         compatible = "qcom,rpm-msg-ram";
 800                         reg = <0x00778000 0x7000>;
 801                 };
 802
 803                 qfprom: qfprom@780000 {
 804                         compatible = "qcom,qfprom";
 805                         reg = <0x00780000 0x621c>;
 806                         #address-cells = <1>;
 807                         #size-cells = <1>;
 808
 809                         qusb2_hstx_trim: hstx-trim@423a {
 810                                 reg = <0x423a 0x1>;
 811                                 bits = <0 4>;
 812                         };
 813                 };
 814
 815                 tsens0: thermal@10ab000 {
 816                         compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
 817                         reg = <0x010ab000 0x1000>, /* TM */
 818                               <0x010aa000 0x1000>; /* SROT */
 819                         #qcom,sensors = <14>;
 820                         interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>;
 821                         interrupt-names = "uplow";
 822                         #thermal-sensor-cells = <1>;
 823                 };
 824
 825                 tsens1: thermal@10ae000 {
 826                         compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
 827                         reg = <0x010ae000 0x1000>, /* TM */
 828                               <0x010ad000 0x1000>; /* SROT */
 829                         #qcom,sensors = <8>;
 830                         interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
 831                         interrupt-names = "uplow";
 832                         #thermal-sensor-cells = <1>;
 833                 };
 834
 835                 anoc1_smmu: iommu@1680000 {
 836                         compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
 837                         reg = <0x01680000 0x10000>;
 838                         #iommu-cells = <1>;
 839
 840                         #global-interrupts = <0>;
 841                         interrupts =
 842                                 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
 843                                 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
 844                                 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
 845                                 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
 846                                 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
 847                                 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>;
 848                 };
 849
 850                 pcie0: pci@1c00000 {
 851                         compatible = "qcom,pcie-msm8996";
 852                         reg =   <0x01c00000 0x2000>,
 853                                 <0x1b000000 0xf1d>,
 854                                 <0x1b000f20 0xa8>,
 855                                 <0x1b100000 0x100000>;
 856                         reg-names = "parf", "dbi", "elbi", "config";
 857                         device_type = "pci";
 858                         linux,pci-domain = <0>;
 859                         bus-range = <0x00 0xff>;
 860                         #address-cells = <3>;
 861                         #size-cells = <2>;
 862                         num-lanes = <1>;
 863                         phys = <&pciephy>;
 864                         phy-names = "pciephy";
 865
 866                         ranges = <0x01000000 0x0 0x1b200000 0x1b200000 0x0 0x100000>,
 867                                  <0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>;
 868
 869                         #interrupt-cells = <1>;
 870                         interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
 871                         interrupt-names = "msi";
 872                         interrupt-map-mask = <0 0 0 0x7>;
 873                         interrupt-map = <0 0 0 1 &intc 0 135 IRQ_TYPE_LEVEL_HIGH>,
 874                                         <0 0 0 2 &intc 0 136 IRQ_TYPE_LEVEL_HIGH>,
 875                                         <0 0 0 3 &intc 0 138 IRQ_TYPE_LEVEL_HIGH>,
 876                                         <0 0 0 4 &intc 0 139 IRQ_TYPE_LEVEL_HIGH>;
 877
 878                         clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
 879                                  <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
 880                                  <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
 881                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
 882                                  <&gcc GCC_PCIE_0_AUX_CLK>;
 883                         clock-names = "pipe", "bus_master", "bus_slave", "cfg", "aux";
 884
 885                         power-domains = <&gcc PCIE_0_GDSC>;
 886                         iommu-map = <0x100 &anoc1_smmu 0x1480 1>;
 887                         perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
 888                 };
 889
 890                 phy@1c06000 {
 891                         compatible = "qcom,msm8998-qmp-pcie-phy";
 892                         reg = <0x01c06000 0x18c>;
 893                         #address-cells = <1>;
 894                         #size-cells = <1>;
 895                         ranges;
 896
 897                         clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
 898                                  <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
 899                                  <&gcc GCC_PCIE_CLKREF_CLK>;
 900                         clock-names = "aux", "cfg_ahb", "ref";
 901
 902                         resets = <&gcc GCC_PCIE_0_PHY_BCR>, <&gcc GCC_PCIE_PHY_BCR>;
 903                         reset-names = "phy", "common";
 904
 905                         vdda-phy-supply = <&vreg_l1a_0p875>;
 906                         vdda-pll-supply = <&vreg_l2a_1p2>;
 907
 908                         pciephy: lane@1c06800 {
 909                                 reg = <0x01c06200 0x128>, <0x01c06400 0x1fc>, <0x01c06800 0x20c>;
 910                                 #phy-cells = <0>;
 911
 912                                 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
 913                                 clock-names = "pipe0";
 914                                 clock-output-names = "pcie_0_pipe_clk_src";
 915                                 #clock-cells = <0>;
 916                         };
 917                 };
 918
 919                 ufshc: ufshc@1da4000 {
 920                         compatible = "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
 921                         reg = <0x01da4000 0x2500>;
 922                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
 923                         phys = <&ufsphy_lanes>;
 924                         phy-names = "ufsphy";
 925                         lanes-per-direction = <2>;
 926                         power-domains = <&gcc UFS_GDSC>;
 927                         #reset-cells = <1>;
 928
 929                         clock-names =
 930                                 "core_clk",
 931                                 "bus_aggr_clk",
 932                                 "iface_clk",
 933                                 "core_clk_unipro",
 934                                 "ref_clk",
 935                                 "tx_lane0_sync_clk",
 936                                 "rx_lane0_sync_clk",
 937                                 "rx_lane1_sync_clk";
 938                         clocks =
 939                                 <&gcc GCC_UFS_AXI_CLK>,
 940                                 <&gcc GCC_AGGRE1_UFS_AXI_CLK>,
 941                                 <&gcc GCC_UFS_AHB_CLK>,
 942                                 <&gcc GCC_UFS_UNIPRO_CORE_CLK>,
 943                                 <&rpmcc RPM_SMD_LN_BB_CLK1>,
 944                                 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
 945                                 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>,
 946                                 <&gcc GCC_UFS_RX_SYMBOL_1_CLK>;
 947                         freq-table-hz =
 948                                 <50000000 200000000>,
 949                                 <0 0>,
 950                                 <0 0>,
 951                                 <37500000 150000000>,
 952                                 <0 0>,
 953                                 <0 0>,
 954                                 <0 0>,
 955                                 <0 0>;
 956
 957                         resets = <&gcc GCC_UFS_BCR>;
 958                         reset-names = "rst";
 959                 };
 960
 961                 ufsphy: phy@1da7000 {
 962                         compatible = "qcom,msm8998-qmp-ufs-phy";
 963                         reg = <0x01da7000 0x18c>;
 964                         #address-cells = <1>;
 965                         #size-cells = <1>;
 966                         ranges;
 967
 968                         clock-names =
 969                                 "ref",
 970                                 "ref_aux";
 971                         clocks =
 972                                 <&gcc GCC_UFS_CLKREF_CLK>,
 973                                 <&gcc GCC_UFS_PHY_AUX_CLK>;
 974
 975                         reset-names = "ufsphy";
 976                         resets = <&ufshc 0>;
 977
 978                         ufsphy_lanes: lanes@1da7400 {
 979                                 reg = <0x01da7400 0x128>,
 980                                       <0x01da7600 0x1fc>,
 981                                       <0x01da7c00 0x1dc>,
 982                                       <0x01da7800 0x128>,
 983                                       <0x01da7a00 0x1fc>;
 984                                 #phy-cells = <0>;
 985                         };
 986                 };
 987
 988                 tcsr_mutex_regs: syscon@1f40000 {
 989                         compatible = "syscon";
 990                         reg = <0x01f40000 0x20000>;
 991                 };
 992
 993                 tlmm: pinctrl@3400000 {
 994                         compatible = "qcom,msm8998-pinctrl";
 995                         reg = <0x03400000 0xc00000>;
 996                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 997                         gpio-controller;
 998                         #gpio-cells = <0x2>;
 999                         interrupt-controller;
1000                         #interrupt-cells = <0x2>;
1001                 };
1002
1003                 stm: stm@6002000 {
1004                         compatible = "arm,coresight-stm", "arm,primecell";
1005                         reg = <0x06002000 0x1000>,
1006                               <0x16280000 0x180000>;
1007                         reg-names = "stm-base", "stm-data-base";
1008                         status = "disabled";
1009
1010                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1011                         clock-names = "apb_pclk", "atclk";
1012
1013                         out-ports {
1014                                 port {
1015                                         stm_out: endpoint {
1016                                                 remote-endpoint = <&funnel0_in7>;
1017                                         };
1018                                 };
1019                         };
1020                 };
1021
1022                 funnel1: funnel@6041000 {
1023                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1024                         reg = <0x06041000 0x1000>;
1025                         status = "disabled";
1026
1027                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1028                         clock-names = "apb_pclk", "atclk";
1029
1030                         out-ports {
1031                                 port {
1032                                         funnel0_out: endpoint {
1033                                                 remote-endpoint =
1034                                                   <&merge_funnel_in0>;
1035                                         };
1036                                 };
1037                         };
1038
1039                         in-ports {
1040                                 #address-cells = <1>;
1041                                 #size-cells = <0>;
1042
1043                                 port@7 {
1044                                         reg = <7>;
1045                                         funnel0_in7: endpoint {
1046                                                 remote-endpoint = <&stm_out>;
1047                                         };
1048                                 };
1049                         };
1050                 };
1051
1052                 funnel2: funnel@6042000 {
1053                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1054                         reg = <0x06042000 0x1000>;
1055                         status = "disabled";
1056
1057                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1058                         clock-names = "apb_pclk", "atclk";
1059
1060                         out-ports {
1061                                 port {
1062                                         funnel1_out: endpoint {
1063                                                 remote-endpoint =
1064                                                   <&merge_funnel_in1>;
1065                                         };
1066                                 };
1067                         };
1068
1069                         in-ports {
1070                                 #address-cells = <1>;
1071                                 #size-cells = <0>;
1072
1073                                 port@6 {
1074                                         reg = <6>;
1075                                         funnel1_in6: endpoint {
1076                                                 remote-endpoint =
1077                                                   <&apss_merge_funnel_out>;
1078                                         };
1079                                 };
1080                         };
1081                 };
1082
1083                 funnel3: funnel@6045000 {
1084                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1085                         reg = <0x06045000 0x1000>;
1086                         status = "disabled";
1087
1088                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1089                         clock-names = "apb_pclk", "atclk";
1090
1091                         out-ports {
1092                                 port {
1093                                         merge_funnel_out: endpoint {
1094                                                 remote-endpoint =
1095                                                   <&etf_in>;
1096                                         };
1097                                 };
1098                         };
1099
1100                         in-ports {
1101                                 #address-cells = <1>;
1102                                 #size-cells = <0>;
1103
1104                                 port@0 {
1105                                         reg = <0>;
1106                                         merge_funnel_in0: endpoint {
1107                                                 remote-endpoint =
1108                                                   <&funnel0_out>;
1109                                         };
1110                                 };
1111
1112                                 port@1 {
1113                                         reg = <1>;
1114                                         merge_funnel_in1: endpoint {
1115                                                 remote-endpoint =
1116                                                   <&funnel1_out>;
1117                                         };
1118                                 };
1119                         };
1120                 };
1121
1122                 replicator1: replicator@6046000 {
1123                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
1124                         reg = <0x06046000 0x1000>;
1125                         status = "disabled";
1126
1127                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1128                         clock-names = "apb_pclk", "atclk";
1129
1130                         out-ports {
1131                                 port {
1132                                         replicator_out: endpoint {
1133                                                 remote-endpoint = <&etr_in>;
1134                                         };
1135                                 };
1136                         };
1137
1138                         in-ports {
1139                                 port {
1140                                         replicator_in: endpoint {
1141                                                 remote-endpoint = <&etf_out>;
1142                                         };
1143                                 };
1144                         };
1145                 };
1146
1147                 etf: etf@6047000 {
1148                         compatible = "arm,coresight-tmc", "arm,primecell";
1149                         reg = <0x06047000 0x1000>;
1150                         status = "disabled";
1151
1152                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1153                         clock-names = "apb_pclk", "atclk";
1154
1155                         out-ports {
1156                                 port {
1157                                         etf_out: endpoint {
1158                                                 remote-endpoint =
1159                                                   <&replicator_in>;
1160                                         };
1161                                 };
1162                         };
1163
1164                         in-ports {
1165                                 port {
1166                                         etf_in: endpoint {
1167                                                 remote-endpoint =
1168                                                   <&merge_funnel_out>;
1169                                         };
1170                                 };
1171                         };
1172                 };
1173
1174                 etr: etr@6048000 {
1175                         compatible = "arm,coresight-tmc", "arm,primecell";
1176                         reg = <0x06048000 0x1000>;
1177                         status = "disabled";
1178
1179                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1180                         clock-names = "apb_pclk", "atclk";
1181                         arm,scatter-gather;
1182
1183                         in-ports {
1184                                 port {
1185                                         etr_in: endpoint {
1186                                                 remote-endpoint =
1187                                                   <&replicator_out>;
1188                                         };
1189                                 };
1190                         };
1191                 };
1192
1193                 etm1: etm@7840000 {
1194                         compatible = "arm,coresight-etm4x", "arm,primecell";
1195                         reg = <0x07840000 0x1000>;
1196                         status = "disabled";
1197
1198                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1199                         clock-names = "apb_pclk", "atclk";
1200
1201                         cpu = <&CPU0>;
1202
1203                         out-ports {
1204                                 port {
1205                                         etm0_out: endpoint {
1206                                                 remote-endpoint =
1207                                                   <&apss_funnel_in0>;
1208                                         };
1209                                 };
1210                         };
1211                 };
1212
1213                 etm2: etm@7940000 {
1214                         compatible = "arm,coresight-etm4x", "arm,primecell";
1215                         reg = <0x07940000 0x1000>;
1216                         status = "disabled";
1217
1218                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1219                         clock-names = "apb_pclk", "atclk";
1220
1221                         cpu = <&CPU1>;
1222
1223                         out-ports {
1224                                 port {
1225                                         etm1_out: endpoint {
1226                                                 remote-endpoint =
1227                                                   <&apss_funnel_in1>;
1228                                         };
1229                                 };
1230                         };
1231                 };
1232
1233                 etm3: etm@7a40000 {
1234                         compatible = "arm,coresight-etm4x", "arm,primecell";
1235                         reg = <0x07a40000 0x1000>;
1236                         status = "disabled";
1237
1238                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1239                         clock-names = "apb_pclk", "atclk";
1240
1241                         cpu = <&CPU2>;
1242
1243                         out-ports {
1244                                 port {
1245                                         etm2_out: endpoint {
1246                                                 remote-endpoint =
1247                                                   <&apss_funnel_in2>;
1248                                         };
1249                                 };
1250                         };
1251                 };
1252
1253                 etm4: etm@7b40000 {
1254                         compatible = "arm,coresight-etm4x", "arm,primecell";
1255                         reg = <0x07b40000 0x1000>;
1256                         status = "disabled";
1257
1258                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1259                         clock-names = "apb_pclk", "atclk";
1260
1261                         cpu = <&CPU3>;
1262
1263                         out-ports {
1264                                 port {
1265                                         etm3_out: endpoint {
1266                                                 remote-endpoint =
1267                                                   <&apss_funnel_in3>;
1268                                         };
1269                                 };
1270                         };
1271                 };
1272
1273                 funnel4: funnel@7b60000 { /* APSS Funnel */
1274                         compatible = "arm,coresight-etm4x", "arm,primecell";
1275                         reg = <0x07b60000 0x1000>;
1276                         status = "disabled";
1277
1278                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1279                         clock-names = "apb_pclk", "atclk";
1280
1281                         out-ports {
1282                                 port {
1283                                         apss_funnel_out: endpoint {
1284                                                 remote-endpoint =
1285                                                   <&apss_merge_funnel_in>;
1286                                         };
1287                                 };
1288                         };
1289
1290                         in-ports {
1291                                 #address-cells = <1>;
1292                                 #size-cells = <0>;
1293
1294                                 port@0 {
1295                                         reg = <0>;
1296                                         apss_funnel_in0: endpoint {
1297                                                 remote-endpoint =
1298                                                   <&etm0_out>;
1299                                         };
1300                                 };
1301
1302                                 port@1 {
1303                                         reg = <1>;
1304                                         apss_funnel_in1: endpoint {
1305                                                 remote-endpoint =
1306                                                   <&etm1_out>;
1307                                         };
1308                                 };
1309
1310                                 port@2 {
1311                                         reg = <2>;
1312                                         apss_funnel_in2: endpoint {
1313                                                 remote-endpoint =
1314                                                   <&etm2_out>;
1315                                         };
1316                                 };
1317
1318                                 port@3 {
1319                                         reg = <3>;
1320                                         apss_funnel_in3: endpoint {
1321                                                 remote-endpoint =
1322                                                   <&etm3_out>;
1323                                         };
1324                                 };
1325
1326                                 port@4 {
1327                                         reg = <4>;
1328                                         apss_funnel_in4: endpoint {
1329                                                 remote-endpoint =
1330                                                   <&etm4_out>;
1331                                         };
1332                                 };
1333
1334                                 port@5 {
1335                                         reg = <5>;
1336                                         apss_funnel_in5: endpoint {
1337                                                 remote-endpoint =
1338                                                   <&etm5_out>;
1339                                         };
1340                                 };
1341
1342                                 port@6 {
1343                                         reg = <6>;
1344                                         apss_funnel_in6: endpoint {
1345                                                 remote-endpoint =
1346                                                   <&etm6_out>;
1347                                         };
1348                                 };
1349
1350                                 port@7 {
1351                                         reg = <7>;
1352                                         apss_funnel_in7: endpoint {
1353                                                 remote-endpoint =
1354                                                   <&etm7_out>;
1355                                         };
1356                                 };
1357                         };
1358                 };
1359
1360                 funnel5: funnel@7b70000 {
1361                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1362                         reg = <0x07b70000 0x1000>;
1363                         status = "disabled";
1364
1365                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1366                         clock-names = "apb_pclk", "atclk";
1367
1368                         out-ports {
1369                                 port {
1370                                         apss_merge_funnel_out: endpoint {
1371                                                 remote-endpoint =
1372                                                   <&funnel1_in6>;
1373                                         };
1374                                 };
1375                         };
1376
1377                         in-ports {
1378                                 port {
1379                                         apss_merge_funnel_in: endpoint {
1380                                                 remote-endpoint =
1381                                                   <&apss_funnel_out>;
1382                                         };
1383                                 };
1384                         };
1385                 };
1386
1387                 etm5: etm@7c40000 {
1388                         compatible = "arm,coresight-etm4x", "arm,primecell";
1389                         reg = <0x07c40000 0x1000>;
1390                         status = "disabled";
1391
1392                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1393                         clock-names = "apb_pclk", "atclk";
1394
1395                         cpu = <&CPU4>;
1396
1397                         port{
1398                                 etm4_out: endpoint {
1399                                         remote-endpoint = <&apss_funnel_in4>;
1400                                 };
1401                         };
1402                 };
1403
1404                 etm6: etm@7d40000 {
1405                         compatible = "arm,coresight-etm4x", "arm,primecell";
1406                         reg = <0x07d40000 0x1000>;
1407                         status = "disabled";
1408
1409                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1410                         clock-names = "apb_pclk", "atclk";
1411
1412                         cpu = <&CPU5>;
1413
1414                         port{
1415                                 etm5_out: endpoint {
1416                                         remote-endpoint = <&apss_funnel_in5>;
1417                                 };
1418                         };
1419                 };
1420
1421                 etm7: etm@7e40000 {
1422                         compatible = "arm,coresight-etm4x", "arm,primecell";
1423                         reg = <0x07e40000 0x1000>;
1424                         status = "disabled";
1425
1426                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1427                         clock-names = "apb_pclk", "atclk";
1428
1429                         cpu = <&CPU6>;
1430
1431                         port{
1432                                 etm6_out: endpoint {
1433                                         remote-endpoint = <&apss_funnel_in6>;
1434                                 };
1435                         };
1436                 };
1437
1438                 etm8: etm@7f40000 {
1439                         compatible = "arm,coresight-etm4x", "arm,primecell";
1440                         reg = <0x07f40000 0x1000>;
1441                         status = "disabled";
1442
1443                         clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1444                         clock-names = "apb_pclk", "atclk";
1445
1446                         cpu = <&CPU7>;
1447
1448                         port{
1449                                 etm7_out: endpoint {
1450                                         remote-endpoint = <&apss_funnel_in7>;
1451                                 };
1452                         };
1453                 };
1454
1455                 spmi_bus: spmi@800f000 {
1456                         compatible = "qcom,spmi-pmic-arb";
1457                         reg =   <0x0800f000 0x1000>,
1458                                 <0x08400000 0x1000000>,
1459                                 <0x09400000 0x1000000>,
1460                                 <0x0a400000 0x220000>,
1461                                 <0x0800a000 0x3000>;
1462                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1463                         interrupt-names = "periph_irq";
1464                         interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
1465                         qcom,ee = <0>;
1466                         qcom,channel = <0>;
1467                         #address-cells = <2>;
1468                         #size-cells = <0>;
1469                         interrupt-controller;
1470                         #interrupt-cells = <4>;
1471                         cell-index = <0>;
1472                 };
1473
1474                 usb3: usb@a8f8800 {
1475                         compatible = "qcom,msm8998-dwc3", "qcom,dwc3";
1476                         reg = <0x0a8f8800 0x400>;
1477                         status = "disabled";
1478                         #address-cells = <1>;
1479                         #size-cells = <1>;
1480                         ranges;
1481
1482                         clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>,
1483                                  <&gcc GCC_USB30_MASTER_CLK>,
1484                                  <&gcc GCC_AGGRE1_USB3_AXI_CLK>,
1485                                  <&gcc GCC_USB30_MOCK_UTMI_CLK>,
1486                                  <&gcc GCC_USB30_SLEEP_CLK>;
1487                         clock-names = "cfg_noc", "core", "iface", "mock_utmi",
1488                                       "sleep";
1489
1490                         assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
1491                                           <&gcc GCC_USB30_MASTER_CLK>;
1492                         assigned-clock-rates = <19200000>, <120000000>;
1493
1494                         interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
1495                                      <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
1496                         interrupt-names = "hs_phy_irq", "ss_phy_irq";
1497
1498                         power-domains = <&gcc USB_30_GDSC>;
1499
1500                         resets = <&gcc GCC_USB_30_BCR>;
1501
1502                         usb3_dwc3: dwc3@a800000 {
1503                                 compatible = "snps,dwc3";
1504                                 reg = <0x0a800000 0xcd00>;
1505                                 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
1506                                 snps,dis_u2_susphy_quirk;
1507                                 snps,dis_enblslpm_quirk;
1508                                 phys = <&qusb2phy>, <&usb1_ssphy>;
1509                                 phy-names = "usb2-phy", "usb3-phy";
1510                                 snps,has-lpm-erratum;
1511                                 snps,hird-threshold = /bits/ 8 <0x10>;
1512                         };
1513                 };
1514
1515                 usb3phy: phy@c010000 {
1516                         compatible = "qcom,msm8998-qmp-usb3-phy";
1517                         reg = <0x0c010000 0x18c>;
1518                         status = "disabled";
1519                         #clock-cells = <1>;
1520                         #address-cells = <1>;
1521                         #size-cells = <1>;
1522                         ranges;
1523
1524                         clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
1525                                  <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1526                                  <&gcc GCC_USB3_CLKREF_CLK>;
1527                         clock-names = "aux", "cfg_ahb", "ref";
1528
1529                         resets = <&gcc GCC_USB3_PHY_BCR>,
1530                                  <&gcc GCC_USB3PHY_PHY_BCR>;
1531                         reset-names = "phy", "common";
1532
1533                         usb1_ssphy: lane@c010200 {
1534                                 reg = <0xc010200 0x128>,
1535                                       <0xc010400 0x200>,
1536                                       <0xc010c00 0x20c>,
1537                                       <0xc010600 0x128>,
1538                                       <0xc010800 0x200>;
1539                                 #phy-cells = <0>;
1540                                 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
1541                                 clock-names = "pipe0";
1542                                 clock-output-names = "usb3_phy_pipe_clk_src";
1543                         };
1544                 };
1545
1546                 qusb2phy: phy@c012000 {
1547                         compatible = "qcom,msm8998-qusb2-phy";
1548                         reg = <0x0c012000 0x2a8>;
1549                         status = "disabled";
1550                         #phy-cells = <0>;
1551
1552                         clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1553                                  <&gcc GCC_RX1_USB2_CLKREF_CLK>;
1554                         clock-names = "cfg_ahb", "ref";
1555
1556                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
1557
1558                         nvmem-cells = <&qusb2_hstx_trim>;
1559                 };
1560
1561                 sdhc2: sdhci@c0a4900 {
1562                         compatible = "qcom,sdhci-msm-v4";
1563                         reg = <0x0c0a4900 0x314>, <0x0c0a4000 0x800>;
1564                         reg-names = "hc_mem", "core_mem";
1565
1566                         interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1567                                      <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
1568                         interrupt-names = "hc_irq", "pwr_irq";
1569
1570                         clock-names = "iface", "core", "xo";
1571                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
1572                                  <&gcc GCC_SDCC2_APPS_CLK>,
1573                                  <&xo>;
1574                         bus-width = <4>;
1575                         status = "disabled";
1576                 };
1577
1578                 blsp1_dma: dma@c144000 {
1579                         compatible = "qcom,bam-v1.7.0";
1580                         reg = <0x0c144000 0x25000>;
1581                         interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
1582                         clocks = <&gcc GCC_BLSP1_AHB_CLK>;
1583                         clock-names = "bam_clk";
1584                         #dma-cells = <1>;
1585                         qcom,ee = <0>;
1586                         qcom,controlled-remotely;
1587                         num-channels = <18>;
1588                         qcom,num-ees = <4>;
1589                 };
1590
1591                 blsp1_uart3: serial@c171000 {
1592                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1593                         reg = <0x0c171000 0x1000>;
1594                         interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
1595                         clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
1596                                  <&gcc GCC_BLSP1_AHB_CLK>;
1597                         clock-names = "core", "iface";
1598                         dmas = <&blsp1_dma 4>, <&blsp1_dma 5>;
1599                         dma-names = "tx", "rx";
1600                         pinctrl-names = "default";
1601                         pinctrl-0 = <&blsp1_uart3_on>;
1602                         status = "disabled";
1603                 };
1604
1605                 blsp1_i2c1: i2c@c175000 {
1606                         compatible = "qcom,i2c-qup-v2.2.1";
1607                         reg = <0x0c175000 0x600>;
1608                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1609
1610                         clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
1611                                  <&gcc GCC_BLSP1_AHB_CLK>;
1612                         clock-names = "core", "iface";
1613                         clock-frequency = <400000>;
1614
1615                         status = "disabled";
1616                         #address-cells = <1>;
1617                         #size-cells = <0>;
1618                 };
1619
1620                 blsp1_i2c2: i2c@c176000 {
1621                         compatible = "qcom,i2c-qup-v2.2.1";
1622                         reg = <0x0c176000 0x600>;
1623                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1624
1625                         clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
1626                                  <&gcc GCC_BLSP1_AHB_CLK>;
1627                         clock-names = "core", "iface";
1628                         clock-frequency = <400000>;
1629
1630                         status = "disabled";
1631                         #address-cells = <1>;
1632                         #size-cells = <0>;
1633                 };
1634
1635                 blsp1_i2c3: i2c@c177000 {
1636                         compatible = "qcom,i2c-qup-v2.2.1";
1637                         reg = <0x0c177000 0x600>;
1638                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1639
1640                         clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
1641                                  <&gcc GCC_BLSP1_AHB_CLK>;
1642                         clock-names = "core", "iface";
1643                         clock-frequency = <400000>;
1644
1645                         status = "disabled";
1646                         #address-cells = <1>;
1647                         #size-cells = <0>;
1648                 };
1649
1650                 blsp1_i2c4: i2c@c178000 {
1651                         compatible = "qcom,i2c-qup-v2.2.1";
1652                         reg = <0x0c178000 0x600>;
1653                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1654
1655                         clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
1656                                  <&gcc GCC_BLSP1_AHB_CLK>;
1657                         clock-names = "core", "iface";
1658                         clock-frequency = <400000>;
1659
1660                         status = "disabled";
1661                         #address-cells = <1>;
1662                         #size-cells = <0>;
1663                 };
1664
1665                 blsp1_i2c5: i2c@c179000 {
1666                         compatible = "qcom,i2c-qup-v2.2.1";
1667                         reg = <0x0c179000 0x600>;
1668                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
1669
1670                         clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
1671                                  <&gcc GCC_BLSP1_AHB_CLK>;
1672                         clock-names = "core", "iface";
1673                         clock-frequency = <400000>;
1674
1675                         status = "disabled";
1676                         #address-cells = <1>;
1677                         #size-cells = <0>;
1678                 };
1679
1680                 blsp1_i2c6: i2c@c17a000 {
1681                         compatible = "qcom,i2c-qup-v2.2.1";
1682                         reg = <0x0c17a000 0x600>;
1683                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1684
1685                         clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
1686                                  <&gcc GCC_BLSP1_AHB_CLK>;
1687                         clock-names = "core", "iface";
1688                         clock-frequency = <400000>;
1689
1690                         status = "disabled";
1691                         #address-cells = <1>;
1692                         #size-cells = <0>;
1693                 };
1694
1695                 blsp2_uart1: serial@c1b0000 {
1696                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1697                         reg = <0x0c1b0000 0x1000>;
1698                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
1699                         clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
1700                                  <&gcc GCC_BLSP2_AHB_CLK>;
1701                         clock-names = "core", "iface";
1702                         status = "disabled";
1703                 };
1704
1705                 blsp2_i2c0: i2c@c1b5000 {
1706                         compatible = "qcom,i2c-qup-v2.2.1";
1707                         reg = <0x0c1b5000 0x600>;
1708                         interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1709
1710                         clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
1711                                  <&gcc GCC_BLSP2_AHB_CLK>;
1712                         clock-names = "core", "iface";
1713                         clock-frequency = <400000>;
1714
1715                         status = "disabled";
1716                         #address-cells = <1>;
1717                         #size-cells = <0>;
1718                 };
1719
1720                 blsp2_i2c1: i2c@c1b6000 {
1721                         compatible = "qcom,i2c-qup-v2.2.1";
1722                         reg = <0x0c1b6000 0x600>;
1723                         interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1724
1725                         clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
1726                                  <&gcc GCC_BLSP2_AHB_CLK>;
1727                         clock-names = "core", "iface";
1728                         clock-frequency = <400000>;
1729
1730                         status = "disabled";
1731                         #address-cells = <1>;
1732                         #size-cells = <0>;
1733                 };
1734
1735                 blsp2_i2c2: i2c@c1b7000 {
1736                         compatible = "qcom,i2c-qup-v2.2.1";
1737                         reg = <0x0c1b7000 0x600>;
1738                         interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1739
1740                         clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
1741                                  <&gcc GCC_BLSP2_AHB_CLK>;
1742                         clock-names = "core", "iface";
1743                         clock-frequency = <400000>;
1744
1745                         status = "disabled";
1746                         #address-cells = <1>;
1747                         #size-cells = <0>;
1748                 };
1749
1750                 blsp2_i2c3: i2c@c1b8000 {
1751                         compatible = "qcom,i2c-qup-v2.2.1";
1752                         reg = <0x0c1b8000 0x600>;
1753                         interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1754
1755                         clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>,
1756                                  <&gcc GCC_BLSP2_AHB_CLK>;
1757                         clock-names = "core", "iface";
1758                         clock-frequency = <400000>;
1759
1760                         status = "disabled";
1761                         #address-cells = <1>;
1762                         #size-cells = <0>;
1763                 };
1764
1765                 blsp2_i2c4: i2c@c1b9000 {
1766                         compatible = "qcom,i2c-qup-v2.2.1";
1767                         reg = <0x0c1b9000 0x600>;
1768                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1769
1770                         clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
1771                                  <&gcc GCC_BLSP2_AHB_CLK>;
1772                         clock-names = "core", "iface";
1773                         clock-frequency = <400000>;
1774
1775                         status = "disabled";
1776                         #address-cells = <1>;
1777                         #size-cells = <0>;
1778                 };
1779
1780                 blsp2_i2c5: i2c@c1ba000 {
1781                         compatible = "qcom,i2c-qup-v2.2.1";
1782                         reg = <0x0c1ba000 0x600>;
1783                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
1784
1785                         clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>,
1786                                  <&gcc GCC_BLSP2_AHB_CLK>;
1787                         clock-names = "core", "iface";
1788                         clock-frequency = <400000>;
1789
1790                         status = "disabled";
1791                         #address-cells = <1>;
1792                         #size-cells = <0>;
1793                 };
1794
1795                 apcs_glb: mailbox@17911000 {
1796                         compatible = "qcom,msm8998-apcs-hmss-global";
1797                         reg = <0x17911000 0x1000>;
1798
1799                         #mbox-cells = <1>;
1800                 };
1801
1802                 timer@17920000 {
1803                         #address-cells = <1>;
1804                         #size-cells = <1>;
1805                         ranges;
1806                         compatible = "arm,armv7-timer-mem";
1807                         reg = <0x17920000 0x1000>;
1808
1809                         frame@17921000 {
1810                                 frame-number = <0>;
1811                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
1812                                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1813                                 reg = <0x17921000 0x1000>,
1814                                       <0x17922000 0x1000>;
1815                         };
1816
1817                         frame@17923000 {
1818                                 frame-number = <1>;
1819                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1820                                 reg = <0x17923000 0x1000>;
1821                                 status = "disabled";
1822                         };
1823
1824                         frame@17924000 {
1825                                 frame-number = <2>;
1826                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1827                                 reg = <0x17924000 0x1000>;
1828                                 status = "disabled";
1829                         };
1830
1831                         frame@17925000 {
1832                                 frame-number = <3>;
1833                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1834                                 reg = <0x17925000 0x1000>;
1835                                 status = "disabled";
1836                         };
1837
1838                         frame@17926000 {
1839                                 frame-number = <4>;
1840                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1841                                 reg = <0x17926000 0x1000>;
1842                                 status = "disabled";
1843                         };
1844
1845                         frame@17927000 {
1846                                 frame-number = <5>;
1847                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1848                                 reg = <0x17927000 0x1000>;
1849                                 status = "disabled";
1850                         };
1851
1852                         frame@17928000 {
1853                                 frame-number = <6>;
1854                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1855                                 reg = <0x17928000 0x1000>;
1856                                 status = "disabled";
1857                         };
1858                 };
1859
1860                 intc: interrupt-controller@17a00000 {
1861                         compatible = "arm,gic-v3";
1862                         reg = <0x17a00000 0x10000>,       /* GICD */
1863                               <0x17b00000 0x100000>;      /* GICR * 8 */
1864                         #interrupt-cells = <3>;
1865                         #address-cells = <1>;
1866                         #size-cells = <1>;
1867                         ranges;
1868                         interrupt-controller;
1869                         #redistributor-regions = <1>;
1870                         redistributor-stride = <0x0 0x20000>;
1871                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1872                 };
1873         };
1874 };
1875
1876 #include "msm8998-pins.dtsi"