sys/gnu/dts/arm64/qcom/qcs404.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 // Copyright (c) 2018, Linaro Limited
   3
   4 #include <dt-bindings/interrupt-controller/arm-gic.h>
   5 #include <dt-bindings/clock/qcom,gcc-qcs404.h>
   6 #include <dt-bindings/clock/qcom,turingcc-qcs404.h>
   7 #include <dt-bindings/clock/qcom,rpmcc.h>
   8 #include <dt-bindings/power/qcom-rpmpd.h>
   9 #include <dt-bindings/thermal/thermal.h>
  10
  11 / {
  12         interrupt-parent = <&intc>;
  13
  14         #address-cells = <2>;
  15         #size-cells = <2>;
  16
  17         chosen { };
  18
  19         clocks {
  20                 xo_board: xo-board {
  21                         compatible = "fixed-clock";
  22                         #clock-cells = <0>;
  23                         clock-frequency = <19200000>;
  24                 };
  25         };
  26
  27         cpus {
  28                 #address-cells = <1>;
  29                 #size-cells = <0>;
  30
  31                 CPU0: cpu@100 {
  32                         device_type = "cpu";
  33                         compatible = "arm,cortex-a53";
  34                         reg = <0x100>;
  35                         enable-method = "psci";
  36                         cpu-idle-states = <&CPU_SLEEP_0>;
  37                         next-level-cache = <&L2_0>;
  38                         #cooling-cells = <2>;
  39                 };
  40
  41                 CPU1: cpu@101 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a53";
  44                         reg = <0x101>;
  45                         enable-method = "psci";
  46                         cpu-idle-states = <&CPU_SLEEP_0>;
  47                         next-level-cache = <&L2_0>;
  48                         #cooling-cells = <2>;
  49                 };
  50
  51                 CPU2: cpu@102 {
  52                         device_type = "cpu";
  53                         compatible = "arm,cortex-a53";
  54                         reg = <0x102>;
  55                         enable-method = "psci";
  56                         cpu-idle-states = <&CPU_SLEEP_0>;
  57                         next-level-cache = <&L2_0>;
  58                         #cooling-cells = <2>;
  59                 };
  60
  61                 CPU3: cpu@103 {
  62                         device_type = "cpu";
  63                         compatible = "arm,cortex-a53";
  64                         reg = <0x103>;
  65                         enable-method = "psci";
  66                         cpu-idle-states = <&CPU_SLEEP_0>;
  67                         next-level-cache = <&L2_0>;
  68                         #cooling-cells = <2>;
  69                 };
  70
  71                 L2_0: l2-cache {
  72                         compatible = "cache";
  73                         cache-level = <2>;
  74                 };
  75
  76                 idle-states {
  77                         entry-method = "psci";
  78
  79                         CPU_SLEEP_0: cpu-sleep-0 {
  80                                 compatible = "arm,idle-state";
  81                                 idle-state-name = "standalone-power-collapse";
  82                                 arm,psci-suspend-param = <0x40000003>;
  83                                 entry-latency-us = <125>;
  84                                 exit-latency-us = <180>;
  85                                 min-residency-us = <595>;
  86                                 local-timer-stop;
  87                         };
  88                 };
  89         };
  90
  91         firmware {
  92                 scm: scm {
  93                         compatible = "qcom,scm-qcs404", "qcom,scm";
  94                         #reset-cells = <1>;
  95                 };
  96         };
  97
  98         memory@80000000 {
  99                 device_type = "memory";
 100                 /* We expect the bootloader to fill in the size */
 101                 reg = <0 0x80000000 0 0>;
 102         };
 103
 104         psci {
 105                 compatible = "arm,psci-1.0";
 106                 method = "smc";
 107         };
 108
 109         reserved-memory {
 110                 #address-cells = <2>;
 111                 #size-cells = <2>;
 112                 ranges;
 113
 114                 memory@85600000 {
 115                         reg = <0 0x85600000 0 0x90000>;
 116                         no-map;
 117                 };
 118
 119                 smem_region: memory@85f00000 {
 120                         reg = <0 0x85f00000 0 0x200000>;
 121                         no-map;
 122                 };
 123
 124                 memory@86100000 {
 125                         reg = <0 0x86100000 0 0x300000>;
 126                         no-map;
 127                 };
 128
 129                 wlan_fw_mem: memory@86400000 {
 130                         reg = <0 0x86400000 0 0x1c00000>;
 131                         no-map;
 132                 };
 133
 134                 adsp_fw_mem: memory@88000000 {
 135                         reg = <0 0x88000000 0 0x1a00000>;
 136                         no-map;
 137                 };
 138
 139                 cdsp_fw_mem: memory@89a00000 {
 140                         reg = <0 0x89a00000 0 0x600000>;
 141                         no-map;
 142                 };
 143
 144                 wlan_msa_mem: memory@8a000000 {
 145                         reg = <0 0x8a000000 0 0x100000>;
 146                         no-map;
 147                 };
 148         };
 149
 150         rpm-glink {
 151                 compatible = "qcom,glink-rpm";
 152
 153                 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
 154                 qcom,rpm-msg-ram = <&rpm_msg_ram>;
 155                 mboxes = <&apcs_glb 0>;
 156
 157                 rpm_requests: glink-channel {
 158                         compatible = "qcom,rpm-qcs404";
 159                         qcom,glink-channels = "rpm_requests";
 160
 161                         rpmcc: clock-controller {
 162                                 compatible = "qcom,rpmcc-qcs404";
 163                                 #clock-cells = <1>;
 164                         };
 165
 166                         rpmpd: power-controller {
 167                                 compatible = "qcom,qcs404-rpmpd";
 168                                 #power-domain-cells = <1>;
 169                                 operating-points-v2 = <&rpmpd_opp_table>;
 170
 171                                 rpmpd_opp_table: opp-table {
 172                                         compatible = "operating-points-v2";
 173
 174                                         rpmpd_opp_ret: opp1 {
 175                                                 opp-level = <16>;
 176                                         };
 177
 178                                         rpmpd_opp_ret_plus: opp2 {
 179                                                 opp-level = <32>;
 180                                         };
 181
 182                                         rpmpd_opp_min_svs: opp3 {
 183                                                 opp-level = <48>;
 184                                         };
 185
 186                                         rpmpd_opp_low_svs: opp4 {
 187                                                 opp-level = <64>;
 188                                         };
 189
 190                                         rpmpd_opp_svs: opp5 {
 191                                                 opp-level = <128>;
 192                                         };
 193
 194                                         rpmpd_opp_svs_plus: opp6 {
 195                                                 opp-level = <192>;
 196                                         };
 197
 198                                         rpmpd_opp_nom: opp7 {
 199                                                 opp-level = <256>;
 200                                         };
 201
 202                                         rpmpd_opp_nom_plus: opp8 {
 203                                                 opp-level = <320>;
 204                                         };
 205
 206                                         rpmpd_opp_turbo: opp9 {
 207                                                 opp-level = <384>;
 208                                         };
 209
 210                                         rpmpd_opp_turbo_no_cpr: opp10 {
 211                                                 opp-level = <416>;
 212                                         };
 213
 214                                         rpmpd_opp_turbo_plus: opp11 {
 215                                                 opp-level = <512>;
 216                                         };
 217                                 };
 218                         };
 219                 };
 220         };
 221
 222         smem {
 223                 compatible = "qcom,smem";
 224
 225                 memory-region = <&smem_region>;
 226                 qcom,rpm-msg-ram = <&rpm_msg_ram>;
 227
 228                 hwlocks = <&tcsr_mutex 3>;
 229         };
 230
 231         tcsr_mutex: hwlock {
 232                 compatible = "qcom,tcsr-mutex";
 233                 syscon = <&tcsr_mutex_regs 0 0x1000>;
 234                 #hwlock-cells = <1>;
 235         };
 236
 237         soc: soc@0 {
 238                 #address-cells = <1>;
 239                 #size-cells = <1>;
 240                 ranges = <0 0 0 0xffffffff>;
 241                 compatible = "simple-bus";
 242
 243                 turingcc: clock-controller@800000 {
 244                         compatible = "qcom,qcs404-turingcc";
 245                         reg = <0x00800000 0x30000>;
 246                         clocks = <&gcc GCC_CDSP_CFG_AHB_CLK>;
 247
 248                         #clock-cells = <1>;
 249                         #reset-cells = <1>;
 250
 251                         status = "disabled";
 252                 };
 253
 254                 rpm_msg_ram: memory@60000 {
 255                         compatible = "qcom,rpm-msg-ram";
 256                         reg = <0x00060000 0x6000>;
 257                 };
 258
 259                 qfprom: qfprom@a4000 {
 260                         compatible = "qcom,qfprom";
 261                         reg = <0x000a4000 0x1000>;
 262                         #address-cells = <1>;
 263                         #size-cells = <1>;
 264                         tsens_caldata: caldata@d0 {
 265                                 reg = <0x1f8 0x14>;
 266                         };
 267                 };
 268
 269                 rng: rng@e3000 {
 270                         compatible = "qcom,prng-ee";
 271                         reg = <0x000e3000 0x1000>;
 272                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 273                         clock-names = "core";
 274                 };
 275
 276                 tsens: thermal-sensor@4a9000 {
 277                         compatible = "qcom,qcs404-tsens", "qcom,tsens-v1";
 278                         reg = <0x004a9000 0x1000>, /* TM */
 279                               <0x004a8000 0x1000>; /* SROT */
 280                         nvmem-cells = <&tsens_caldata>;
 281                         nvmem-cell-names = "calib";
 282                         #qcom,sensors = <10>;
 283                         #thermal-sensor-cells = <1>;
 284                 };
 285
 286                 remoteproc_cdsp: remoteproc@b00000 {
 287                         compatible = "qcom,qcs404-cdsp-pas";
 288                         reg = <0x00b00000 0x4040>;
 289
 290                         interrupts-extended = <&intc GIC_SPI 229 IRQ_TYPE_EDGE_RISING>,
 291                                               <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
 292                                               <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
 293                                               <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
 294                                               <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
 295                         interrupt-names = "wdog", "fatal", "ready",
 296                                           "handover", "stop-ack";
 297
 298                         clocks = <&xo_board>,
 299                                  <&gcc GCC_CDSP_CFG_AHB_CLK>,
 300                                  <&gcc GCC_CDSP_TBU_CLK>,
 301                                  <&gcc GCC_BIMC_CDSP_CLK>,
 302                                  <&turingcc TURING_WRAPPER_AON_CLK>,
 303                                  <&turingcc TURING_Q6SS_AHBS_AON_CLK>,
 304                                  <&turingcc TURING_Q6SS_AHBM_AON_CLK>,
 305                                  <&turingcc TURING_Q6SS_Q6_AXIM_CLK>;
 306                         clock-names = "xo",
 307                                       "sway",
 308                                       "tbu",
 309                                       "bimc",
 310                                       "ahb_aon",
 311                                       "q6ss_slave",
 312                                       "q6ss_master",
 313                                       "q6_axim";
 314
 315                         resets = <&gcc GCC_CDSP_RESTART>;
 316                         reset-names = "restart";
 317
 318                         qcom,halt-regs = <&tcsr 0x19004>;
 319
 320                         memory-region = <&cdsp_fw_mem>;
 321
 322                         qcom,smem-states = <&cdsp_smp2p_out 0>;
 323                         qcom,smem-state-names = "stop";
 324
 325                         status = "disabled";
 326
 327                         glink-edge {
 328                                 interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>;
 329
 330                                 qcom,remote-pid = <5>;
 331                                 mboxes = <&apcs_glb 12>;
 332
 333                                 label = "cdsp";
 334                         };
 335                 };
 336
 337                 tlmm: pinctrl@1000000 {
 338                         compatible = "qcom,qcs404-pinctrl";
 339                         reg = <0x01000000 0x200000>,
 340                               <0x01300000 0x200000>,
 341                               <0x07b00000 0x200000>;
 342                         reg-names = "south", "north", "east";
 343                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 344                         gpio-ranges = <&tlmm 0 0 120>;
 345                         gpio-controller;
 346                         #gpio-cells = <2>;
 347                         interrupt-controller;
 348                         #interrupt-cells = <2>;
 349
 350                         blsp1_i2c0_default: blsp1-i2c0-default {
 351                                 pins = "gpio32", "gpio33";
 352                                 function = "blsp_i2c0";
 353                         };
 354
 355                         blsp1_i2c1_default: blsp1-i2c1-default {
 356                                 pins = "gpio24", "gpio25";
 357                                 function = "blsp_i2c1";
 358                         };
 359
 360                         blsp1_i2c2_default: blsp1-i2c2-default {
 361                                 sda {
 362                                         pins = "gpio19";
 363                                         function = "blsp_i2c_sda_a2";
 364                                 };
 365
 366                                 scl {
 367                                         pins = "gpio20";
 368                                         function = "blsp_i2c_scl_a2";
 369                                 };
 370                         };
 371
 372                         blsp1_i2c3_default: blsp1-i2c3-default {
 373                                 pins = "gpio84", "gpio85";
 374                                 function = "blsp_i2c3";
 375                         };
 376
 377                         blsp1_i2c4_default: blsp1-i2c4-default {
 378                                 pins = "gpio117", "gpio118";
 379                                 function = "blsp_i2c4";
 380                         };
 381
 382                         blsp1_uart0_default: blsp1-uart0-default {
 383                                 pins = "gpio30", "gpio31", "gpio32", "gpio33";
 384                                 function = "blsp_uart0";
 385                         };
 386
 387                         blsp1_uart1_default: blsp1-uart1-default {
 388                                 pins = "gpio22", "gpio23";
 389                                 function = "blsp_uart1";
 390                         };
 391
 392                         blsp1_uart2_default: blsp1-uart2-default {
 393                                 rx {
 394                                         pins = "gpio18";
 395                                         function = "blsp_uart_rx_a2";
 396                                 };
 397
 398                                 tx {
 399                                         pins = "gpio17";
 400                                         function = "blsp_uart_tx_a2";
 401                                 };
 402                         };
 403
 404                         blsp1_uart3_default: blsp1-uart3-default {
 405                                 pins = "gpio82", "gpio83", "gpio84", "gpio85";
 406                                 function = "blsp_uart3";
 407                         };
 408
 409                         blsp2_i2c0_default: blsp2-i2c0-default {
 410                                 pins = "gpio28", "gpio29";
 411                                 function = "blsp_i2c5";
 412                         };
 413
 414                         blsp1_spi0_default: blsp1-spi0-default {
 415                                 pins = "gpio30", "gpio31", "gpio32", "gpio33";
 416                                 function = "blsp_spi0";
 417                         };
 418
 419                         blsp1_spi1_default: blsp1-spi1-default {
 420                                 pins = "gpio22", "gpio23", "gpio24", "gpio25";
 421                                 function = "blsp_spi1";
 422                         };
 423
 424                         blsp1_spi2_default: blsp1-spi2-default {
 425                                 pins = "gpio17", "gpio18", "gpio19", "gpio20";
 426                                 function = "blsp_spi2";
 427                         };
 428
 429                         blsp1_spi3_default: blsp1-spi3-default {
 430                                 pins = "gpio82", "gpio83", "gpio84", "gpio85";
 431                                 function = "blsp_spi3";
 432                         };
 433
 434                         blsp1_spi4_default: blsp1-spi4-default {
 435                                 pins = "gpio37", "gpio38", "gpio117", "gpio118";
 436                                 function = "blsp_spi4";
 437                         };
 438
 439                         blsp2_spi0_default: blsp2-spi0-default {
 440                                 pins = "gpio26", "gpio27", "gpio28", "gpio29";
 441                                 function = "blsp_spi5";
 442                         };
 443
 444                         blsp2_uart0_default: blsp2-uart0-default {
 445                                 pins = "gpio26", "gpio27", "gpio28", "gpio29";
 446                                 function = "blsp_uart5";
 447                         };
 448                 };
 449
 450                 gcc: clock-controller@1800000 {
 451                         compatible = "qcom,gcc-qcs404";
 452                         reg = <0x01800000 0x80000>;
 453                         #clock-cells = <1>;
 454                         #reset-cells = <1>;
 455
 456                         assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>;
 457                         assigned-clock-rates = <19200000>;
 458                 };
 459
 460                 tcsr_mutex_regs: syscon@1905000 {
 461                         compatible = "syscon";
 462                         reg = <0x01905000 0x20000>;
 463                 };
 464
 465                 tcsr: syscon@1937000 {
 466                         compatible = "syscon";
 467                         reg = <0x01937000 0x25000>;
 468                 };
 469
 470                 spmi_bus: spmi@200f000 {
 471                         compatible = "qcom,spmi-pmic-arb";
 472                         reg = <0x0200f000 0x001000>,
 473                               <0x02400000 0x800000>,
 474                               <0x02c00000 0x800000>,
 475                               <0x03800000 0x200000>,
 476                               <0x0200a000 0x002100>;
 477                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
 478                         interrupt-names = "periph_irq";
 479                         interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
 480                         qcom,ee = <0>;
 481                         qcom,channel = <0>;
 482                         #address-cells = <2>;
 483                         #size-cells = <0>;
 484                         interrupt-controller;
 485                         #interrupt-cells = <4>;
 486                 };
 487
 488                 remoteproc_wcss: remoteproc@7400000 {
 489                         compatible = "qcom,qcs404-wcss-pas";
 490                         reg = <0x07400000 0x4040>;
 491
 492                         interrupts-extended = <&intc GIC_SPI 153 IRQ_TYPE_EDGE_RISING>,
 493                                               <&wcss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
 494                                               <&wcss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
 495                                               <&wcss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
 496                                               <&wcss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
 497                         interrupt-names = "wdog", "fatal", "ready",
 498                                           "handover", "stop-ack";
 499
 500                         clocks = <&xo_board>;
 501                         clock-names = "xo";
 502
 503                         memory-region = <&wlan_fw_mem>;
 504
 505                         qcom,smem-states = <&wcss_smp2p_out 0>;
 506                         qcom,smem-state-names = "stop";
 507
 508                         status = "disabled";
 509
 510                         glink-edge {
 511                                 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
 512
 513                                 qcom,remote-pid = <1>;
 514                                 mboxes = <&apcs_glb 16>;
 515
 516                                 label = "wcss";
 517                         };
 518                 };
 519
 520                 pcie_phy: phy@7786000 {
 521                         compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy";
 522                         reg = <0x07786000 0xb8>;
 523
 524                         clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
 525                         resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>,
 526                                  <&gcc 21>;
 527                         reset-names = "phy", "pipe";
 528
 529                         clock-output-names = "pcie_0_pipe_clk";
 530                         #phy-cells = <0>;
 531
 532                         status = "disabled";
 533                 };
 534
 535                 sdcc1: sdcc@7804000 {
 536                         compatible = "qcom,sdhci-msm-v5";
 537                         reg = <0x07804000 0x1000>, <0x7805000 0x1000>;
 538                         reg-names = "hc_mem", "cmdq_mem";
 539
 540                         interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
 541                                      <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
 542                         interrupt-names = "hc_irq", "pwr_irq";
 543
 544                         clocks = <&gcc GCC_SDCC1_APPS_CLK>,
 545                                  <&gcc GCC_SDCC1_AHB_CLK>,
 546                                  <&xo_board>;
 547                         clock-names = "core", "iface", "xo";
 548
 549                         status = "disabled";
 550                 };
 551
 552                 blsp1_dma: dma@7884000 {
 553                         compatible = "qcom,bam-v1.7.0";
 554                         reg = <0x07884000 0x25000>;
 555                         interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
 556                         clocks = <&gcc GCC_BLSP1_AHB_CLK>;
 557                         clock-names = "bam_clk";
 558                         #dma-cells = <1>;
 559                         qcom,ee = <0>;
 560                         status = "okay";
 561                 };
 562
 563                 blsp1_uart0: serial@78af000 {
 564                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 565                         reg = <0x078af000 0x200>;
 566                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 567                         clocks = <&gcc GCC_BLSP1_UART0_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 568                         clock-names = "core", "iface";
 569                         dmas = <&blsp1_dma 1>, <&blsp1_dma 0>;
 570                         dma-names = "rx", "tx";
 571                         pinctrl-names = "default";
 572                         pinctrl-0 = <&blsp1_uart0_default>;
 573                         status = "disabled";
 574                 };
 575
 576                 blsp1_uart1: serial@78b0000 {
 577                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 578                         reg = <0x078b0000 0x200>;
 579                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 580                         clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 581                         clock-names = "core", "iface";
 582                         dmas = <&blsp1_dma 3>, <&blsp1_dma 2>;
 583                         dma-names = "rx", "tx";
 584                         pinctrl-names = "default";
 585                         pinctrl-0 = <&blsp1_uart1_default>;
 586                         status = "disabled";
 587                 };
 588
 589                 blsp1_uart2: serial@78b1000 {
 590                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 591                         reg = <0x078b1000 0x200>;
 592                         interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
 593                         clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 594                         clock-names = "core", "iface";
 595                         dmas = <&blsp1_dma 5>, <&blsp1_dma 4>;
 596                         dma-names = "rx", "tx";
 597                         pinctrl-names = "default";
 598                         pinctrl-0 = <&blsp1_uart2_default>;
 599                         status = "okay";
 600                 };
 601
 602                 ethernet: ethernet@7a80000 {
 603                         compatible = "qcom,qcs404-ethqos";
 604                         reg = <0x07a80000 0x10000>,
 605                                 <0x07a96000 0x100>;
 606                         reg-names = "stmmaceth", "rgmii";
 607                         clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii";
 608                         clocks = <&gcc GCC_ETH_AXI_CLK>,
 609                                 <&gcc GCC_ETH_SLAVE_AHB_CLK>,
 610                                 <&gcc GCC_ETH_PTP_CLK>,
 611                                 <&gcc GCC_ETH_RGMII_CLK>;
 612                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
 613                                         <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 614                         interrupt-names = "macirq", "eth_lpi";
 615
 616                         snps,tso;
 617                         rx-fifo-depth = <4096>;
 618                         tx-fifo-depth = <4096>;
 619
 620                         status = "disabled";
 621                 };
 622
 623                 wifi: wifi@a000000 {
 624                         compatible = "qcom,wcn3990-wifi";
 625                         reg = <0xa000000 0x800000>;
 626                         reg-names = "membase";
 627                         memory-region = <&wlan_msa_mem>;
 628                         interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
 629                                      <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
 630                                      <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
 631                                      <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
 632                                      <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
 633                                      <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
 634                                      <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
 635                                      <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
 636                                      <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>,
 637                                      <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
 638                                      <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>,
 639                                      <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
 640                         status = "disabled";
 641                 };
 642
 643                 blsp1_uart3: serial@78b2000 {
 644                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 645                         reg = <0x078b2000 0x200>;
 646                         interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 647                         clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 648                         clock-names = "core", "iface";
 649                         dmas = <&blsp1_dma 7>, <&blsp1_dma 6>;
 650                         dma-names = "rx", "tx";
 651                         pinctrl-names = "default";
 652                         pinctrl-0 = <&blsp1_uart3_default>;
 653                         status = "disabled";
 654                 };
 655
 656                 blsp1_i2c0: i2c@78b5000 {
 657                         compatible = "qcom,i2c-qup-v2.2.1";
 658                         reg = <0x078b5000 0x600>;
 659                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 660                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 661                                  <&gcc GCC_BLSP1_QUP0_I2C_APPS_CLK>;
 662                         clock-names = "iface", "core";
 663                         pinctrl-names = "default";
 664                         pinctrl-0 = <&blsp1_i2c0_default>;
 665                         #address-cells = <1>;
 666                         #size-cells = <0>;
 667                         status = "disabled";
 668                 };
 669
 670                 blsp1_spi0: spi@78b5000 {
 671                         compatible = "qcom,spi-qup-v2.2.1";
 672                         reg = <0x078b5000 0x600>;
 673                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 674                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 675                                  <&gcc GCC_BLSP1_QUP0_SPI_APPS_CLK>;
 676                         clock-names = "iface", "core";
 677                         pinctrl-names = "default";
 678                         pinctrl-0 = <&blsp1_spi0_default>;
 679                         #address-cells = <1>;
 680                         #size-cells = <0>;
 681                         status = "disabled";
 682                 };
 683
 684                 blsp1_i2c1: i2c@78b6000 {
 685                         compatible = "qcom,i2c-qup-v2.2.1";
 686                         reg = <0x078b6000 0x600>;
 687                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 688                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 689                                  <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
 690                         clock-names = "iface", "core";
 691                         pinctrl-names = "default";
 692                         pinctrl-0 = <&blsp1_i2c1_default>;
 693                         #address-cells = <1>;
 694                         #size-cells = <0>;
 695                         status = "disabled";
 696                 };
 697
 698                 blsp1_spi1: spi@78b6000 {
 699                         compatible = "qcom,spi-qup-v2.2.1";
 700                         reg = <0x078b6000 0x600>;
 701                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 702                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 703                                  <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>;
 704                         clock-names = "iface", "core";
 705                         pinctrl-names = "default";
 706                         pinctrl-0 = <&blsp1_spi1_default>;
 707                         #address-cells = <1>;
 708                         #size-cells = <0>;
 709                         status = "disabled";
 710                 };
 711
 712                 blsp1_i2c2: i2c@78b7000 {
 713                         compatible = "qcom,i2c-qup-v2.2.1";
 714                         reg = <0x078b7000 0x600>;
 715                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 716                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 717                                  <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
 718                         clock-names = "iface", "core";
 719                         pinctrl-names = "default";
 720                         pinctrl-0 = <&blsp1_i2c2_default>;
 721                         #address-cells = <1>;
 722                         #size-cells = <0>;
 723                         status = "disabled";
 724                 };
 725
 726                 blsp1_spi2: spi@78b7000 {
 727                         compatible = "qcom,spi-qup-v2.2.1";
 728                         reg = <0x078b7000 0x600>;
 729                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 730                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 731                                  <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>;
 732                         clock-names = "iface", "core";
 733                         pinctrl-names = "default";
 734                         pinctrl-0 = <&blsp1_spi2_default>;
 735                         #address-cells = <1>;
 736                         #size-cells = <0>;
 737                         status = "disabled";
 738                 };
 739
 740                 blsp1_i2c3: i2c@78b8000 {
 741                         compatible = "qcom,i2c-qup-v2.2.1";
 742                         reg = <0x078b8000 0x600>;
 743                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 744                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 745                                  <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
 746                         clock-names = "iface", "core";
 747                         pinctrl-names = "default";
 748                         pinctrl-0 = <&blsp1_i2c3_default>;
 749                         #address-cells = <1>;
 750                         #size-cells = <0>;
 751                         status = "disabled";
 752                 };
 753
 754                 blsp1_spi3: spi@78b8000 {
 755                         compatible = "qcom,spi-qup-v2.2.1";
 756                         reg = <0x078b8000 0x600>;
 757                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 758                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 759                                  <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>;
 760                         clock-names = "iface", "core";
 761                         pinctrl-names = "default";
 762                         pinctrl-0 = <&blsp1_spi3_default>;
 763                         #address-cells = <1>;
 764                         #size-cells = <0>;
 765                         status = "disabled";
 766                 };
 767
 768                 blsp1_i2c4: i2c@78b9000 {
 769                         compatible = "qcom,i2c-qup-v2.2.1";
 770                         reg = <0x078b9000 0x600>;
 771                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 772                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 773                                  <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
 774                         clock-names = "iface", "core";
 775                         pinctrl-names = "default";
 776                         pinctrl-0 = <&blsp1_i2c4_default>;
 777                         #address-cells = <1>;
 778                         #size-cells = <0>;
 779                         status = "disabled";
 780                 };
 781
 782                 blsp1_spi4: spi@78b9000 {
 783                         compatible = "qcom,spi-qup-v2.2.1";
 784                         reg = <0x078b9000 0x600>;
 785                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 786                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 787                                  <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>;
 788                         clock-names = "iface", "core";
 789                         pinctrl-names = "default";
 790                         pinctrl-0 = <&blsp1_spi4_default>;
 791                         #address-cells = <1>;
 792                         #size-cells = <0>;
 793                         status = "disabled";
 794                 };
 795
 796                 blsp2_dma: dma@7ac4000 {
 797                         compatible = "qcom,bam-v1.7.0";
 798                         reg = <0x07ac4000 0x17000>;
 799                         interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
 800                         clocks = <&gcc GCC_BLSP2_AHB_CLK>;
 801                         clock-names = "bam_clk";
 802                         #dma-cells = <1>;
 803                         qcom,ee = <0>;
 804                         status = "disabled";
 805                 };
 806
 807                 blsp2_uart0: serial@7aef000 {
 808                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 809                         reg = <0x07aef000 0x200>;
 810                         interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
 811                         clocks = <&gcc GCC_BLSP2_UART0_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
 812                         clock-names = "core", "iface";
 813                         dmas = <&blsp2_dma 1>, <&blsp2_dma 0>;
 814                         dma-names = "rx", "tx";
 815                         pinctrl-names = "default";
 816                         pinctrl-0 = <&blsp2_uart0_default>;
 817                         status = "disabled";
 818                 };
 819
 820                 blsp2_i2c0: i2c@7af5000 {
 821                         compatible = "qcom,i2c-qup-v2.2.1";
 822                         reg = <0x07af5000 0x600>;
 823                         interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
 824                         clocks = <&gcc GCC_BLSP2_AHB_CLK>,
 825                                  <&gcc GCC_BLSP2_QUP0_I2C_APPS_CLK>;
 826                         clock-names = "iface", "core";
 827                         pinctrl-names = "default";
 828                         pinctrl-0 = <&blsp2_i2c0_default>;
 829                         #address-cells = <1>;
 830                         #size-cells = <0>;
 831                         status = "disabled";
 832                 };
 833
 834                 blsp2_spi0: spi@7af5000 {
 835                         compatible = "qcom,spi-qup-v2.2.1";
 836                         reg = <0x07af5000 0x600>;
 837                         interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
 838                         clocks = <&gcc GCC_BLSP2_AHB_CLK>,
 839                                  <&gcc GCC_BLSP2_QUP0_SPI_APPS_CLK>;
 840                         clock-names = "iface", "core";
 841                         pinctrl-names = "default";
 842                         pinctrl-0 = <&blsp2_spi0_default>;
 843                         #address-cells = <1>;
 844                         #size-cells = <0>;
 845                         status = "disabled";
 846                 };
 847
 848                 intc: interrupt-controller@b000000 {
 849                         compatible = "qcom,msm-qgic2";
 850                         interrupt-controller;
 851                         #interrupt-cells = <3>;
 852                         reg = <0x0b000000 0x1000>,
 853                               <0x0b002000 0x1000>;
 854                 };
 855
 856                 apcs_glb: mailbox@b011000 {
 857                         compatible = "qcom,qcs404-apcs-apps-global", "syscon";
 858                         reg = <0x0b011000 0x1000>;
 859                         #mbox-cells = <1>;
 860                 };
 861
 862                 timer@b120000 {
 863                         #address-cells = <1>;
 864                         #size-cells = <1>;
 865                         ranges;
 866                         compatible = "arm,armv7-timer-mem";
 867                         reg = <0x0b120000 0x1000>;
 868                         clock-frequency = <19200000>;
 869
 870                         frame@b121000 {
 871                                 frame-number = <0>;
 872                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 873                                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 874                                 reg = <0x0b121000 0x1000>,
 875                                       <0x0b122000 0x1000>;
 876                         };
 877
 878                         frame@b123000 {
 879                                 frame-number = <1>;
 880                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 881                                 reg = <0x0b123000 0x1000>;
 882                                 status = "disabled";
 883                         };
 884
 885                         frame@b124000 {
 886                                 frame-number = <2>;
 887                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 888                                 reg = <0x0b124000 0x1000>;
 889                                 status = "disabled";
 890                         };
 891
 892                         frame@b125000 {
 893                                 frame-number = <3>;
 894                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 895                                 reg = <0x0b125000 0x1000>;
 896                                 status = "disabled";
 897                         };
 898
 899                         frame@b126000 {
 900                                 frame-number = <4>;
 901                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 902                                 reg = <0x0b126000 0x1000>;
 903                                 status = "disabled";
 904                         };
 905
 906                         frame@b127000 {
 907                                 frame-number = <5>;
 908                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 909                                 reg = <0xb127000 0x1000>;
 910                                 status = "disabled";
 911                         };
 912
 913                         frame@b128000 {
 914                                 frame-number = <6>;
 915                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 916                                 reg = <0x0b128000 0x1000>;
 917                                 status = "disabled";
 918                         };
 919                 };
 920
 921                 remoteproc_adsp: remoteproc@c700000 {
 922                         compatible = "qcom,qcs404-adsp-pas";
 923                         reg = <0x0c700000 0x4040>;
 924
 925                         interrupts-extended = <&intc GIC_SPI 293 IRQ_TYPE_EDGE_RISING>,
 926                                               <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
 927                                               <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
 928                                               <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
 929                                               <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
 930                         interrupt-names = "wdog", "fatal", "ready",
 931                                           "handover", "stop-ack";
 932
 933                         clocks = <&xo_board>;
 934                         clock-names = "xo";
 935
 936                         memory-region = <&adsp_fw_mem>;
 937
 938                         qcom,smem-states = <&adsp_smp2p_out 0>;
 939                         qcom,smem-state-names = "stop";
 940
 941                         status = "disabled";
 942
 943                         glink-edge {
 944                                 interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>;
 945
 946                                 qcom,remote-pid = <2>;
 947                                 mboxes = <&apcs_glb 8>;
 948
 949                                 label = "adsp";
 950                         };
 951                 };
 952
 953                 pcie: pci@10000000 {
 954                         compatible = "qcom,pcie-qcs404", "snps,dw-pcie";
 955                         reg =  <0x10000000 0xf1d>,
 956                                <0x10000f20 0xa8>,
 957                                <0x07780000 0x2000>,
 958                                <0x10001000 0x2000>;
 959                         reg-names = "dbi", "elbi", "parf", "config";
 960                         device_type = "pci";
 961                         linux,pci-domain = <0>;
 962                         bus-range = <0x00 0xff>;
 963                         num-lanes = <1>;
 964                         #address-cells = <3>;
 965                         #size-cells = <2>;
 966
 967                         ranges = <0x81000000 0 0          0x10003000 0 0x00010000>, /* I/O */
 968                                  <0x82000000 0 0x10013000 0x10013000 0 0x007ed000>; /* memory */
 969
 970                         interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
 971                         interrupt-names = "msi";
 972                         #interrupt-cells = <1>;
 973                         interrupt-map-mask = <0 0 0 0x7>;
 974                         interrupt-map = <0 0 0 1 &intc GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 975                                         <0 0 0 2 &intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 976                                         <0 0 0 3 &intc GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 977                                         <0 0 0 4 &intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 978                         clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
 979                                  <&gcc GCC_PCIE_0_AUX_CLK>,
 980                                  <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
 981                                  <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
 982                         clock-names = "iface", "aux", "master_bus", "slave_bus";
 983
 984                         resets = <&gcc 18>,
 985                                  <&gcc 17>,
 986                                  <&gcc 15>,
 987                                  <&gcc 19>,
 988                                  <&gcc GCC_PCIE_0_BCR>,
 989                                  <&gcc 16>;
 990                         reset-names = "axi_m",
 991                                       "axi_s",
 992                                       "axi_m_sticky",
 993                                       "pipe_sticky",
 994                                       "pwr",
 995                                       "ahb";
 996
 997                         phys = <&pcie_phy>;
 998                         phy-names = "pciephy";
 999
1000                         status = "disabled";
1001                 };
1002         };
1003
1004         timer {
1005                 compatible = "arm,armv8-timer";
1006                 interrupts = <GIC_PPI 2 0xff08>,
1007                              <GIC_PPI 3 0xff08>,
1008                              <GIC_PPI 4 0xff08>,
1009                              <GIC_PPI 1 0xff08>;
1010         };
1011
1012         smp2p-adsp {
1013                 compatible = "qcom,smp2p";
1014                 qcom,smem = <443>, <429>;
1015                 interrupts = <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>;
1016                 mboxes = <&apcs_glb 10>;
1017                 qcom,local-pid = <0>;
1018                 qcom,remote-pid = <2>;
1019
1020                 adsp_smp2p_out: master-kernel {
1021                         qcom,entry-name = "master-kernel";
1022                         #qcom,smem-state-cells = <1>;
1023                 };
1024
1025                 adsp_smp2p_in: slave-kernel {
1026                         qcom,entry-name = "slave-kernel";
1027                         interrupt-controller;
1028                         #interrupt-cells = <2>;
1029                 };
1030         };
1031
1032         smp2p-cdsp {
1033                 compatible = "qcom,smp2p";
1034                 qcom,smem = <94>, <432>;
1035                 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
1036                 mboxes = <&apcs_glb 14>;
1037                 qcom,local-pid = <0>;
1038                 qcom,remote-pid = <5>;
1039
1040                 cdsp_smp2p_out: master-kernel {
1041                         qcom,entry-name = "master-kernel";
1042                         #qcom,smem-state-cells = <1>;
1043                 };
1044
1045                 cdsp_smp2p_in: slave-kernel {
1046                         qcom,entry-name = "slave-kernel";
1047                         interrupt-controller;
1048                         #interrupt-cells = <2>;
1049                 };
1050         };
1051
1052         smp2p-wcss {
1053                 compatible = "qcom,smp2p";
1054                 qcom,smem = <435>, <428>;
1055                 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
1056                 mboxes = <&apcs_glb 18>;
1057                 qcom,local-pid = <0>;
1058                 qcom,remote-pid = <1>;
1059
1060                 wcss_smp2p_out: master-kernel {
1061                         qcom,entry-name = "master-kernel";
1062                         #qcom,smem-state-cells = <1>;
1063                 };
1064
1065                 wcss_smp2p_in: slave-kernel {
1066                         qcom,entry-name = "slave-kernel";
1067                         interrupt-controller;
1068                         #interrupt-cells = <2>;
1069                 };
1070         };
1071
1072         thermal-zones {
1073                 aoss-thermal {
1074                         polling-delay-passive = <250>;
1075                         polling-delay = <1000>;
1076
1077                         thermal-sensors = <&tsens 0>;
1078
1079                         trips {
1080                                 aoss_alert0: trip-point@0 {
1081                                         temperature = <105000>;
1082                                         hysteresis = <2000>;
1083                                         type = "hot";
1084                                 };
1085                         };
1086                 };
1087
1088                 q6-hvx-thermal {
1089                         polling-delay-passive = <250>;
1090                         polling-delay = <1000>;
1091
1092                         thermal-sensors = <&tsens 1>;
1093
1094                         trips {
1095                                 q6_hvx_alert0: trip-point@0 {
1096                                         temperature = <105000>;
1097                                         hysteresis = <2000>;
1098                                         type = "hot";
1099                                 };
1100                         };
1101                 };
1102
1103                 lpass-thermal {
1104                         polling-delay-passive = <250>;
1105                         polling-delay = <1000>;
1106
1107                         thermal-sensors = <&tsens 2>;
1108
1109                         trips {
1110                                 lpass_alert0: trip-point@0 {
1111                                         temperature = <105000>;
1112                                         hysteresis = <2000>;
1113                                         type = "hot";
1114                                 };
1115                         };
1116                 };
1117
1118                 wlan-thermal {
1119                         polling-delay-passive = <250>;
1120                         polling-delay = <1000>;
1121
1122                         thermal-sensors = <&tsens 3>;
1123
1124                         trips {
1125                                 wlan_alert0: trip-point@0 {
1126                                         temperature = <105000>;
1127                                         hysteresis = <2000>;
1128                                         type = "hot";
1129                                 };
1130                         };
1131                 };
1132
1133                 cluster-thermal {
1134                         polling-delay-passive = <250>;
1135                         polling-delay = <1000>;
1136
1137                         thermal-sensors = <&tsens 4>;
1138
1139                         trips {
1140                                 cluster_alert0: trip-point@0 {
1141                                         temperature = <95000>;
1142                                         hysteresis = <2000>;
1143                                         type = "hot";
1144                                 };
1145                                 cluster_alert1: trip-point@1 {
1146                                         temperature = <105000>;
1147                                         hysteresis = <2000>;
1148                                         type = "passive";
1149                                 };
1150                                 cluster_crit: cluster_crit {
1151                                         temperature = <120000>;
1152                                         hysteresis = <2000>;
1153                                         type = "critical";
1154                                 };
1155                         };
1156                         cooling-maps {
1157                                 map0 {
1158                                         trip = <&cluster_alert1>;
1159                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1160                                                        <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1161                                                        <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1162                                                        <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1163                                 };
1164                         };
1165                 };
1166
1167                 cpu0-thermal {
1168                         polling-delay-passive = <250>;
1169                         polling-delay = <1000>;
1170
1171                         thermal-sensors = <&tsens 5>;
1172
1173                         trips {
1174                                 cpu0_alert0: trip-point@0 {
1175                                         temperature = <95000>;
1176                                         hysteresis = <2000>;
1177                                         type = "hot";
1178                                 };
1179                                 cpu0_alert1: trip-point@1 {
1180                                         temperature = <105000>;
1181                                         hysteresis = <2000>;
1182                                         type = "passive";
1183                                 };
1184                                 cpu0_crit: cpu_crit {
1185                                         temperature = <120000>;
1186                                         hysteresis = <2000>;
1187                                         type = "critical";
1188                                 };
1189                         };
1190                         cooling-maps {
1191                                 map0 {
1192                                         trip = <&cpu0_alert1>;
1193                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1194                                                        <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1195                                                        <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1196                                                        <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1197                                 };
1198                         };
1199                 };
1200
1201                 cpu1-thermal {
1202                         polling-delay-passive = <250>;
1203                         polling-delay = <1000>;
1204
1205                         thermal-sensors = <&tsens 6>;
1206
1207                         trips {
1208                                 cpu1_alert0: trip-point@0 {
1209                                         temperature = <95000>;
1210                                         hysteresis = <2000>;
1211                                         type = "hot";
1212                                 };
1213                                 cpu1_alert1: trip-point@1 {
1214                                         temperature = <105000>;
1215                                         hysteresis = <2000>;
1216                                         type = "passive";
1217                                 };
1218                                 cpu1_crit: cpu_crit {
1219                                         temperature = <120000>;
1220                                         hysteresis = <2000>;
1221                                         type = "critical";
1222                                 };
1223                         };
1224                         cooling-maps {
1225                                 map0 {
1226                                         trip = <&cpu1_alert1>;
1227                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1228                                                        <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1229                                                        <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1230                                                        <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1231                                 };
1232                         };
1233                 };
1234
1235                 cpu2-thermal {
1236                         polling-delay-passive = <250>;
1237                         polling-delay = <1000>;
1238
1239                         thermal-sensors = <&tsens 7>;
1240
1241                         trips {
1242                                 cpu2_alert0: trip-point@0 {
1243                                         temperature = <95000>;
1244                                         hysteresis = <2000>;
1245                                         type = "hot";
1246                                 };
1247                                 cpu2_alert1: trip-point@1 {
1248                                         temperature = <105000>;
1249                                         hysteresis = <2000>;
1250                                         type = "passive";
1251                                 };
1252                                 cpu2_crit: cpu_crit {
1253                                         temperature = <120000>;
1254                                         hysteresis = <2000>;
1255                                         type = "critical";
1256                                 };
1257                         };
1258                         cooling-maps {
1259                                 map0 {
1260                                         trip = <&cpu2_alert1>;
1261                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1262                                                        <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1263                                                        <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1264                                                        <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1265                                 };
1266                         };
1267                 };
1268
1269                 cpu3-thermal {
1270                         polling-delay-passive = <250>;
1271                         polling-delay = <1000>;
1272
1273                         thermal-sensors = <&tsens 8>;
1274
1275                         trips {
1276                                 cpu3_alert0: trip-point@0 {
1277                                         temperature = <95000>;
1278                                         hysteresis = <2000>;
1279                                         type = "hot";
1280                                 };
1281                                 cpu3_alert1: trip-point@1 {
1282                                         temperature = <105000>;
1283                                         hysteresis = <2000>;
1284                                         type = "passive";
1285                                 };
1286                                 cpu3_crit: cpu_crit {
1287                                         temperature = <120000>;
1288                                         hysteresis = <2000>;
1289                                         type = "critical";
1290                                 };
1291                         };
1292                         cooling-maps {
1293                                 map0 {
1294                                         trip = <&cpu3_alert1>;
1295                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1296                                                        <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1297                                                        <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1298                                                        <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1299                                 };
1300                         };
1301                 };
1302
1303                 gpu-thermal {
1304                         polling-delay-passive = <250>;
1305                         polling-delay = <1000>;
1306
1307                         thermal-sensors = <&tsens 9>;
1308
1309                         trips {
1310                                 gpu_alert0: trip-point@0 {
1311                                         temperature = <95000>;
1312                                         hysteresis = <2000>;
1313                                         type = "hot";
1314                                 };
1315                         };
1316                 };
1317         };
1318 };