1 // SPDX-License-Identifier: BSD-3-Clause
3 * SC7180 SoC device tree source
5 * Copyright (c) 2019, The Linux Foundation. All rights reserved.
8 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
9 #include <dt-bindings/clock/qcom,gcc-sc7180.h>
10 #include <dt-bindings/clock/qcom,gpucc-sc7180.h>
11 #include <dt-bindings/clock/qcom,rpmh.h>
12 #include <dt-bindings/clock/qcom,videocc-sc7180.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/phy/phy-qcom-qusb2.h>
15 #include <dt-bindings/power/qcom-aoss-qmp.h>
16 #include <dt-bindings/power/qcom-rpmpd.h>
17 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
18 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
19 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
20 #include <dt-bindings/thermal/thermal.h>
23 interrupt-parent = <&intc>;
55 compatible = "fixed-clock";
56 clock-frequency = <38400000>;
60 sleep_clk: sleep-clk {
61 compatible = "fixed-clock";
62 clock-frequency = <32764>;
67 reserved_memory: reserved-memory {
72 aop_cmd_db_mem: memory@80820000 {
73 reg = <0x0 0x80820000 0x0 0x20000>;
74 compatible = "qcom,cmd-db";
77 smem_mem: memory@80900000 {
78 reg = <0x0 0x80900000 0x0 0x200000>;
82 venus_mem: memory@8f600000 {
83 reg = <0 0x8f600000 0 0x500000>;
94 compatible = "arm,armv8";
96 enable-method = "psci";
97 capacity-dmips-mhz = <1024>;
98 dynamic-power-coefficient = <100>;
99 next-level-cache = <&L2_0>;
100 #cooling-cells = <2>;
101 qcom,freq-domain = <&cpufreq_hw 0>;
103 compatible = "cache";
104 next-level-cache = <&L3_0>;
106 compatible = "cache";
113 compatible = "arm,armv8";
115 enable-method = "psci";
116 capacity-dmips-mhz = <1024>;
117 dynamic-power-coefficient = <100>;
118 next-level-cache = <&L2_100>;
119 #cooling-cells = <2>;
120 qcom,freq-domain = <&cpufreq_hw 0>;
122 compatible = "cache";
123 next-level-cache = <&L3_0>;
129 compatible = "arm,armv8";
131 enable-method = "psci";
132 capacity-dmips-mhz = <1024>;
133 dynamic-power-coefficient = <100>;
134 next-level-cache = <&L2_200>;
135 #cooling-cells = <2>;
136 qcom,freq-domain = <&cpufreq_hw 0>;
138 compatible = "cache";
139 next-level-cache = <&L3_0>;
145 compatible = "arm,armv8";
147 enable-method = "psci";
148 capacity-dmips-mhz = <1024>;
149 dynamic-power-coefficient = <100>;
150 next-level-cache = <&L2_300>;
151 #cooling-cells = <2>;
152 qcom,freq-domain = <&cpufreq_hw 0>;
154 compatible = "cache";
155 next-level-cache = <&L3_0>;
161 compatible = "arm,armv8";
163 enable-method = "psci";
164 capacity-dmips-mhz = <1024>;
165 dynamic-power-coefficient = <100>;
166 next-level-cache = <&L2_400>;
167 #cooling-cells = <2>;
168 qcom,freq-domain = <&cpufreq_hw 0>;
170 compatible = "cache";
171 next-level-cache = <&L3_0>;
177 compatible = "arm,armv8";
179 enable-method = "psci";
180 capacity-dmips-mhz = <1024>;
181 dynamic-power-coefficient = <100>;
182 next-level-cache = <&L2_500>;
183 #cooling-cells = <2>;
184 qcom,freq-domain = <&cpufreq_hw 0>;
186 compatible = "cache";
187 next-level-cache = <&L3_0>;
193 compatible = "arm,armv8";
195 enable-method = "psci";
196 capacity-dmips-mhz = <1740>;
197 dynamic-power-coefficient = <405>;
198 next-level-cache = <&L2_600>;
199 #cooling-cells = <2>;
200 qcom,freq-domain = <&cpufreq_hw 1>;
202 compatible = "cache";
203 next-level-cache = <&L3_0>;
209 compatible = "arm,armv8";
211 enable-method = "psci";
212 capacity-dmips-mhz = <1740>;
213 dynamic-power-coefficient = <405>;
214 next-level-cache = <&L2_700>;
215 #cooling-cells = <2>;
216 qcom,freq-domain = <&cpufreq_hw 1>;
218 compatible = "cache";
219 next-level-cache = <&L3_0>;
261 device_type = "memory";
262 /* We expect the bootloader to fill in the size */
263 reg = <0 0x80000000 0 0>;
267 compatible = "arm,armv8-pmuv3";
268 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
273 compatible = "qcom,scm-sc7180", "qcom,scm";
278 compatible = "qcom,tcsr-mutex";
279 syscon = <&tcsr_mutex_regs 0 0x1000>;
284 compatible = "qcom,smem";
285 memory-region = <&smem_mem>;
286 hwlocks = <&tcsr_mutex 3>;
290 compatible = "qcom,smp2p";
291 qcom,smem = <94>, <432>;
293 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
295 mboxes = <&apss_shared 6>;
297 qcom,local-pid = <0>;
298 qcom,remote-pid = <5>;
300 cdsp_smp2p_out: master-kernel {
301 qcom,entry-name = "master-kernel";
302 #qcom,smem-state-cells = <1>;
305 cdsp_smp2p_in: slave-kernel {
306 qcom,entry-name = "slave-kernel";
308 interrupt-controller;
309 #interrupt-cells = <2>;
314 compatible = "qcom,smp2p";
315 qcom,smem = <443>, <429>;
317 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
319 mboxes = <&apss_shared 10>;
321 qcom,local-pid = <0>;
322 qcom,remote-pid = <2>;
324 adsp_smp2p_out: master-kernel {
325 qcom,entry-name = "master-kernel";
326 #qcom,smem-state-cells = <1>;
329 adsp_smp2p_in: slave-kernel {
330 qcom,entry-name = "slave-kernel";
332 interrupt-controller;
333 #interrupt-cells = <2>;
338 compatible = "qcom,smp2p";
339 qcom,smem = <435>, <428>;
340 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
341 mboxes = <&apss_shared 14>;
342 qcom,local-pid = <0>;
343 qcom,remote-pid = <1>;
345 modem_smp2p_out: master-kernel {
346 qcom,entry-name = "master-kernel";
347 #qcom,smem-state-cells = <1>;
350 modem_smp2p_in: slave-kernel {
351 qcom,entry-name = "slave-kernel";
352 interrupt-controller;
353 #interrupt-cells = <2>;
358 compatible = "arm,psci-1.0";
363 #address-cells = <2>;
365 ranges = <0 0 0 0 0x10 0>;
366 dma-ranges = <0 0 0 0 0x10 0>;
367 compatible = "simple-bus";
369 gcc: clock-controller@100000 {
370 compatible = "qcom,gcc-sc7180";
371 reg = <0 0x00100000 0 0x1f0000>;
372 clocks = <&rpmhcc RPMH_CXO_CLK>,
373 <&rpmhcc RPMH_CXO_CLK_A>,
375 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
378 #power-domain-cells = <1>;
382 compatible = "qcom,qfprom";
383 reg = <0 0x00784000 0 0x8ff>;
384 #address-cells = <1>;
387 qusb2p_hstx_trim: hstx-trim-primary@25b {
393 sdhc_1: sdhci@7c4000 {
394 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
395 reg = <0 0x7c4000 0 0x1000>,
396 <0 0x07c5000 0 0x1000>;
397 reg-names = "hc", "cqhci";
399 iommus = <&apps_smmu 0x60 0x0>;
400 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
401 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
402 interrupt-names = "hc_irq", "pwr_irq";
404 clocks = <&gcc GCC_SDCC1_APPS_CLK>,
405 <&gcc GCC_SDCC1_AHB_CLK>;
406 clock-names = "core", "iface";
415 mmc-hs400-enhanced-strobe;
420 qupv3_id_0: geniqup@8c0000 {
421 compatible = "qcom,geni-se-qup";
422 reg = <0 0x008c0000 0 0x6000>;
423 clock-names = "m-ahb", "s-ahb";
424 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
425 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
426 #address-cells = <2>;
429 iommus = <&apps_smmu 0x43 0x0>;
433 compatible = "qcom,geni-i2c";
434 reg = <0 0x00880000 0 0x4000>;
436 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
437 pinctrl-names = "default";
438 pinctrl-0 = <&qup_i2c0_default>;
439 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
440 #address-cells = <1>;
446 compatible = "qcom,geni-spi";
447 reg = <0 0x00880000 0 0x4000>;
449 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
450 pinctrl-names = "default";
451 pinctrl-0 = <&qup_spi0_default>;
452 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
453 #address-cells = <1>;
458 uart0: serial@880000 {
459 compatible = "qcom,geni-uart";
460 reg = <0 0x00880000 0 0x4000>;
462 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
463 pinctrl-names = "default";
464 pinctrl-0 = <&qup_uart0_default>;
465 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
470 compatible = "qcom,geni-i2c";
471 reg = <0 0x00884000 0 0x4000>;
473 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
474 pinctrl-names = "default";
475 pinctrl-0 = <&qup_i2c1_default>;
476 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
477 #address-cells = <1>;
483 compatible = "qcom,geni-spi";
484 reg = <0 0x00884000 0 0x4000>;
486 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
487 pinctrl-names = "default";
488 pinctrl-0 = <&qup_spi1_default>;
489 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
490 #address-cells = <1>;
495 uart1: serial@884000 {
496 compatible = "qcom,geni-uart";
497 reg = <0 0x00884000 0 0x4000>;
499 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
500 pinctrl-names = "default";
501 pinctrl-0 = <&qup_uart1_default>;
502 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
507 compatible = "qcom,geni-i2c";
508 reg = <0 0x00888000 0 0x4000>;
510 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
511 pinctrl-names = "default";
512 pinctrl-0 = <&qup_i2c2_default>;
513 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
514 #address-cells = <1>;
519 uart2: serial@888000 {
520 compatible = "qcom,geni-uart";
521 reg = <0 0x00888000 0 0x4000>;
523 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
524 pinctrl-names = "default";
525 pinctrl-0 = <&qup_uart2_default>;
526 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
531 compatible = "qcom,geni-i2c";
532 reg = <0 0x0088c000 0 0x4000>;
534 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
535 pinctrl-names = "default";
536 pinctrl-0 = <&qup_i2c3_default>;
537 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
538 #address-cells = <1>;
544 compatible = "qcom,geni-spi";
545 reg = <0 0x0088c000 0 0x4000>;
547 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
548 pinctrl-names = "default";
549 pinctrl-0 = <&qup_spi3_default>;
550 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
551 #address-cells = <1>;
556 uart3: serial@88c000 {
557 compatible = "qcom,geni-uart";
558 reg = <0 0x0088c000 0 0x4000>;
560 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
561 pinctrl-names = "default";
562 pinctrl-0 = <&qup_uart3_default>;
563 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
568 compatible = "qcom,geni-i2c";
569 reg = <0 0x00890000 0 0x4000>;
571 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
572 pinctrl-names = "default";
573 pinctrl-0 = <&qup_i2c4_default>;
574 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
575 #address-cells = <1>;
580 uart4: serial@890000 {
581 compatible = "qcom,geni-uart";
582 reg = <0 0x00890000 0 0x4000>;
584 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
585 pinctrl-names = "default";
586 pinctrl-0 = <&qup_uart4_default>;
587 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
592 compatible = "qcom,geni-i2c";
593 reg = <0 0x00894000 0 0x4000>;
595 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
596 pinctrl-names = "default";
597 pinctrl-0 = <&qup_i2c5_default>;
598 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
599 #address-cells = <1>;
605 compatible = "qcom,geni-spi";
606 reg = <0 0x00894000 0 0x4000>;
608 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
609 pinctrl-names = "default";
610 pinctrl-0 = <&qup_spi5_default>;
611 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
612 #address-cells = <1>;
617 uart5: serial@894000 {
618 compatible = "qcom,geni-uart";
619 reg = <0 0x00894000 0 0x4000>;
621 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
622 pinctrl-names = "default";
623 pinctrl-0 = <&qup_uart5_default>;
624 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
629 qupv3_id_1: geniqup@ac0000 {
630 compatible = "qcom,geni-se-qup";
631 reg = <0 0x00ac0000 0 0x6000>;
632 clock-names = "m-ahb", "s-ahb";
633 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
634 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
635 #address-cells = <2>;
638 iommus = <&apps_smmu 0x4c3 0x0>;
642 compatible = "qcom,geni-i2c";
643 reg = <0 0x00a80000 0 0x4000>;
645 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
646 pinctrl-names = "default";
647 pinctrl-0 = <&qup_i2c6_default>;
648 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
649 #address-cells = <1>;
655 compatible = "qcom,geni-spi";
656 reg = <0 0x00a80000 0 0x4000>;
658 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
659 pinctrl-names = "default";
660 pinctrl-0 = <&qup_spi6_default>;
661 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
662 #address-cells = <1>;
667 uart6: serial@a80000 {
668 compatible = "qcom,geni-uart";
669 reg = <0 0x00a80000 0 0x4000>;
671 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
672 pinctrl-names = "default";
673 pinctrl-0 = <&qup_uart6_default>;
674 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
679 compatible = "qcom,geni-i2c";
680 reg = <0 0x00a84000 0 0x4000>;
682 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
683 pinctrl-names = "default";
684 pinctrl-0 = <&qup_i2c7_default>;
685 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
686 #address-cells = <1>;
691 uart7: serial@a84000 {
692 compatible = "qcom,geni-uart";
693 reg = <0 0x00a84000 0 0x4000>;
695 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
696 pinctrl-names = "default";
697 pinctrl-0 = <&qup_uart7_default>;
698 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
703 compatible = "qcom,geni-i2c";
704 reg = <0 0x00a88000 0 0x4000>;
706 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
707 pinctrl-names = "default";
708 pinctrl-0 = <&qup_i2c8_default>;
709 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
710 #address-cells = <1>;
716 compatible = "qcom,geni-spi";
717 reg = <0 0x00a88000 0 0x4000>;
719 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
720 pinctrl-names = "default";
721 pinctrl-0 = <&qup_spi8_default>;
722 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
723 #address-cells = <1>;
728 uart8: serial@a88000 {
729 compatible = "qcom,geni-debug-uart";
730 reg = <0 0x00a88000 0 0x4000>;
732 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
733 pinctrl-names = "default";
734 pinctrl-0 = <&qup_uart8_default>;
735 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
740 compatible = "qcom,geni-i2c";
741 reg = <0 0x00a8c000 0 0x4000>;
743 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
744 pinctrl-names = "default";
745 pinctrl-0 = <&qup_i2c9_default>;
746 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
747 #address-cells = <1>;
752 uart9: serial@a8c000 {
753 compatible = "qcom,geni-uart";
754 reg = <0 0x00a8c000 0 0x4000>;
756 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
757 pinctrl-names = "default";
758 pinctrl-0 = <&qup_uart9_default>;
759 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
764 compatible = "qcom,geni-i2c";
765 reg = <0 0x00a90000 0 0x4000>;
767 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
768 pinctrl-names = "default";
769 pinctrl-0 = <&qup_i2c10_default>;
770 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
771 #address-cells = <1>;
777 compatible = "qcom,geni-spi";
778 reg = <0 0x00a90000 0 0x4000>;
780 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
781 pinctrl-names = "default";
782 pinctrl-0 = <&qup_spi10_default>;
783 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
784 #address-cells = <1>;
789 uart10: serial@a90000 {
790 compatible = "qcom,geni-uart";
791 reg = <0 0x00a90000 0 0x4000>;
793 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
794 pinctrl-names = "default";
795 pinctrl-0 = <&qup_uart10_default>;
796 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
801 compatible = "qcom,geni-i2c";
802 reg = <0 0x00a94000 0 0x4000>;
804 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
805 pinctrl-names = "default";
806 pinctrl-0 = <&qup_i2c11_default>;
807 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
808 #address-cells = <1>;
814 compatible = "qcom,geni-spi";
815 reg = <0 0x00a94000 0 0x4000>;
817 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
818 pinctrl-names = "default";
819 pinctrl-0 = <&qup_spi11_default>;
820 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
821 #address-cells = <1>;
826 uart11: serial@a94000 {
827 compatible = "qcom,geni-uart";
828 reg = <0 0x00a94000 0 0x4000>;
830 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
831 pinctrl-names = "default";
832 pinctrl-0 = <&qup_uart11_default>;
833 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
838 config_noc: interconnect@1500000 {
839 compatible = "qcom,sc7180-config-noc";
840 reg = <0 0x01500000 0 0x28000>;
841 #interconnect-cells = <1>;
842 qcom,bcm-voters = <&apps_bcm_voter>;
845 system_noc: interconnect@1620000 {
846 compatible = "qcom,sc7180-system-noc";
847 reg = <0 0x01620000 0 0x17080>;
848 #interconnect-cells = <1>;
849 qcom,bcm-voters = <&apps_bcm_voter>;
852 mc_virt: interconnect@1638000 {
853 compatible = "qcom,sc7180-mc-virt";
854 reg = <0 0x01638000 0 0x1000>;
855 #interconnect-cells = <1>;
856 qcom,bcm-voters = <&apps_bcm_voter>;
859 qup_virt: interconnect@1650000 {
860 compatible = "qcom,sc7180-qup-virt";
861 reg = <0 0x01650000 0 0x1000>;
862 #interconnect-cells = <1>;
863 qcom,bcm-voters = <&apps_bcm_voter>;
866 aggre1_noc: interconnect@16e0000 {
867 compatible = "qcom,sc7180-aggre1-noc";
868 reg = <0 0x016e0000 0 0x15080>;
869 #interconnect-cells = <1>;
870 qcom,bcm-voters = <&apps_bcm_voter>;
873 aggre2_noc: interconnect@1705000 {
874 compatible = "qcom,sc7180-aggre2-noc";
875 reg = <0 0x01705000 0 0x9000>;
876 #interconnect-cells = <1>;
877 qcom,bcm-voters = <&apps_bcm_voter>;
880 compute_noc: interconnect@170e000 {
881 compatible = "qcom,sc7180-compute-noc";
882 reg = <0 0x0170e000 0 0x6000>;
883 #interconnect-cells = <1>;
884 qcom,bcm-voters = <&apps_bcm_voter>;
887 mmss_noc: interconnect@1740000 {
888 compatible = "qcom,sc7180-mmss-noc";
889 reg = <0 0x01740000 0 0x1c100>;
890 #interconnect-cells = <1>;
891 qcom,bcm-voters = <&apps_bcm_voter>;
894 ipa_virt: interconnect@1e00000 {
895 compatible = "qcom,sc7180-ipa-virt";
896 reg = <0 0x01e00000 0 0x1000>;
897 #interconnect-cells = <1>;
898 qcom,bcm-voters = <&apps_bcm_voter>;
901 tcsr_mutex_regs: syscon@1f40000 {
902 compatible = "syscon";
903 reg = <0 0x01f40000 0 0x40000>;
906 tlmm: pinctrl@3500000 {
907 compatible = "qcom,sc7180-pinctrl";
908 reg = <0 0x03500000 0 0x300000>,
909 <0 0x03900000 0 0x300000>,
910 <0 0x03d00000 0 0x300000>;
911 reg-names = "west", "north", "south";
912 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
915 interrupt-controller;
916 #interrupt-cells = <2>;
917 gpio-ranges = <&tlmm 0 0 120>;
918 wakeup-parent = <&pdc>;
923 function = "qspi_clk";
930 function = "qspi_cs";
937 function = "qspi_cs";
941 qspi_data01: qspi-data01 {
943 pins = "gpio64", "gpio65";
944 function = "qspi_data";
948 qspi_data12: qspi-data12 {
950 pins = "gpio66", "gpio67";
951 function = "qspi_data";
955 qup_i2c0_default: qup-i2c0-default {
957 pins = "gpio34", "gpio35";
962 qup_i2c1_default: qup-i2c1-default {
964 pins = "gpio0", "gpio1";
969 qup_i2c2_default: qup-i2c2-default {
971 pins = "gpio15", "gpio16";
972 function = "qup02_i2c";
976 qup_i2c3_default: qup-i2c3-default {
978 pins = "gpio38", "gpio39";
983 qup_i2c4_default: qup-i2c4-default {
985 pins = "gpio115", "gpio116";
986 function = "qup04_i2c";
990 qup_i2c5_default: qup-i2c5-default {
992 pins = "gpio25", "gpio26";
997 qup_i2c6_default: qup-i2c6-default {
999 pins = "gpio59", "gpio60";
1004 qup_i2c7_default: qup-i2c7-default {
1006 pins = "gpio6", "gpio7";
1007 function = "qup11_i2c";
1011 qup_i2c8_default: qup-i2c8-default {
1013 pins = "gpio42", "gpio43";
1018 qup_i2c9_default: qup-i2c9-default {
1020 pins = "gpio46", "gpio47";
1021 function = "qup13_i2c";
1025 qup_i2c10_default: qup-i2c10-default {
1027 pins = "gpio86", "gpio87";
1032 qup_i2c11_default: qup-i2c11-default {
1034 pins = "gpio53", "gpio54";
1039 qup_spi0_default: qup-spi0-default {
1041 pins = "gpio34", "gpio35",
1047 qup_spi1_default: qup-spi1-default {
1049 pins = "gpio0", "gpio1",
1055 qup_spi3_default: qup-spi3-default {
1057 pins = "gpio38", "gpio39",
1063 qup_spi5_default: qup-spi5-default {
1065 pins = "gpio25", "gpio26",
1071 qup_spi6_default: qup-spi6-default {
1073 pins = "gpio59", "gpio60",
1079 qup_spi8_default: qup-spi8-default {
1081 pins = "gpio42", "gpio43",
1087 qup_spi10_default: qup-spi10-default {
1089 pins = "gpio86", "gpio87",
1095 qup_spi11_default: qup-spi11-default {
1097 pins = "gpio53", "gpio54",
1103 qup_uart0_default: qup-uart0-default {
1105 pins = "gpio34", "gpio35",
1111 qup_uart1_default: qup-uart1-default {
1113 pins = "gpio0", "gpio1",
1119 qup_uart2_default: qup-uart2-default {
1121 pins = "gpio15", "gpio16";
1122 function = "qup02_uart";
1126 qup_uart3_default: qup-uart3-default {
1128 pins = "gpio38", "gpio39",
1134 qup_uart4_default: qup-uart4-default {
1136 pins = "gpio115", "gpio116";
1137 function = "qup04_uart";
1141 qup_uart5_default: qup-uart5-default {
1143 pins = "gpio25", "gpio26",
1149 qup_uart6_default: qup-uart6-default {
1151 pins = "gpio59", "gpio60",
1157 qup_uart7_default: qup-uart7-default {
1159 pins = "gpio6", "gpio7";
1160 function = "qup11_uart";
1164 qup_uart8_default: qup-uart8-default {
1166 pins = "gpio44", "gpio45";
1171 qup_uart9_default: qup-uart9-default {
1173 pins = "gpio46", "gpio47";
1174 function = "qup13_uart";
1178 qup_uart10_default: qup-uart10-default {
1180 pins = "gpio86", "gpio87",
1186 qup_uart11_default: qup-uart11-default {
1188 pins = "gpio53", "gpio54",
1198 drive-strength = <16>;
1204 drive-strength = <10>;
1210 drive-strength = <10>;
1219 sdc1_off: sdc1-off {
1223 drive-strength = <2>;
1229 drive-strength = <2>;
1235 drive-strength = <2>;
1248 drive-strength = <16>;
1254 drive-strength = <10>;
1260 drive-strength = <10>;
1266 drive-strength = <2>;
1270 sdc2_off: sdc2-off {
1274 drive-strength = <2>;
1280 drive-strength = <2>;
1286 drive-strength = <2>;
1292 drive-strength = <2>;
1297 sdhc_2: sdhci@8804000 {
1298 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
1299 reg = <0 0x08804000 0 0x1000>;
1301 iommus = <&apps_smmu 0x80 0>;
1302 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
1303 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
1304 interrupt-names = "hc_irq", "pwr_irq";
1306 clocks = <&gcc GCC_SDCC2_APPS_CLK>,
1307 <&gcc GCC_SDCC2_AHB_CLK>;
1308 clock-names = "core", "iface";
1312 status = "disabled";
1315 gpucc: clock-controller@5090000 {
1316 compatible = "qcom,sc7180-gpucc";
1317 reg = <0 0x05090000 0 0x9000>;
1318 clocks = <&rpmhcc RPMH_CXO_CLK>,
1319 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
1320 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
1321 clock-names = "bi_tcxo",
1322 "gcc_gpu_gpll0_clk_src",
1323 "gcc_gpu_gpll0_div_clk_src";
1326 #power-domain-cells = <1>;
1330 compatible = "qcom,qspi-v1";
1331 reg = <0 0x088dc000 0 0x600>;
1332 #address-cells = <1>;
1334 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
1335 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
1336 <&gcc GCC_QSPI_CORE_CLK>;
1337 clock-names = "iface", "core";
1338 status = "disabled";
1341 usb_1_hsphy: phy@88e3000 {
1342 compatible = "qcom,sc7180-qusb2-phy";
1343 reg = <0 0x088e3000 0 0x400>;
1344 status = "disabled";
1346 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1347 <&rpmhcc RPMH_CXO_CLK>;
1348 clock-names = "cfg_ahb", "ref";
1349 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
1351 nvmem-cells = <&qusb2p_hstx_trim>;
1354 usb_1_qmpphy: phy-wrapper@88e9000 {
1355 compatible = "qcom,sc7180-qmp-usb3-phy";
1356 reg = <0 0x088e9000 0 0x18c>,
1357 <0 0x088e8000 0 0x38>;
1358 reg-names = "reg-base", "dp_com";
1359 status = "disabled";
1361 #address-cells = <2>;
1365 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
1366 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1367 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
1368 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
1369 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
1371 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
1372 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
1373 reset-names = "phy", "common";
1375 usb_1_ssphy: phy@88e9200 {
1376 reg = <0 0x088e9200 0 0x128>,
1377 <0 0x088e9400 0 0x200>,
1378 <0 0x088e9c00 0 0x218>,
1379 <0 0x088e9600 0 0x128>,
1380 <0 0x088e9800 0 0x200>,
1381 <0 0x088e9a00 0 0x18>;
1384 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
1385 clock-names = "pipe0";
1386 clock-output-names = "usb3_phy_pipe_clk_src";
1390 dc_noc: interconnect@9160000 {
1391 compatible = "qcom,sc7180-dc-noc";
1392 reg = <0 0x09160000 0 0x03200>;
1393 #interconnect-cells = <1>;
1394 qcom,bcm-voters = <&apps_bcm_voter>;
1397 system-cache-controller@9200000 {
1398 compatible = "qcom,sc7180-llcc";
1399 reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>;
1400 reg-names = "llcc_base", "llcc_broadcast_base";
1401 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
1404 gem_noc: interconnect@9680000 {
1405 compatible = "qcom,sc7180-gem-noc";
1406 reg = <0 0x09680000 0 0x3e200>;
1407 #interconnect-cells = <1>;
1408 qcom,bcm-voters = <&apps_bcm_voter>;
1411 npu_noc: interconnect@9990000 {
1412 compatible = "qcom,sc7180-npu-noc";
1413 reg = <0 0x09990000 0 0x1600>;
1414 #interconnect-cells = <1>;
1415 qcom,bcm-voters = <&apps_bcm_voter>;
1418 usb_1: usb@a6f8800 {
1419 compatible = "qcom,sc7180-dwc3", "qcom,dwc3";
1420 reg = <0 0x0a6f8800 0 0x400>;
1421 status = "disabled";
1422 #address-cells = <2>;
1427 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
1428 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
1429 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
1430 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1431 <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
1432 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
1435 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1436 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
1437 assigned-clock-rates = <19200000>, <150000000>;
1439 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
1440 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
1441 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
1442 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
1443 interrupt-names = "hs_phy_irq", "ss_phy_irq",
1444 "dm_hs_phy_irq", "dp_hs_phy_irq";
1446 power-domains = <&gcc USB30_PRIM_GDSC>;
1448 resets = <&gcc GCC_USB30_PRIM_BCR>;
1450 usb_1_dwc3: dwc3@a600000 {
1451 compatible = "snps,dwc3";
1452 reg = <0 0x0a600000 0 0xe000>;
1453 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
1454 iommus = <&apps_smmu 0x540 0>;
1455 snps,dis_u2_susphy_quirk;
1456 snps,dis_enblslpm_quirk;
1457 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
1458 phy-names = "usb2-phy", "usb3-phy";
1462 venus: video-codec@aa00000 {
1463 compatible = "qcom,sc7180-venus";
1464 reg = <0 0x0aa00000 0 0xff000>;
1465 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
1466 power-domains = <&videocc VENUS_GDSC>,
1467 <&videocc VCODEC0_GDSC>;
1468 power-domain-names = "venus", "vcodec0";
1469 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
1470 <&videocc VIDEO_CC_VENUS_AHB_CLK>,
1471 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>,
1472 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
1473 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>;
1474 clock-names = "core", "iface", "bus",
1475 "vcodec0_core", "vcodec0_bus";
1476 iommus = <&apps_smmu 0x0c00 0x60>;
1477 memory-region = <&venus_mem>;
1480 compatible = "venus-decoder";
1484 compatible = "venus-encoder";
1488 videocc: clock-controller@ab00000 {
1489 compatible = "qcom,sc7180-videocc";
1490 reg = <0 0x0ab00000 0 0x10000>;
1491 clocks = <&rpmhcc RPMH_CXO_CLK>;
1492 clock-names = "bi_tcxo";
1495 #power-domain-cells = <1>;
1498 camnoc_virt: interconnect@ac00000 {
1499 compatible = "qcom,sc7180-camnoc-virt";
1500 reg = <0 0x0ac00000 0 0x1000>;
1501 #interconnect-cells = <1>;
1502 qcom,bcm-voters = <&apps_bcm_voter>;
1505 mdss: mdss@ae00000 {
1506 compatible = "qcom,sc7180-mdss";
1507 reg = <0 0x0ae00000 0 0x1000>;
1510 power-domains = <&dispcc MDSS_GDSC>;
1512 clocks = <&gcc GCC_DISP_AHB_CLK>,
1513 <&gcc GCC_DISP_HF_AXI_CLK>,
1514 <&dispcc DISP_CC_MDSS_AHB_CLK>,
1515 <&dispcc DISP_CC_MDSS_MDP_CLK>;
1516 clock-names = "iface", "bus", "ahb", "core";
1518 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
1519 assigned-clock-rates = <300000000>;
1521 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1522 interrupt-controller;
1523 #interrupt-cells = <1>;
1525 iommus = <&apps_smmu 0x800 0x2>;
1527 #address-cells = <2>;
1531 status = "disabled";
1534 compatible = "qcom,sc7180-dpu";
1535 reg = <0 0x0ae01000 0 0x8f000>,
1536 <0 0x0aeb0000 0 0x2008>;
1537 reg-names = "mdp", "vbif";
1539 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
1540 <&dispcc DISP_CC_MDSS_ROT_CLK>,
1541 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
1542 <&dispcc DISP_CC_MDSS_MDP_CLK>,
1543 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
1544 clock-names = "iface", "rot", "lut", "core",
1546 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
1547 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
1548 assigned-clock-rates = <300000000>,
1551 interrupt-parent = <&mdss>;
1552 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
1554 status = "disabled";
1557 #address-cells = <1>;
1562 dpu_intf1_out: endpoint {
1563 remote-endpoint = <&dsi0_in>;
1570 compatible = "qcom,mdss-dsi-ctrl";
1571 reg = <0 0x0ae94000 0 0x400>;
1572 reg-names = "dsi_ctrl";
1574 interrupt-parent = <&mdss>;
1575 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
1577 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
1578 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
1579 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
1580 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
1581 <&dispcc DISP_CC_MDSS_AHB_CLK>,
1582 <&gcc GCC_DISP_HF_AXI_CLK>;
1583 clock-names = "byte",
1593 #address-cells = <1>;
1596 status = "disabled";
1599 #address-cells = <1>;
1605 remote-endpoint = <&dpu_intf1_out>;
1611 dsi0_out: endpoint {
1617 dsi_phy: dsi-phy@ae94400 {
1618 compatible = "qcom,dsi-phy-10nm";
1619 reg = <0 0x0ae94400 0 0x200>,
1620 <0 0x0ae94600 0 0x280>,
1621 <0 0x0ae94a00 0 0x1e0>;
1622 reg-names = "dsi_phy",
1629 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
1630 <&rpmhcc RPMH_CXO_CLK>;
1631 clock-names = "iface", "ref";
1633 status = "disabled";
1637 dispcc: clock-controller@af00000 {
1638 compatible = "qcom,sc7180-dispcc";
1639 reg = <0 0x0af00000 0 0x200000>;
1640 clocks = <&rpmhcc RPMH_CXO_CLK>,
1641 <&gcc GCC_DISP_GPLL0_CLK_SRC>,
1646 clock-names = "bi_tcxo",
1647 "gcc_disp_gpll0_clk_src",
1648 "dsi0_phy_pll_out_byteclk",
1649 "dsi0_phy_pll_out_dsiclk",
1650 "dp_phy_pll_link_clk",
1651 "dp_phy_pll_vco_div_clk";
1654 #power-domain-cells = <1>;
1657 pdc: interrupt-controller@b220000 {
1658 compatible = "qcom,sc7180-pdc", "qcom,pdc";
1659 reg = <0 0x0b220000 0 0x30000>;
1660 qcom,pdc-ranges = <0 480 15>, <17 497 98>,
1661 <119 634 4>, <124 639 1>;
1662 #interrupt-cells = <2>;
1663 interrupt-parent = <&intc>;
1664 interrupt-controller;
1667 pdc_reset: reset-controller@b2e0000 {
1668 compatible = "qcom,sc7180-pdc-global", "qcom,sdm845-pdc-global";
1669 reg = <0 0x0b2e0000 0 0x20000>;
1673 tsens0: thermal-sensor@c263000 {
1674 compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
1675 reg = <0 0x0c263000 0 0x1ff>, /* TM */
1676 <0 0x0c222000 0 0x1ff>; /* SROT */
1677 #qcom,sensors = <15>;
1678 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
1679 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
1680 interrupt-names = "uplow","critical";
1681 #thermal-sensor-cells = <1>;
1684 tsens1: thermal-sensor@c265000 {
1685 compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
1686 reg = <0 0x0c265000 0 0x1ff>, /* TM */
1687 <0 0x0c223000 0 0x1ff>; /* SROT */
1688 #qcom,sensors = <10>;
1689 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
1690 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
1691 interrupt-names = "uplow","critical";
1692 #thermal-sensor-cells = <1>;
1695 aoss_reset: reset-controller@c2a0000 {
1696 compatible = "qcom,sc7180-aoss-cc", "qcom,sdm845-aoss-cc";
1697 reg = <0 0x0c2a0000 0 0x31000>;
1701 aoss_qmp: qmp@c300000 {
1702 compatible = "qcom,sc7180-aoss-qmp";
1703 reg = <0 0x0c300000 0 0x100000>;
1704 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
1705 mboxes = <&apss_shared 0>;
1708 #power-domain-cells = <1>;
1711 spmi_bus: spmi@c440000 {
1712 compatible = "qcom,spmi-pmic-arb";
1713 reg = <0 0x0c440000 0 0x1100>,
1714 <0 0x0c600000 0 0x2000000>,
1715 <0 0x0e600000 0 0x100000>,
1716 <0 0x0e700000 0 0xa0000>,
1717 <0 0x0c40a000 0 0x26000>;
1718 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1719 interrupt-names = "periph_irq";
1720 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
1723 #address-cells = <1>;
1725 interrupt-controller;
1726 #interrupt-cells = <4>;
1730 apps_smmu: iommu@15000000 {
1731 compatible = "qcom,sc7180-smmu-500", "arm,mmu-500";
1732 reg = <0 0x15000000 0 0x100000>;
1734 #global-interrupts = <1>;
1735 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
1736 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
1737 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
1738 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
1739 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
1740 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
1741 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
1742 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1743 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1744 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1745 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1746 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1747 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
1748 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1749 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
1750 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1751 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1752 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
1753 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
1754 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
1755 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
1756 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
1757 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
1758 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1759 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1760 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1761 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
1762 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
1763 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
1764 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
1765 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
1766 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
1767 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
1768 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
1769 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
1770 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
1771 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
1772 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
1773 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
1774 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
1775 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
1776 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
1777 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
1778 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
1779 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
1780 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
1781 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
1782 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
1783 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
1784 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
1785 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
1786 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
1787 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1788 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
1789 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
1790 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
1791 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
1792 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1793 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1794 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1795 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
1796 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
1797 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
1798 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
1799 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
1800 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
1801 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
1802 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
1803 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
1804 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
1805 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
1806 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
1807 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
1808 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
1809 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
1810 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
1811 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
1812 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
1813 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
1814 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
1815 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
1818 intc: interrupt-controller@17a00000 {
1819 compatible = "arm,gic-v3";
1820 #address-cells = <2>;
1823 #interrupt-cells = <3>;
1824 interrupt-controller;
1825 reg = <0 0x17a00000 0 0x10000>, /* GICD */
1826 <0 0x17a60000 0 0x100000>; /* GICR * 8 */
1827 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1829 msi-controller@17a40000 {
1830 compatible = "arm,gic-v3-its";
1833 reg = <0 0x17a40000 0 0x20000>;
1834 status = "disabled";
1838 apss_shared: mailbox@17c00000 {
1839 compatible = "qcom,sc7180-apss-shared";
1840 reg = <0 0x17c00000 0 0x10000>;
1845 compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt";
1846 reg = <0 0x17c10000 0 0x1000>;
1847 clocks = <&sleep_clk>;
1851 #address-cells = <2>;
1854 compatible = "arm,armv7-timer-mem";
1855 reg = <0 0x17c20000 0 0x1000>;
1859 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
1860 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1861 reg = <0 0x17c21000 0 0x1000>,
1862 <0 0x17c22000 0 0x1000>;
1867 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1868 reg = <0 0x17c23000 0 0x1000>;
1869 status = "disabled";
1874 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1875 reg = <0 0x17c25000 0 0x1000>;
1876 status = "disabled";
1881 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1882 reg = <0 0x17c27000 0 0x1000>;
1883 status = "disabled";
1888 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1889 reg = <0 0x17c29000 0 0x1000>;
1890 status = "disabled";
1895 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1896 reg = <0 0x17c2b000 0 0x1000>;
1897 status = "disabled";
1902 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1903 reg = <0 0x17c2d000 0 0x1000>;
1904 status = "disabled";
1908 apps_rsc: rsc@18200000 {
1909 compatible = "qcom,rpmh-rsc";
1910 reg = <0 0x18200000 0 0x10000>,
1911 <0 0x18210000 0 0x10000>,
1912 <0 0x18220000 0 0x10000>;
1913 reg-names = "drv-0", "drv-1", "drv-2";
1914 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
1915 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
1916 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1917 qcom,tcs-offset = <0xd00>;
1919 qcom,tcs-config = <ACTIVE_TCS 2>,
1924 rpmhcc: clock-controller {
1925 compatible = "qcom,sc7180-rpmh-clk";
1926 clocks = <&xo_board>;
1931 rpmhpd: power-controller {
1932 compatible = "qcom,sc7180-rpmhpd";
1933 #power-domain-cells = <1>;
1934 operating-points-v2 = <&rpmhpd_opp_table>;
1936 rpmhpd_opp_table: opp-table {
1937 compatible = "operating-points-v2";
1939 rpmhpd_opp_ret: opp1 {
1940 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
1943 rpmhpd_opp_min_svs: opp2 {
1944 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1947 rpmhpd_opp_low_svs: opp3 {
1948 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1951 rpmhpd_opp_svs: opp4 {
1952 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1955 rpmhpd_opp_svs_l1: opp5 {
1956 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1959 rpmhpd_opp_svs_l2: opp6 {
1963 rpmhpd_opp_nom: opp7 {
1964 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1967 rpmhpd_opp_nom_l1: opp8 {
1968 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1971 rpmhpd_opp_nom_l2: opp9 {
1972 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
1975 rpmhpd_opp_turbo: opp10 {
1976 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1979 rpmhpd_opp_turbo_l1: opp11 {
1980 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1985 apps_bcm_voter: bcm_voter {
1986 compatible = "qcom,bcm-voter";
1990 osm_l3: interconnect@18321000 {
1991 compatible = "qcom,sc7180-osm-l3";
1992 reg = <0 0x18321000 0 0x1400>;
1994 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
1995 clock-names = "xo", "alternate";
1997 #interconnect-cells = <1>;
2000 cpufreq_hw: cpufreq@18323000 {
2001 compatible = "qcom,cpufreq-hw";
2002 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>;
2003 reg-names = "freq-domain0", "freq-domain1";
2005 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
2006 clock-names = "xo", "alternate";
2008 #freq-domain-cells = <1>;
2014 polling-delay-passive = <250>;
2015 polling-delay = <1000>;
2017 thermal-sensors = <&tsens0 1>;
2020 cpu0_alert0: trip-point0 {
2021 temperature = <90000>;
2022 hysteresis = <2000>;
2026 cpu0_alert1: trip-point1 {
2027 temperature = <95000>;
2028 hysteresis = <2000>;
2032 cpu0_crit: cpu_crit {
2033 temperature = <110000>;
2034 hysteresis = <1000>;
2041 trip = <&cpu0_alert0>;
2042 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2043 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2044 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2045 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2046 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2047 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2050 trip = <&cpu0_alert1>;
2051 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2052 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2053 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2054 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2055 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2056 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2062 polling-delay-passive = <250>;
2063 polling-delay = <1000>;
2065 thermal-sensors = <&tsens0 2>;
2068 cpu1_alert0: trip-point0 {
2069 temperature = <90000>;
2070 hysteresis = <2000>;
2074 cpu1_alert1: trip-point1 {
2075 temperature = <95000>;
2076 hysteresis = <2000>;
2080 cpu1_crit: cpu_crit {
2081 temperature = <110000>;
2082 hysteresis = <1000>;
2089 trip = <&cpu1_alert0>;
2090 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2091 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2092 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2093 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2094 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2095 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2098 trip = <&cpu1_alert1>;
2099 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2100 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2101 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2102 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2103 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2104 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2110 polling-delay-passive = <250>;
2111 polling-delay = <1000>;
2113 thermal-sensors = <&tsens0 3>;
2116 cpu2_alert0: trip-point0 {
2117 temperature = <90000>;
2118 hysteresis = <2000>;
2122 cpu2_alert1: trip-point1 {
2123 temperature = <95000>;
2124 hysteresis = <2000>;
2128 cpu2_crit: cpu_crit {
2129 temperature = <110000>;
2130 hysteresis = <1000>;
2137 trip = <&cpu2_alert0>;
2138 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2139 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2140 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2141 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2142 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2143 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2146 trip = <&cpu2_alert1>;
2147 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2148 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2149 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2150 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2151 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2152 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2158 polling-delay-passive = <250>;
2159 polling-delay = <1000>;
2161 thermal-sensors = <&tsens0 4>;
2164 cpu3_alert0: trip-point0 {
2165 temperature = <90000>;
2166 hysteresis = <2000>;
2170 cpu3_alert1: trip-point1 {
2171 temperature = <95000>;
2172 hysteresis = <2000>;
2176 cpu3_crit: cpu_crit {
2177 temperature = <110000>;
2178 hysteresis = <1000>;
2185 trip = <&cpu3_alert0>;
2186 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2187 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2188 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2189 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2190 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2191 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2194 trip = <&cpu3_alert1>;
2195 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2196 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2197 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2198 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2199 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2200 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2206 polling-delay-passive = <250>;
2207 polling-delay = <1000>;
2209 thermal-sensors = <&tsens0 5>;
2212 cpu4_alert0: trip-point0 {
2213 temperature = <90000>;
2214 hysteresis = <2000>;
2218 cpu4_alert1: trip-point1 {
2219 temperature = <95000>;
2220 hysteresis = <2000>;
2224 cpu4_crit: cpu_crit {
2225 temperature = <110000>;
2226 hysteresis = <1000>;
2233 trip = <&cpu4_alert0>;
2234 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2235 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2236 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2237 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2238 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2239 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2242 trip = <&cpu4_alert1>;
2243 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2244 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2245 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2246 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2247 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2248 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2254 polling-delay-passive = <250>;
2255 polling-delay = <1000>;
2257 thermal-sensors = <&tsens0 6>;
2260 cpu5_alert0: trip-point0 {
2261 temperature = <90000>;
2262 hysteresis = <2000>;
2266 cpu5_alert1: trip-point1 {
2267 temperature = <95000>;
2268 hysteresis = <2000>;
2272 cpu5_crit: cpu_crit {
2273 temperature = <110000>;
2274 hysteresis = <1000>;
2281 trip = <&cpu5_alert0>;
2282 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2283 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2284 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2285 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2286 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2287 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2290 trip = <&cpu5_alert1>;
2291 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2292 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2293 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2294 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2295 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2296 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2302 polling-delay-passive = <250>;
2303 polling-delay = <1000>;
2305 thermal-sensors = <&tsens0 9>;
2308 cpu6_alert0: trip-point0 {
2309 temperature = <90000>;
2310 hysteresis = <2000>;
2314 cpu6_alert1: trip-point1 {
2315 temperature = <95000>;
2316 hysteresis = <2000>;
2320 cpu6_crit: cpu_crit {
2321 temperature = <110000>;
2322 hysteresis = <1000>;
2329 trip = <&cpu6_alert0>;
2330 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2331 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2334 trip = <&cpu6_alert1>;
2335 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2336 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2342 polling-delay-passive = <250>;
2343 polling-delay = <1000>;
2345 thermal-sensors = <&tsens0 10>;
2348 cpu7_alert0: trip-point0 {
2349 temperature = <90000>;
2350 hysteresis = <2000>;
2354 cpu7_alert1: trip-point1 {
2355 temperature = <95000>;
2356 hysteresis = <2000>;
2360 cpu7_crit: cpu_crit {
2361 temperature = <110000>;
2362 hysteresis = <1000>;
2369 trip = <&cpu7_alert0>;
2370 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2371 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2374 trip = <&cpu7_alert1>;
2375 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2376 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2382 polling-delay-passive = <250>;
2383 polling-delay = <1000>;
2385 thermal-sensors = <&tsens0 11>;
2388 cpu8_alert0: trip-point0 {
2389 temperature = <90000>;
2390 hysteresis = <2000>;
2394 cpu8_alert1: trip-point1 {
2395 temperature = <95000>;
2396 hysteresis = <2000>;
2400 cpu8_crit: cpu_crit {
2401 temperature = <110000>;
2402 hysteresis = <1000>;
2409 trip = <&cpu8_alert0>;
2410 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2411 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2414 trip = <&cpu8_alert1>;
2415 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2416 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2422 polling-delay-passive = <250>;
2423 polling-delay = <1000>;
2425 thermal-sensors = <&tsens0 12>;
2428 cpu9_alert0: trip-point0 {
2429 temperature = <90000>;
2430 hysteresis = <2000>;
2434 cpu9_alert1: trip-point1 {
2435 temperature = <95000>;
2436 hysteresis = <2000>;
2440 cpu9_crit: cpu_crit {
2441 temperature = <110000>;
2442 hysteresis = <1000>;
2449 trip = <&cpu9_alert0>;
2450 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2451 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2454 trip = <&cpu9_alert1>;
2455 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
2456 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
2462 polling-delay-passive = <250>;
2463 polling-delay = <1000>;
2465 thermal-sensors = <&tsens0 0>;
2468 aoss0_alert0: trip-point0 {
2469 temperature = <90000>;
2470 hysteresis = <2000>;
2474 aoss0_crit: aoss0_crit {
2475 temperature = <110000>;
2476 hysteresis = <2000>;
2483 polling-delay-passive = <250>;
2484 polling-delay = <1000>;
2486 thermal-sensors = <&tsens0 7>;
2489 cpuss0_alert0: trip-point0 {
2490 temperature = <90000>;
2491 hysteresis = <2000>;
2494 cpuss0_crit: cluster0_crit {
2495 temperature = <110000>;
2496 hysteresis = <2000>;
2503 polling-delay-passive = <250>;
2504 polling-delay = <1000>;
2506 thermal-sensors = <&tsens0 8>;
2509 cpuss1_alert0: trip-point0 {
2510 temperature = <90000>;
2511 hysteresis = <2000>;
2514 cpuss1_crit: cluster0_crit {
2515 temperature = <110000>;
2516 hysteresis = <2000>;
2523 polling-delay-passive = <250>;
2524 polling-delay = <1000>;
2526 thermal-sensors = <&tsens0 13>;
2529 gpuss0_alert0: trip-point0 {
2530 temperature = <90000>;
2531 hysteresis = <2000>;
2535 gpuss0_crit: gpuss0_crit {
2536 temperature = <110000>;
2537 hysteresis = <2000>;
2544 polling-delay-passive = <250>;
2545 polling-delay = <1000>;
2547 thermal-sensors = <&tsens0 14>;
2550 gpuss1_alert0: trip-point0 {
2551 temperature = <90000>;
2552 hysteresis = <2000>;
2556 gpuss1_crit: gpuss1_crit {
2557 temperature = <110000>;
2558 hysteresis = <2000>;
2565 polling-delay-passive = <250>;
2566 polling-delay = <1000>;
2568 thermal-sensors = <&tsens1 0>;
2571 aoss1_alert0: trip-point0 {
2572 temperature = <90000>;
2573 hysteresis = <2000>;
2577 aoss1_crit: aoss1_crit {
2578 temperature = <110000>;
2579 hysteresis = <2000>;
2586 polling-delay-passive = <250>;
2587 polling-delay = <1000>;
2589 thermal-sensors = <&tsens1 1>;
2592 cwlan_alert0: trip-point0 {
2593 temperature = <90000>;
2594 hysteresis = <2000>;
2598 cwlan_crit: cwlan_crit {
2599 temperature = <110000>;
2600 hysteresis = <2000>;
2607 polling-delay-passive = <250>;
2608 polling-delay = <1000>;
2610 thermal-sensors = <&tsens1 2>;
2613 audio_alert0: trip-point0 {
2614 temperature = <90000>;
2615 hysteresis = <2000>;
2619 audio_crit: audio_crit {
2620 temperature = <110000>;
2621 hysteresis = <2000>;
2628 polling-delay-passive = <250>;
2629 polling-delay = <1000>;
2631 thermal-sensors = <&tsens1 3>;
2634 ddr_alert0: trip-point0 {
2635 temperature = <90000>;
2636 hysteresis = <2000>;
2640 ddr_crit: ddr_crit {
2641 temperature = <110000>;
2642 hysteresis = <2000>;
2649 polling-delay-passive = <250>;
2650 polling-delay = <1000>;
2652 thermal-sensors = <&tsens1 4>;
2655 q6_hvx_alert0: trip-point0 {
2656 temperature = <90000>;
2657 hysteresis = <2000>;
2661 q6_hvx_crit: q6_hvx_crit {
2662 temperature = <110000>;
2663 hysteresis = <2000>;
2670 polling-delay-passive = <250>;
2671 polling-delay = <1000>;
2673 thermal-sensors = <&tsens1 5>;
2676 camera_alert0: trip-point0 {
2677 temperature = <90000>;
2678 hysteresis = <2000>;
2682 camera_crit: camera_crit {
2683 temperature = <110000>;
2684 hysteresis = <2000>;
2691 polling-delay-passive = <250>;
2692 polling-delay = <1000>;
2694 thermal-sensors = <&tsens1 6>;
2697 mdm_alert0: trip-point0 {
2698 temperature = <90000>;
2699 hysteresis = <2000>;
2703 mdm_crit: mdm_crit {
2704 temperature = <110000>;
2705 hysteresis = <2000>;
2712 polling-delay-passive = <250>;
2713 polling-delay = <1000>;
2715 thermal-sensors = <&tsens1 7>;
2718 mdm_dsp_alert0: trip-point0 {
2719 temperature = <90000>;
2720 hysteresis = <2000>;
2724 mdm_dsp_crit: mdm_dsp_crit {
2725 temperature = <110000>;
2726 hysteresis = <2000>;
2733 polling-delay-passive = <250>;
2734 polling-delay = <1000>;
2736 thermal-sensors = <&tsens1 8>;
2739 npu_alert0: trip-point0 {
2740 temperature = <90000>;
2741 hysteresis = <2000>;
2745 npu_crit: npu_crit {
2746 temperature = <110000>;
2747 hysteresis = <2000>;
2754 polling-delay-passive = <250>;
2755 polling-delay = <1000>;
2757 thermal-sensors = <&tsens1 9>;
2760 video_alert0: trip-point0 {
2761 temperature = <90000>;
2762 hysteresis = <2000>;
2766 video_crit: video_crit {
2767 temperature = <110000>;
2768 hysteresis = <2000>;
2776 compatible = "arm,armv8-timer";
2777 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
2778 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
2779 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
2780 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;