1 // SPDX-License-Identifier: GPL-2.0
3 * SDM845 SoC device tree source
5 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
8 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
9 #include <dt-bindings/clock/qcom,rpmh.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
14 interrupt-parent = <&intc>;
57 device_type = "memory";
58 /* We expect the bootloader to fill in the size */
59 reg = <0 0x80000000 0 0>;
68 reg = <0 0x85fc0000 0 0x20000>;
73 compatible = "qcom,cmd-db";
74 reg = <0x0 0x85fe0000 0x0 0x20000>;
78 smem_mem: memory@86000000 {
79 reg = <0x0 0x86000000 0x0 0x200000>;
84 reg = <0 0x86200000 0 0x2d00000>;
95 compatible = "qcom,kryo385";
97 enable-method = "psci";
98 next-level-cache = <&L2_0>;
100 compatible = "cache";
101 next-level-cache = <&L3_0>;
103 compatible = "cache";
110 compatible = "qcom,kryo385";
112 enable-method = "psci";
113 next-level-cache = <&L2_100>;
115 compatible = "cache";
116 next-level-cache = <&L3_0>;
122 compatible = "qcom,kryo385";
124 enable-method = "psci";
125 next-level-cache = <&L2_200>;
127 compatible = "cache";
128 next-level-cache = <&L3_0>;
134 compatible = "qcom,kryo385";
136 enable-method = "psci";
137 next-level-cache = <&L2_300>;
139 compatible = "cache";
140 next-level-cache = <&L3_0>;
146 compatible = "qcom,kryo385";
148 enable-method = "psci";
149 next-level-cache = <&L2_400>;
151 compatible = "cache";
152 next-level-cache = <&L3_0>;
158 compatible = "qcom,kryo385";
160 enable-method = "psci";
161 next-level-cache = <&L2_500>;
163 compatible = "cache";
164 next-level-cache = <&L3_0>;
170 compatible = "qcom,kryo385";
172 enable-method = "psci";
173 next-level-cache = <&L2_600>;
175 compatible = "cache";
176 next-level-cache = <&L3_0>;
182 compatible = "qcom,kryo385";
184 enable-method = "psci";
185 next-level-cache = <&L2_700>;
187 compatible = "cache";
188 next-level-cache = <&L3_0>;
194 compatible = "arm,armv8-pmuv3";
195 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
199 compatible = "arm,armv8-timer";
200 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
201 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
202 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
203 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
208 compatible = "fixed-clock";
210 clock-frequency = <38400000>;
211 clock-output-names = "xo_board";
214 sleep_clk: sleep-clk {
215 compatible = "fixed-clock";
217 clock-frequency = <32764>;
222 compatible = "qcom,tcsr-mutex";
223 syscon = <&tcsr_mutex_regs 0 0x1000>;
228 compatible = "qcom,smem";
229 memory-region = <&smem_mem>;
230 hwlocks = <&tcsr_mutex 3>;
234 compatible = "arm,psci-1.0";
239 #address-cells = <1>;
241 ranges = <0 0 0 0xffffffff>;
242 compatible = "simple-bus";
244 gcc: clock-controller@100000 {
245 compatible = "qcom,gcc-sdm845";
246 reg = <0x100000 0x1f0000>;
249 #power-domain-cells = <1>;
252 qupv3_id_0: geniqup@8c0000 {
253 compatible = "qcom,geni-se-qup";
254 reg = <0x8c0000 0x6000>;
255 clock-names = "m-ahb", "s-ahb";
256 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
257 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
258 #address-cells = <1>;
264 compatible = "qcom,geni-i2c";
265 reg = <0x880000 0x4000>;
267 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
268 pinctrl-names = "default";
269 pinctrl-0 = <&qup_i2c0_default>;
270 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
271 #address-cells = <1>;
277 compatible = "qcom,geni-spi";
278 reg = <0x880000 0x4000>;
280 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
281 pinctrl-names = "default";
282 pinctrl-0 = <&qup_spi0_default>;
283 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
284 #address-cells = <1>;
290 compatible = "qcom,geni-i2c";
291 reg = <0x884000 0x4000>;
293 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
294 pinctrl-names = "default";
295 pinctrl-0 = <&qup_i2c1_default>;
296 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
297 #address-cells = <1>;
303 compatible = "qcom,geni-spi";
304 reg = <0x884000 0x4000>;
306 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
307 pinctrl-names = "default";
308 pinctrl-0 = <&qup_spi1_default>;
309 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
310 #address-cells = <1>;
316 compatible = "qcom,geni-i2c";
317 reg = <0x888000 0x4000>;
319 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
320 pinctrl-names = "default";
321 pinctrl-0 = <&qup_i2c2_default>;
322 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
323 #address-cells = <1>;
329 compatible = "qcom,geni-spi";
330 reg = <0x888000 0x4000>;
332 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
333 pinctrl-names = "default";
334 pinctrl-0 = <&qup_spi2_default>;
335 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
336 #address-cells = <1>;
342 compatible = "qcom,geni-i2c";
343 reg = <0x88c000 0x4000>;
345 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
346 pinctrl-names = "default";
347 pinctrl-0 = <&qup_i2c3_default>;
348 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
349 #address-cells = <1>;
355 compatible = "qcom,geni-spi";
356 reg = <0x88c000 0x4000>;
358 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
359 pinctrl-names = "default";
360 pinctrl-0 = <&qup_spi3_default>;
361 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
362 #address-cells = <1>;
368 compatible = "qcom,geni-i2c";
369 reg = <0x890000 0x4000>;
371 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
372 pinctrl-names = "default";
373 pinctrl-0 = <&qup_i2c4_default>;
374 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
375 #address-cells = <1>;
381 compatible = "qcom,geni-spi";
382 reg = <0x890000 0x4000>;
384 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
385 pinctrl-names = "default";
386 pinctrl-0 = <&qup_spi4_default>;
387 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
388 #address-cells = <1>;
394 compatible = "qcom,geni-i2c";
395 reg = <0x894000 0x4000>;
397 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
398 pinctrl-names = "default";
399 pinctrl-0 = <&qup_i2c5_default>;
400 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
401 #address-cells = <1>;
407 compatible = "qcom,geni-spi";
408 reg = <0x894000 0x4000>;
410 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
411 pinctrl-names = "default";
412 pinctrl-0 = <&qup_spi5_default>;
413 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
414 #address-cells = <1>;
420 compatible = "qcom,geni-i2c";
421 reg = <0x898000 0x4000>;
423 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
424 pinctrl-names = "default";
425 pinctrl-0 = <&qup_i2c6_default>;
426 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
427 #address-cells = <1>;
433 compatible = "qcom,geni-spi";
434 reg = <0x898000 0x4000>;
436 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
437 pinctrl-names = "default";
438 pinctrl-0 = <&qup_spi6_default>;
439 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
440 #address-cells = <1>;
446 compatible = "qcom,geni-i2c";
447 reg = <0x89c000 0x4000>;
449 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
450 pinctrl-names = "default";
451 pinctrl-0 = <&qup_i2c7_default>;
452 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
453 #address-cells = <1>;
459 compatible = "qcom,geni-spi";
460 reg = <0x89c000 0x4000>;
462 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
463 pinctrl-names = "default";
464 pinctrl-0 = <&qup_spi7_default>;
465 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
466 #address-cells = <1>;
472 qupv3_id_1: geniqup@ac0000 {
473 compatible = "qcom,geni-se-qup";
474 reg = <0xac0000 0x6000>;
475 clock-names = "m-ahb", "s-ahb";
476 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
477 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
478 #address-cells = <1>;
484 compatible = "qcom,geni-i2c";
485 reg = <0xa80000 0x4000>;
487 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
488 pinctrl-names = "default";
489 pinctrl-0 = <&qup_i2c8_default>;
490 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
491 #address-cells = <1>;
497 compatible = "qcom,geni-spi";
498 reg = <0xa80000 0x4000>;
500 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
501 pinctrl-names = "default";
502 pinctrl-0 = <&qup_spi8_default>;
503 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
504 #address-cells = <1>;
510 compatible = "qcom,geni-i2c";
511 reg = <0xa84000 0x4000>;
513 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
514 pinctrl-names = "default";
515 pinctrl-0 = <&qup_i2c9_default>;
516 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
517 #address-cells = <1>;
523 compatible = "qcom,geni-spi";
524 reg = <0xa84000 0x4000>;
526 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
527 pinctrl-names = "default";
528 pinctrl-0 = <&qup_spi9_default>;
529 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
530 #address-cells = <1>;
535 uart9: serial@a84000 {
536 compatible = "qcom,geni-debug-uart";
537 reg = <0xa84000 0x4000>;
539 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
540 pinctrl-names = "default";
541 pinctrl-0 = <&qup_uart9_default>;
542 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
547 compatible = "qcom,geni-i2c";
548 reg = <0xa88000 0x4000>;
550 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
551 pinctrl-names = "default";
552 pinctrl-0 = <&qup_i2c10_default>;
553 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
554 #address-cells = <1>;
560 compatible = "qcom,geni-spi";
561 reg = <0xa88000 0x4000>;
563 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
564 pinctrl-names = "default";
565 pinctrl-0 = <&qup_spi10_default>;
566 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
567 #address-cells = <1>;
573 compatible = "qcom,geni-i2c";
574 reg = <0xa8c000 0x4000>;
576 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
577 pinctrl-names = "default";
578 pinctrl-0 = <&qup_i2c11_default>;
579 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
580 #address-cells = <1>;
586 compatible = "qcom,geni-spi";
587 reg = <0xa8c000 0x4000>;
589 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
590 pinctrl-names = "default";
591 pinctrl-0 = <&qup_spi11_default>;
592 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
593 #address-cells = <1>;
599 compatible = "qcom,geni-i2c";
600 reg = <0xa90000 0x4000>;
602 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
603 pinctrl-names = "default";
604 pinctrl-0 = <&qup_i2c12_default>;
605 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
606 #address-cells = <1>;
612 compatible = "qcom,geni-spi";
613 reg = <0xa90000 0x4000>;
615 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
616 pinctrl-names = "default";
617 pinctrl-0 = <&qup_spi12_default>;
618 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
619 #address-cells = <1>;
625 compatible = "qcom,geni-i2c";
626 reg = <0xa94000 0x4000>;
628 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
629 pinctrl-names = "default";
630 pinctrl-0 = <&qup_i2c13_default>;
631 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
632 #address-cells = <1>;
638 compatible = "qcom,geni-spi";
639 reg = <0xa94000 0x4000>;
641 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
642 pinctrl-names = "default";
643 pinctrl-0 = <&qup_spi13_default>;
644 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
645 #address-cells = <1>;
651 compatible = "qcom,geni-i2c";
652 reg = <0xa98000 0x4000>;
654 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
655 pinctrl-names = "default";
656 pinctrl-0 = <&qup_i2c14_default>;
657 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
658 #address-cells = <1>;
664 compatible = "qcom,geni-spi";
665 reg = <0xa98000 0x4000>;
667 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
668 pinctrl-names = "default";
669 pinctrl-0 = <&qup_spi14_default>;
670 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
671 #address-cells = <1>;
677 compatible = "qcom,geni-i2c";
678 reg = <0xa9c000 0x4000>;
680 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
681 pinctrl-names = "default";
682 pinctrl-0 = <&qup_i2c15_default>;
683 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
684 #address-cells = <1>;
690 compatible = "qcom,geni-spi";
691 reg = <0xa9c000 0x4000>;
693 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
694 pinctrl-names = "default";
695 pinctrl-0 = <&qup_spi15_default>;
696 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
697 #address-cells = <1>;
703 tcsr_mutex_regs: syscon@1f40000 {
704 compatible = "syscon";
705 reg = <0x1f40000 0x40000>;
708 tlmm: pinctrl@3400000 {
709 compatible = "qcom,sdm845-pinctrl";
710 reg = <0x03400000 0xc00000>;
711 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
714 interrupt-controller;
715 #interrupt-cells = <2>;
717 qup_i2c0_default: qup-i2c0-default {
719 pins = "gpio0", "gpio1";
724 qup_i2c1_default: qup-i2c1-default {
726 pins = "gpio17", "gpio18";
731 qup_i2c2_default: qup-i2c2-default {
733 pins = "gpio27", "gpio28";
738 qup_i2c3_default: qup-i2c3-default {
740 pins = "gpio41", "gpio42";
745 qup_i2c4_default: qup-i2c4-default {
747 pins = "gpio89", "gpio90";
752 qup_i2c5_default: qup-i2c5-default {
754 pins = "gpio85", "gpio86";
759 qup_i2c6_default: qup-i2c6-default {
761 pins = "gpio45", "gpio46";
766 qup_i2c7_default: qup-i2c7-default {
768 pins = "gpio93", "gpio94";
773 qup_i2c8_default: qup-i2c8-default {
775 pins = "gpio65", "gpio66";
780 qup_i2c9_default: qup-i2c9-default {
782 pins = "gpio6", "gpio7";
787 qup_i2c10_default: qup-i2c10-default {
789 pins = "gpio55", "gpio56";
794 qup_i2c11_default: qup-i2c11-default {
796 pins = "gpio31", "gpio32";
801 qup_i2c12_default: qup-i2c12-default {
803 pins = "gpio49", "gpio50";
808 qup_i2c13_default: qup-i2c13-default {
810 pins = "gpio105", "gpio106";
815 qup_i2c14_default: qup-i2c14-default {
817 pins = "gpio33", "gpio34";
822 qup_i2c15_default: qup-i2c15-default {
824 pins = "gpio81", "gpio82";
829 qup_spi0_default: qup-spi0-default {
831 pins = "gpio0", "gpio1",
837 qup_spi1_default: qup-spi1-default {
839 pins = "gpio17", "gpio18",
845 qup_spi2_default: qup-spi2-default {
847 pins = "gpio27", "gpio28",
853 qup_spi3_default: qup-spi3-default {
855 pins = "gpio41", "gpio42",
861 qup_spi4_default: qup-spi4-default {
863 pins = "gpio89", "gpio90",
869 qup_spi5_default: qup-spi5-default {
871 pins = "gpio85", "gpio86",
877 qup_spi6_default: qup-spi6-default {
879 pins = "gpio45", "gpio46",
885 qup_spi7_default: qup-spi7-default {
887 pins = "gpio93", "gpio94",
893 qup_spi8_default: qup-spi8-default {
895 pins = "gpio65", "gpio66",
901 qup_spi9_default: qup-spi9-default {
903 pins = "gpio6", "gpio7",
909 qup_spi10_default: qup-spi10-default {
911 pins = "gpio55", "gpio56",
917 qup_spi11_default: qup-spi11-default {
919 pins = "gpio31", "gpio32",
925 qup_spi12_default: qup-spi12-default {
927 pins = "gpio49", "gpio50",
933 qup_spi13_default: qup-spi13-default {
935 pins = "gpio105", "gpio106",
936 "gpio107", "gpio108";
941 qup_spi14_default: qup-spi14-default {
943 pins = "gpio33", "gpio34",
949 qup_spi15_default: qup-spi15-default {
951 pins = "gpio81", "gpio82",
957 qup_uart9_default: qup-uart9-default {
959 pins = "gpio4", "gpio5";
965 tsens0: thermal-sensor@c263000 {
966 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
967 reg = <0xc263000 0x1ff>, /* TM */
968 <0xc222000 0x1ff>; /* SROT */
969 #qcom,sensors = <13>;
970 #thermal-sensor-cells = <1>;
973 tsens1: thermal-sensor@c265000 {
974 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2";
975 reg = <0xc265000 0x1ff>, /* TM */
976 <0xc223000 0x1ff>; /* SROT */
978 #thermal-sensor-cells = <1>;
981 spmi_bus: spmi@c440000 {
982 compatible = "qcom,spmi-pmic-arb";
983 reg = <0xc440000 0x1100>,
984 <0xc600000 0x2000000>,
985 <0xe600000 0x100000>,
988 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
989 interrupt-names = "periph_irq";
990 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
993 #address-cells = <2>;
995 interrupt-controller;
996 #interrupt-cells = <4>;
1000 apss_shared: mailbox@17990000 {
1001 compatible = "qcom,sdm845-apss-shared";
1002 reg = <0x17990000 0x1000>;
1006 apps_rsc: rsc@179c0000 {
1008 compatible = "qcom,rpmh-rsc";
1009 reg = <0x179c0000 0x10000>,
1010 <0x179d0000 0x10000>,
1011 <0x179e0000 0x10000>;
1012 reg-names = "drv-0", "drv-1", "drv-2";
1013 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
1014 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
1015 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1016 qcom,tcs-offset = <0xd00>;
1018 qcom,tcs-config = <ACTIVE_TCS 2>,
1023 rpmhcc: clock-controller {
1024 compatible = "qcom,sdm845-rpmh-clk";
1029 intc: interrupt-controller@17a00000 {
1030 compatible = "arm,gic-v3";
1031 #address-cells = <1>;
1034 #interrupt-cells = <3>;
1035 interrupt-controller;
1036 reg = <0x17a00000 0x10000>, /* GICD */
1037 <0x17a60000 0x100000>; /* GICR * 8 */
1038 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1041 compatible = "arm,gic-v3-its";
1044 reg = <0x17a40000 0x20000>;
1045 status = "disabled";
1050 #address-cells = <1>;
1053 compatible = "arm,armv7-timer-mem";
1054 reg = <0x17c90000 0x1000>;
1058 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1059 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1060 reg = <0x17ca0000 0x1000>,
1061 <0x17cb0000 0x1000>;
1066 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1067 reg = <0x17cc0000 0x1000>;
1068 status = "disabled";
1073 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1074 reg = <0x17cd0000 0x1000>;
1075 status = "disabled";
1080 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1081 reg = <0x17ce0000 0x1000>;
1082 status = "disabled";
1087 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1088 reg = <0x17cf0000 0x1000>;
1089 status = "disabled";
1094 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1095 reg = <0x17d00000 0x1000>;
1096 status = "disabled";
1101 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1102 reg = <0x17d10000 0x1000>;
1103 status = "disabled";