sys/gnu/dts/arm64/qcom/sm8150.dtsi

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /*
   3  * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
   4  * Copyright (c) 2019, Linaro Limited
   5  */
   6
   7 #include <dt-bindings/interrupt-controller/arm-gic.h>
   8 #include <dt-bindings/power/qcom-aoss-qmp.h>
   9 #include <dt-bindings/power/qcom-rpmpd.h>
  10 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
  11 #include <dt-bindings/clock/qcom,rpmh.h>
  12 #include <dt-bindings/clock/qcom,gcc-sm8150.h>
  13
  14 / {
  15         interrupt-parent = <&intc>;
  16
  17         #address-cells = <2>;
  18         #size-cells = <2>;
  19
  20         chosen { };
  21
  22         clocks {
  23                 xo_board: xo-board {
  24                         compatible = "fixed-clock";
  25                         #clock-cells = <0>;
  26                         clock-frequency = <38400000>;
  27                         clock-output-names = "xo_board";
  28                 };
  29
  30                 sleep_clk: sleep-clk {
  31                         compatible = "fixed-clock";
  32                         #clock-cells = <0>;
  33                         clock-frequency = <32764>;
  34                         clock-output-names = "sleep_clk";
  35                 };
  36         };
  37
  38         cpus {
  39                 #address-cells = <2>;
  40                 #size-cells = <0>;
  41
  42                 CPU0: cpu@0 {
  43                         device_type = "cpu";
  44                         compatible = "qcom,kryo485";
  45                         reg = <0x0 0x0>;
  46                         enable-method = "psci";
  47                         next-level-cache = <&L2_0>;
  48                         qcom,freq-domain = <&cpufreq_hw 0>;
  49                         L2_0: l2-cache {
  50                                 compatible = "cache";
  51                                 next-level-cache = <&L3_0>;
  52                                 L3_0: l3-cache {
  53                                       compatible = "cache";
  54                                 };
  55                         };
  56                 };
  57
  58                 CPU1: cpu@100 {
  59                         device_type = "cpu";
  60                         compatible = "qcom,kryo485";
  61                         reg = <0x0 0x100>;
  62                         enable-method = "psci";
  63                         next-level-cache = <&L2_100>;
  64                         qcom,freq-domain = <&cpufreq_hw 0>;
  65                         L2_100: l2-cache {
  66                                 compatible = "cache";
  67                                 next-level-cache = <&L3_0>;
  68                         };
  69
  70                 };
  71
  72                 CPU2: cpu@200 {
  73                         device_type = "cpu";
  74                         compatible = "qcom,kryo485";
  75                         reg = <0x0 0x200>;
  76                         enable-method = "psci";
  77                         next-level-cache = <&L2_200>;
  78                         qcom,freq-domain = <&cpufreq_hw 0>;
  79                         L2_200: l2-cache {
  80                                 compatible = "cache";
  81                                 next-level-cache = <&L3_0>;
  82                         };
  83                 };
  84
  85                 CPU3: cpu@300 {
  86                         device_type = "cpu";
  87                         compatible = "qcom,kryo485";
  88                         reg = <0x0 0x300>;
  89                         enable-method = "psci";
  90                         next-level-cache = <&L2_300>;
  91                         qcom,freq-domain = <&cpufreq_hw 0>;
  92                         L2_300: l2-cache {
  93                                 compatible = "cache";
  94                                 next-level-cache = <&L3_0>;
  95                         };
  96                 };
  97
  98                 CPU4: cpu@400 {
  99                         device_type = "cpu";
 100                         compatible = "qcom,kryo485";
 101                         reg = <0x0 0x400>;
 102                         enable-method = "psci";
 103                         next-level-cache = <&L2_400>;
 104                         qcom,freq-domain = <&cpufreq_hw 1>;
 105                         L2_400: l2-cache {
 106                                 compatible = "cache";
 107                                 next-level-cache = <&L3_0>;
 108                         };
 109                 };
 110
 111                 CPU5: cpu@500 {
 112                         device_type = "cpu";
 113                         compatible = "qcom,kryo485";
 114                         reg = <0x0 0x500>;
 115                         enable-method = "psci";
 116                         next-level-cache = <&L2_500>;
 117                         qcom,freq-domain = <&cpufreq_hw 1>;
 118                         L2_500: l2-cache {
 119                                 compatible = "cache";
 120                                 next-level-cache = <&L3_0>;
 121                         };
 122                 };
 123
 124                 CPU6: cpu@600 {
 125                         device_type = "cpu";
 126                         compatible = "qcom,kryo485";
 127                         reg = <0x0 0x600>;
 128                         enable-method = "psci";
 129                         next-level-cache = <&L2_600>;
 130                         qcom,freq-domain = <&cpufreq_hw 1>;
 131                         L2_600: l2-cache {
 132                                 compatible = "cache";
 133                                 next-level-cache = <&L3_0>;
 134                         };
 135                 };
 136
 137                 CPU7: cpu@700 {
 138                         device_type = "cpu";
 139                         compatible = "qcom,kryo485";
 140                         reg = <0x0 0x700>;
 141                         enable-method = "psci";
 142                         next-level-cache = <&L2_700>;
 143                         qcom,freq-domain = <&cpufreq_hw 2>;
 144                         L2_700: l2-cache {
 145                                 compatible = "cache";
 146                                 next-level-cache = <&L3_0>;
 147                         };
 148                 };
 149         };
 150
 151         firmware {
 152                 scm: scm {
 153                         compatible = "qcom,scm-sm8150", "qcom,scm";
 154                         #reset-cells = <1>;
 155                 };
 156         };
 157
 158         tcsr_mutex: hwlock {
 159                 compatible = "qcom,tcsr-mutex";
 160                 syscon = <&tcsr_mutex_regs 0 0x1000>;
 161                 #hwlock-cells = <1>;
 162         };
 163
 164         memory@80000000 {
 165                 device_type = "memory";
 166                 /* We expect the bootloader to fill in the size */
 167                 reg = <0x0 0x80000000 0x0 0x0>;
 168         };
 169
 170         pmu {
 171                 compatible = "arm,armv8-pmuv3";
 172                 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
 173         };
 174
 175         psci {
 176                 compatible = "arm,psci-1.0";
 177                 method = "smc";
 178         };
 179
 180         reserved-memory {
 181                 #address-cells = <2>;
 182                 #size-cells = <2>;
 183                 ranges;
 184
 185                 hyp_mem: memory@85700000 {
 186                         reg = <0x0 0x85700000 0x0 0x600000>;
 187                         no-map;
 188                 };
 189
 190                 xbl_mem: memory@85d00000 {
 191                         reg = <0x0 0x85d00000 0x0 0x140000>;
 192                         no-map;
 193                 };
 194
 195                 aop_mem: memory@85f00000 {
 196                         reg = <0x0 0x85f00000 0x0 0x20000>;
 197                         no-map;
 198                 };
 199
 200                 aop_cmd_db: memory@85f20000 {
 201                         compatible = "qcom,cmd-db";
 202                         reg = <0x0 0x85f20000 0x0 0x20000>;
 203                         no-map;
 204                 };
 205
 206                 smem_mem: memory@86000000 {
 207                         reg = <0x0 0x86000000 0x0 0x200000>;
 208                         no-map;
 209                 };
 210
 211                 tz_mem: memory@86200000 {
 212                         reg = <0x0 0x86200000 0x0 0x3900000>;
 213                         no-map;
 214                 };
 215
 216                 rmtfs_mem: memory@89b00000 {
 217                         compatible = "qcom,rmtfs-mem";
 218                         reg = <0x0 0x89b00000 0x0 0x200000>;
 219                         no-map;
 220
 221                         qcom,client-id = <1>;
 222                         qcom,vmid = <15>;
 223                 };
 224
 225                 camera_mem: memory@8b700000 {
 226                         reg = <0x0 0x8b700000 0x0 0x500000>;
 227                         no-map;
 228                 };
 229
 230                 wlan_mem: memory@8bc00000 {
 231                         reg = <0x0 0x8bc00000 0x0 0x180000>;
 232                         no-map;
 233                 };
 234
 235                 npu_mem: memory@8bd80000 {
 236                         reg = <0x0 0x8bd80000 0x0 0x80000>;
 237                         no-map;
 238                 };
 239
 240                 adsp_mem: memory@8be00000 {
 241                         reg = <0x0 0x8be00000 0x0 0x1a00000>;
 242                         no-map;
 243                 };
 244
 245                 mpss_mem: memory@8d800000 {
 246                         reg = <0x0 0x8d800000 0x0 0x9600000>;
 247                         no-map;
 248                 };
 249
 250                 venus_mem: memory@96e00000 {
 251                         reg = <0x0 0x96e00000 0x0 0x500000>;
 252                         no-map;
 253                 };
 254
 255                 slpi_mem: memory@97300000 {
 256                         reg = <0x0 0x97300000 0x0 0x1400000>;
 257                         no-map;
 258                 };
 259
 260                 ipa_fw_mem: memory@98700000 {
 261                         reg = <0x0 0x98700000 0x0 0x10000>;
 262                         no-map;
 263                 };
 264
 265                 ipa_gsi_mem: memory@98710000 {
 266                         reg = <0x0 0x98710000 0x0 0x5000>;
 267                         no-map;
 268                 };
 269
 270                 gpu_mem: memory@98715000 {
 271                         reg = <0x0 0x98715000 0x0 0x2000>;
 272                         no-map;
 273                 };
 274
 275                 spss_mem: memory@98800000 {
 276                         reg = <0x0 0x98800000 0x0 0x100000>;
 277                         no-map;
 278                 };
 279
 280                 cdsp_mem: memory@98900000 {
 281                         reg = <0x0 0x98900000 0x0 0x1400000>;
 282                         no-map;
 283                 };
 284
 285                 qseecom_mem: memory@9e400000 {
 286                         reg = <0x0 0x9e400000 0x0 0x1400000>;
 287                         no-map;
 288                 };
 289         };
 290
 291         smem {
 292                 compatible = "qcom,smem";
 293                 memory-region = <&smem_mem>;
 294                 hwlocks = <&tcsr_mutex 3>;
 295         };
 296
 297         smp2p-cdsp {
 298                 compatible = "qcom,smp2p";
 299                 qcom,smem = <94>, <432>;
 300
 301                 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
 302
 303                 mboxes = <&apss_shared 6>;
 304
 305                 qcom,local-pid = <0>;
 306                 qcom,remote-pid = <5>;
 307
 308                 cdsp_smp2p_out: master-kernel {
 309                         qcom,entry-name = "master-kernel";
 310                         #qcom,smem-state-cells = <1>;
 311                 };
 312
 313                 cdsp_smp2p_in: slave-kernel {
 314                         qcom,entry-name = "slave-kernel";
 315
 316                         interrupt-controller;
 317                         #interrupt-cells = <2>;
 318                 };
 319         };
 320
 321         smp2p-lpass {
 322                 compatible = "qcom,smp2p";
 323                 qcom,smem = <443>, <429>;
 324
 325                 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
 326
 327                 mboxes = <&apss_shared 10>;
 328
 329                 qcom,local-pid = <0>;
 330                 qcom,remote-pid = <2>;
 331
 332                 adsp_smp2p_out: master-kernel {
 333                         qcom,entry-name = "master-kernel";
 334                         #qcom,smem-state-cells = <1>;
 335                 };
 336
 337                 adsp_smp2p_in: slave-kernel {
 338                         qcom,entry-name = "slave-kernel";
 339
 340                         interrupt-controller;
 341                         #interrupt-cells = <2>;
 342                 };
 343         };
 344
 345         smp2p-mpss {
 346                 compatible = "qcom,smp2p";
 347                 qcom,smem = <435>, <428>;
 348
 349                 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
 350
 351                 mboxes = <&apss_shared 14>;
 352
 353                 qcom,local-pid = <0>;
 354                 qcom,remote-pid = <1>;
 355
 356                 modem_smp2p_out: master-kernel {
 357                         qcom,entry-name = "master-kernel";
 358                         #qcom,smem-state-cells = <1>;
 359                 };
 360
 361                 modem_smp2p_in: slave-kernel {
 362                         qcom,entry-name = "slave-kernel";
 363
 364                         interrupt-controller;
 365                         #interrupt-cells = <2>;
 366                 };
 367         };
 368
 369         smp2p-slpi {
 370                 compatible = "qcom,smp2p";
 371                 qcom,smem = <481>, <430>;
 372
 373                 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
 374
 375                 mboxes = <&apss_shared 26>;
 376
 377                 qcom,local-pid = <0>;
 378                 qcom,remote-pid = <3>;
 379
 380                 slpi_smp2p_out: master-kernel {
 381                         qcom,entry-name = "master-kernel";
 382                         #qcom,smem-state-cells = <1>;
 383                 };
 384
 385                 slpi_smp2p_in: slave-kernel {
 386                         qcom,entry-name = "slave-kernel";
 387
 388                         interrupt-controller;
 389                         #interrupt-cells = <2>;
 390                 };
 391         };
 392
 393         soc: soc@0 {
 394                 #address-cells = <2>;
 395                 #size-cells = <2>;
 396                 ranges = <0 0 0 0 0x10 0>;
 397                 dma-ranges = <0 0 0 0 0x10 0>;
 398                 compatible = "simple-bus";
 399
 400                 gcc: clock-controller@100000 {
 401                         compatible = "qcom,gcc-sm8150";
 402                         reg = <0x0 0x00100000 0x0 0x1f0000>;
 403                         #clock-cells = <1>;
 404                         #reset-cells = <1>;
 405                         #power-domain-cells = <1>;
 406                         clock-names = "bi_tcxo",
 407                                       "sleep_clk";
 408                         clocks = <&rpmhcc RPMH_CXO_CLK>,
 409                                  <&sleep_clk>;
 410                 };
 411
 412                 qupv3_id_1: geniqup@ac0000 {
 413                         compatible = "qcom,geni-se-qup";
 414                         reg = <0x0 0x00ac0000 0x0 0x6000>;
 415                         clock-names = "m-ahb", "s-ahb";
 416                         clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
 417                                  <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
 418                         #address-cells = <2>;
 419                         #size-cells = <2>;
 420                         ranges;
 421                         status = "disabled";
 422
 423                         uart2: serial@a90000 {
 424                                 compatible = "qcom,geni-debug-uart";
 425                                 reg = <0x0 0x00a90000 0x0 0x4000>;
 426                                 clock-names = "se";
 427                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
 428                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
 429                                 status = "disabled";
 430                         };
 431                 };
 432
 433                 ufs_mem_hc: ufshc@1d84000 {
 434                         compatible = "qcom,sm8150-ufshc", "qcom,ufshc",
 435                                      "jedec,ufs-2.0";
 436                         reg = <0 0x01d84000 0 0x2500>;
 437                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
 438                         phys = <&ufs_mem_phy_lanes>;
 439                         phy-names = "ufsphy";
 440                         lanes-per-direction = <2>;
 441                         #reset-cells = <1>;
 442                         resets = <&gcc GCC_UFS_PHY_BCR>;
 443                         reset-names = "rst";
 444
 445                         clock-names =
 446                                 "core_clk",
 447                                 "bus_aggr_clk",
 448                                 "iface_clk",
 449                                 "core_clk_unipro",
 450                                 "ref_clk",
 451                                 "tx_lane0_sync_clk",
 452                                 "rx_lane0_sync_clk",
 453                                 "rx_lane1_sync_clk";
 454                         clocks =
 455                                 <&gcc GCC_UFS_PHY_AXI_CLK>,
 456                                 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
 457                                 <&gcc GCC_UFS_PHY_AHB_CLK>,
 458                                 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
 459                                 <&rpmhcc RPMH_CXO_CLK>,
 460                                 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
 461                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
 462                                 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
 463                         freq-table-hz =
 464                                 <37500000 300000000>,
 465                                 <0 0>,
 466                                 <0 0>,
 467                                 <37500000 300000000>,
 468                                 <0 0>,
 469                                 <0 0>,
 470                                 <0 0>,
 471                                 <0 0>;
 472
 473                         status = "disabled";
 474                 };
 475
 476                 ufs_mem_phy: phy@1d87000 {
 477                         compatible = "qcom,sm8150-qmp-ufs-phy";
 478                         reg = <0 0x01d87000 0 0x1c0>;
 479                         #address-cells = <2>;
 480                         #size-cells = <2>;
 481                         ranges;
 482                         clock-names = "ref",
 483                                       "ref_aux";
 484                         clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
 485                                  <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
 486
 487                         resets = <&ufs_mem_hc 0>;
 488                         reset-names = "ufsphy";
 489                         status = "disabled";
 490
 491                         ufs_mem_phy_lanes: lanes@1d87400 {
 492                                 reg = <0 0x01d87400 0 0x108>,
 493                                       <0 0x01d87600 0 0x1e0>,
 494                                       <0 0x01d87c00 0 0x1dc>,
 495                                       <0 0x01d87800 0 0x108>,
 496                                       <0 0x01d87a00 0 0x1e0>;
 497                                 #phy-cells = <0>;
 498                         };
 499                 };
 500
 501                 tcsr_mutex_regs: syscon@1f40000 {
 502                         compatible = "syscon";
 503                         reg = <0x0 0x01f40000 0x0 0x40000>;
 504                 };
 505
 506                 remoteproc_slpi: remoteproc@2400000 {
 507                         compatible = "qcom,sm8150-slpi-pas";
 508                         reg = <0x0 0x02400000 0x0 0x4040>;
 509
 510                         interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>,
 511                                               <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
 512                                               <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
 513                                               <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
 514                                               <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
 515                         interrupt-names = "wdog", "fatal", "ready",
 516                                           "handover", "stop-ack";
 517
 518                         clocks = <&rpmhcc RPMH_CXO_CLK>;
 519                         clock-names = "xo";
 520
 521                         power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>,
 522                                         <&rpmhpd 3>,
 523                                         <&rpmhpd 2>;
 524                         power-domain-names = "load_state", "lcx", "lmx";
 525
 526                         memory-region = <&slpi_mem>;
 527
 528                         qcom,smem-states = <&slpi_smp2p_out 0>;
 529                         qcom,smem-state-names = "stop";
 530
 531                         status = "disabled";
 532
 533                         glink-edge {
 534                                 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>;
 535                                 label = "dsps";
 536                                 qcom,remote-pid = <3>;
 537                                 mboxes = <&apss_shared 24>;
 538                         };
 539                 };
 540
 541                 tlmm: pinctrl@3100000 {
 542                         compatible = "qcom,sm8150-pinctrl";
 543                         reg = <0x0 0x03100000 0x0 0x300000>,
 544                               <0x0 0x03500000 0x0 0x300000>,
 545                               <0x0 0x03900000 0x0 0x300000>,
 546                               <0x0 0x03D00000 0x0 0x300000>;
 547                         reg-names = "west", "east", "north", "south";
 548                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 549                         gpio-ranges = <&tlmm 0 0 175>;
 550                         gpio-controller;
 551                         #gpio-cells = <2>;
 552                         interrupt-controller;
 553                         #interrupt-cells = <2>;
 554                 };
 555
 556                 remoteproc_mpss: remoteproc@4080000 {
 557                         compatible = "qcom,sm8150-mpss-pas";
 558                         reg = <0x0 0x04080000 0x0 0x4040>;
 559
 560                         interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
 561                                               <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
 562                                               <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
 563                                               <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
 564                                               <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
 565                                               <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
 566                         interrupt-names = "wdog", "fatal", "ready", "handover",
 567                                           "stop-ack", "shutdown-ack";
 568
 569                         clocks = <&rpmhcc RPMH_CXO_CLK>;
 570                         clock-names = "xo";
 571
 572                         power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>,
 573                                         <&rpmhpd 7>,
 574                                         <&rpmhpd 0>;
 575                         power-domain-names = "load_state", "cx", "mss";
 576
 577                         memory-region = <&mpss_mem>;
 578
 579                         qcom,smem-states = <&modem_smp2p_out 0>;
 580                         qcom,smem-state-names = "stop";
 581
 582                         glink-edge {
 583                                 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
 584                                 label = "modem";
 585                                 qcom,remote-pid = <1>;
 586                                 mboxes = <&apss_shared 12>;
 587                         };
 588                 };
 589
 590                 remoteproc_cdsp: remoteproc@8300000 {
 591                         compatible = "qcom,sm8150-cdsp-pas";
 592                         reg = <0x0 0x08300000 0x0 0x4040>;
 593
 594                         interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
 595                                               <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
 596                                               <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
 597                                               <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
 598                                               <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
 599                         interrupt-names = "wdog", "fatal", "ready",
 600                                           "handover", "stop-ack";
 601
 602                         clocks = <&rpmhcc RPMH_CXO_CLK>;
 603                         clock-names = "xo";
 604
 605                         power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>,
 606                                         <&rpmhpd 7>;
 607                         power-domain-names = "load_state", "cx";
 608
 609                         memory-region = <&cdsp_mem>;
 610
 611                         qcom,smem-states = <&cdsp_smp2p_out 0>;
 612                         qcom,smem-state-names = "stop";
 613
 614                         status = "disabled";
 615
 616                         glink-edge {
 617                                 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
 618                                 label = "cdsp";
 619                                 qcom,remote-pid = <5>;
 620                                 mboxes = <&apss_shared 4>;
 621                         };
 622                 };
 623
 624                 aoss_qmp: power-controller@c300000 {
 625                         compatible = "qcom,sm8150-aoss-qmp";
 626                         reg = <0x0 0x0c300000 0x0 0x100000>;
 627                         interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
 628                         mboxes = <&apss_shared 0>;
 629
 630                         #clock-cells = <0>;
 631                         #power-domain-cells = <1>;
 632                 };
 633
 634                 spmi_bus: spmi@c440000 {
 635                         compatible = "qcom,spmi-pmic-arb";
 636                         reg = <0x0 0x0c440000 0x0 0x0001100>,
 637                               <0x0 0x0c600000 0x0 0x2000000>,
 638                               <0x0 0x0e600000 0x0 0x0100000>,
 639                               <0x0 0x0e700000 0x0 0x00a0000>,
 640                               <0x0 0x0c40a000 0x0 0x0026000>;
 641                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
 642                         interrupt-names = "periph_irq";
 643                         interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
 644                         qcom,ee = <0>;
 645                         qcom,channel = <0>;
 646                         #address-cells = <2>;
 647                         #size-cells = <0>;
 648                         interrupt-controller;
 649                         #interrupt-cells = <4>;
 650                         cell-index = <0>;
 651                 };
 652
 653                 remoteproc_adsp: remoteproc@17300000 {
 654                         compatible = "qcom,sm8150-adsp-pas";
 655                         reg = <0x0 0x17300000 0x0 0x4040>;
 656
 657                         interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
 658                                               <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
 659                                               <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
 660                                               <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
 661                                               <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
 662                         interrupt-names = "wdog", "fatal", "ready",
 663                                           "handover", "stop-ack";
 664
 665                         clocks = <&rpmhcc RPMH_CXO_CLK>;
 666                         clock-names = "xo";
 667
 668                         power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>,
 669                                         <&rpmhpd 7>;
 670                         power-domain-names = "load_state", "cx";
 671
 672                         memory-region = <&adsp_mem>;
 673
 674                         qcom,smem-states = <&adsp_smp2p_out 0>;
 675                         qcom,smem-state-names = "stop";
 676
 677                         status = "disabled";
 678
 679                         glink-edge {
 680                                 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
 681                                 label = "lpass";
 682                                 qcom,remote-pid = <2>;
 683                                 mboxes = <&apss_shared 8>;
 684                         };
 685                 };
 686
 687                 intc: interrupt-controller@17a00000 {
 688                         compatible = "arm,gic-v3";
 689                         interrupt-controller;
 690                         #interrupt-cells = <3>;
 691                         reg = <0x0 0x17a00000 0x0 0x10000>,     /* GICD */
 692                               <0x0 0x17a60000 0x0 0x100000>;    /* GICR * 8 */
 693                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 694                 };
 695
 696                 apss_shared: mailbox@17c00000 {
 697                         compatible = "qcom,sm8150-apss-shared";
 698                         reg = <0x0 0x17c00000 0x0 0x1000>;
 699                         #mbox-cells = <1>;
 700                 };
 701
 702                 watchdog@17c10000 {
 703                         compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt";
 704                         reg = <0 0x17c10000 0 0x1000>;
 705                         clocks = <&sleep_clk>;
 706                 };
 707
 708                 timer@17c20000 {
 709                         #address-cells = <2>;
 710                         #size-cells = <2>;
 711                         ranges;
 712                         compatible = "arm,armv7-timer-mem";
 713                         reg = <0x0 0x17c20000 0x0 0x1000>;
 714                         clock-frequency = <19200000>;
 715
 716                         frame@17c21000{
 717                                 frame-number = <0>;
 718                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 719                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 720                                 reg = <0x0 0x17c21000 0x0 0x1000>,
 721                                       <0x0 0x17c22000 0x0 0x1000>;
 722                         };
 723
 724                         frame@17c23000 {
 725                                 frame-number = <1>;
 726                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 727                                 reg = <0x0 0x17c23000 0x0 0x1000>;
 728                                 status = "disabled";
 729                         };
 730
 731                         frame@17c25000 {
 732                                 frame-number = <2>;
 733                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 734                                 reg = <0x0 0x17c25000 0x0 0x1000>;
 735                                 status = "disabled";
 736                         };
 737
 738                         frame@17c27000 {
 739                                 frame-number = <3>;
 740                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 741                                 reg = <0x0 0x17c26000 0x0 0x1000>;
 742                                 status = "disabled";
 743                         };
 744
 745                         frame@17c29000 {
 746                                 frame-number = <4>;
 747                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 748                                 reg = <0x0 0x17c29000 0x0 0x1000>;
 749                                 status = "disabled";
 750                         };
 751
 752                         frame@17c2b000 {
 753                                 frame-number = <5>;
 754                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 755                                 reg = <0x0 0x17c2b000 0x0 0x1000>;
 756                                 status = "disabled";
 757                         };
 758
 759                         frame@17c2d000 {
 760                                 frame-number = <6>;
 761                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 762                                 reg = <0x0 0x17c2d000 0x0 0x1000>;
 763                                 status = "disabled";
 764                         };
 765                 };
 766
 767                 apps_rsc: rsc@18200000 {
 768                         label = "apps_rsc";
 769                         compatible = "qcom,rpmh-rsc";
 770                         reg = <0x0 0x18200000 0x0 0x10000>,
 771                               <0x0 0x18210000 0x0 0x10000>,
 772                               <0x0 0x18220000 0x0 0x10000>;
 773                         reg-names = "drv-0", "drv-1", "drv-2";
 774                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 775                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 776                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 777                         qcom,tcs-offset = <0xd00>;
 778                         qcom,drv-id = <2>;
 779                         qcom,tcs-config = <ACTIVE_TCS  2>,
 780                                           <SLEEP_TCS   1>,
 781                                           <WAKE_TCS    1>,
 782                                           <CONTROL_TCS 0>;
 783
 784                         rpmhcc: clock-controller {
 785                                 compatible = "qcom,sm8150-rpmh-clk";
 786                                 #clock-cells = <1>;
 787                                 clock-names = "xo";
 788                                 clocks = <&xo_board>;
 789                         };
 790
 791                         rpmhpd: power-controller {
 792                                 compatible = "qcom,sm8150-rpmhpd";
 793                                 #power-domain-cells = <1>;
 794                                 operating-points-v2 = <&rpmhpd_opp_table>;
 795
 796                                 rpmhpd_opp_table: opp-table {
 797                                         compatible = "operating-points-v2";
 798
 799                                         rpmhpd_opp_ret: opp1 {
 800                                                 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
 801                                         };
 802
 803                                         rpmhpd_opp_min_svs: opp2 {
 804                                                 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
 805                                         };
 806
 807                                         rpmhpd_opp_low_svs: opp3 {
 808                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
 809                                         };
 810
 811                                         rpmhpd_opp_svs: opp4 {
 812                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
 813                                         };
 814
 815                                         rpmhpd_opp_svs_l1: opp5 {
 816                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
 817                                         };
 818
 819                                         rpmhpd_opp_svs_l2: opp6 {
 820                                                 opp-level = <224>;
 821                                         };
 822
 823                                         rpmhpd_opp_nom: opp7 {
 824                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
 825                                         };
 826
 827                                         rpmhpd_opp_nom_l1: opp8 {
 828                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
 829                                         };
 830
 831                                         rpmhpd_opp_nom_l2: opp9 {
 832                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
 833                                         };
 834
 835                                         rpmhpd_opp_turbo: opp10 {
 836                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
 837                                         };
 838
 839                                         rpmhpd_opp_turbo_l1: opp11 {
 840                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
 841                                         };
 842                                 };
 843                         };
 844                 };
 845
 846                 cpufreq_hw: cpufreq@18323000 {
 847                         compatible = "qcom,cpufreq-hw";
 848                         reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>,
 849                               <0 0x18327800 0 0x1400>;
 850                         reg-names = "freq-domain0", "freq-domain1",
 851                                     "freq-domain2";
 852
 853                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
 854                         clock-names = "xo", "alternate";
 855
 856                         #freq-domain-cells = <1>;
 857                 };
 858         };
 859
 860         timer {
 861                 compatible = "arm,armv8-timer";
 862                 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
 863                              <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
 864                              <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
 865                              <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
 866         };
 867 };