sys/gnu/dts/arm64/renesas/r8a77980.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device Tree Source for the r8a77980 SoC
   4  *
   5  * Copyright (C) 2018 Renesas Electronics Corp.
   6  * Copyright (C) 2018 Cogent Embedded, Inc.
   7  */
   8
   9 #include <dt-bindings/clock/r8a77980-cpg-mssr.h>
  10 #include <dt-bindings/interrupt-controller/irq.h>
  11 #include <dt-bindings/interrupt-controller/arm-gic.h>
  12 #include <dt-bindings/power/r8a77980-sysc.h>
  13
  14 / {
  15         compatible = "renesas,r8a77980";
  16         #address-cells = <2>;
  17         #size-cells = <2>;
  18
  19         cpus {
  20                 #address-cells = <1>;
  21                 #size-cells = <0>;
  22
  23                 a53_0: cpu@0 {
  24                         device_type = "cpu";
  25                         compatible = "arm,cortex-a53", "arm,armv8";
  26                         reg = <0>;
  27                         clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
  28                         power-domains = <&sysc R8A77980_PD_CA53_CPU0>;
  29                         next-level-cache = <&L2_CA53>;
  30                         enable-method = "psci";
  31                 };
  32
  33                 L2_CA53: cache-controller {
  34                         compatible = "cache";
  35                         power-domains = <&sysc R8A77980_PD_CA53_SCU>;
  36                         cache-unified;
  37                         cache-level = <2>;
  38                 };
  39         };
  40
  41         /* External CAN clock - to be overridden by boards that provide it */
  42         can_clk: can {
  43                 compatible = "fixed-clock";
  44                 #clock-cells = <0>;
  45                 clock-frequency = <0>;
  46         };
  47
  48         extal_clk: extal {
  49                 compatible = "fixed-clock";
  50                 #clock-cells = <0>;
  51                 /* This value must be overridden by the board */
  52                 clock-frequency = <0>;
  53         };
  54
  55         extalr_clk: extalr {
  56                 compatible = "fixed-clock";
  57                 #clock-cells = <0>;
  58                 /* This value must be overridden by the board */
  59                 clock-frequency = <0>;
  60         };
  61
  62         psci {
  63                 compatible = "arm,psci-1.0", "arm,psci-0.2";
  64                 method = "smc";
  65         };
  66
  67         /* External SCIF clock - to be overridden by boards that provide it */
  68         scif_clk: scif {
  69                 compatible = "fixed-clock";
  70                 #clock-cells = <0>;
  71                 clock-frequency = <0>;
  72         };
  73
  74         soc {
  75                 compatible = "simple-bus";
  76                 interrupt-parent = <&gic>;
  77
  78                 #address-cells = <2>;
  79                 #size-cells = <2>;
  80                 ranges;
  81
  82                 pfc: pin-controller@e6060000 {
  83                         compatible = "renesas,pfc-r8a77980";
  84                         reg = <0 0xe6060000 0 0x50c>;
  85                 };
  86
  87                 cpg: clock-controller@e6150000 {
  88                         compatible = "renesas,r8a77980-cpg-mssr";
  89                         reg = <0 0xe6150000 0 0x1000>;
  90                         clocks = <&extal_clk>, <&extalr_clk>;
  91                         clock-names = "extal", "extalr";
  92                         #clock-cells = <2>;
  93                         #power-domain-cells = <0>;
  94                         #reset-cells = <1>;
  95                 };
  96
  97                 rst: reset-controller@e6160000 {
  98                         compatible = "renesas,r8a77980-rst";
  99                         reg = <0 0xe6160000 0 0x200>;
 100                 };
 101
 102                 sysc: system-controller@e6180000 {
 103                         compatible = "renesas,r8a77980-sysc";
 104                         reg = <0 0xe6180000 0 0x440>;
 105                         #power-domain-cells = <1>;
 106                 };
 107
 108                 hscif0: serial@e6540000 {
 109                         compatible = "renesas,hscif-r8a77980",
 110                                      "renesas,rcar-gen3-hscif",
 111                                      "renesas,hscif";
 112                         reg = <0 0xe6540000 0 0x60>;
 113                         interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 114                         clocks = <&cpg CPG_MOD 520>,
 115                                  <&cpg CPG_CORE R8A77980_CLK_S3D1>,
 116                                  <&scif_clk>;
 117                         clock-names = "fck", "brg_int", "scif_clk";
 118                         dmas = <&dmac1 0x31>, <&dmac1 0x30>,
 119                                <&dmac2 0x31>, <&dmac2 0x30>;
 120                         dma-names = "tx", "rx", "tx", "rx";
 121                         power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
 122                         resets = <&cpg 520>;
 123                         status = "disabled";
 124                 };
 125
 126                 hscif1: serial@e6550000 {
 127                         compatible = "renesas,hscif-r8a77980",
 128                                      "renesas,rcar-gen3-hscif",
 129                                      "renesas,hscif";
 130                         reg = <0 0xe6550000 0 0x60>;
 131                         interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
 132                         clocks = <&cpg CPG_MOD 519>,
 133                                  <&cpg CPG_CORE R8A77980_CLK_S3D1>,
 134                                  <&scif_clk>;
 135                         clock-names = "fck", "brg_int", "scif_clk";
 136                         dmas = <&dmac1 0x33>, <&dmac1 0x32>,
 137                                <&dmac2 0x33>, <&dmac2 0x32>;
 138                         dma-names = "tx", "rx", "tx", "rx";
 139                         power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
 140                         resets = <&cpg 519>;
 141                         status = "disabled";
 142                 };
 143
 144                 hscif2: serial@e6560000 {
 145                         compatible = "renesas,hscif-r8a77980",
 146                                      "renesas,rcar-gen3-hscif",
 147                                      "renesas,hscif";
 148                         reg = <0 0xe6560000 0 0x60>;
 149                         interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 150                         clocks = <&cpg CPG_MOD 518>,
 151                                  <&cpg CPG_CORE R8A77980_CLK_S3D1>,
 152                                  <&scif_clk>;
 153                         clock-names = "fck", "brg_int", "scif_clk";
 154                         dmas = <&dmac1 0x35>, <&dmac1 0x34>,
 155                                <&dmac2 0x35>, <&dmac2 0x34>;
 156                         dma-names = "tx", "rx", "tx", "rx";
 157                         power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
 158                         resets = <&cpg 518>;
 159                         status = "disabled";
 160                 };
 161
 162                 hscif3: serial@e66a0000 {
 163                         compatible = "renesas,hscif-r8a77980",
 164                                      "renesas,rcar-gen3-hscif",
 165                                      "renesas,hscif";
 166                         reg = <0 0xe66a0000 0 0x60>;
 167                         interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
 168                         clocks = <&cpg CPG_MOD 517>,
 169                                  <&cpg CPG_CORE R8A77980_CLK_S3D1>,
 170                                  <&scif_clk>;
 171                         clock-names = "fck", "brg_int", "scif_clk";
 172                         dmas = <&dmac1 0x37>, <&dmac1 0x36>,
 173                                <&dmac2 0x37>, <&dmac2 0x36>;
 174                         dma-names = "tx", "rx", "tx", "rx";
 175                         power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
 176                         resets = <&cpg 517>;
 177                         status = "disabled";
 178                 };
 179
 180                 canfd: can@e66c0000 {
 181                         compatible = "renesas,r8a77980-canfd",
 182                                      "renesas,rcar-gen3-canfd";
 183                         reg = <0 0xe66c0000 0 0x8000>;
 184                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
 185                                      <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 186                         clocks = <&cpg CPG_MOD 914>,
 187                                  <&cpg CPG_CORE R8A77980_CLK_CANFD>,
 188                                  <&can_clk>;
 189                         clock-names = "fck", "canfd", "can_clk";
 190                         assigned-clocks = <&cpg CPG_CORE R8A77980_CLK_CANFD>;
 191                         assigned-clock-rates = <40000000>;
 192                         power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
 193                         resets = <&cpg 914>;
 194                         status = "disabled";
 195
 196                         channel0 {
 197                                 status = "disabled";
 198                         };
 199
 200                         channel1 {
 201                                 status = "disabled";
 202                         };
 203                 };
 204
 205                 avb: ethernet@e6800000 {
 206                         compatible = "renesas,etheravb-r8a77980",
 207                                      "renesas,etheravb-rcar-gen3";
 208                         reg = <0 0xe6800000 0 0x800>;
 209                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
 210                                      <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 211                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 212                                      <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
 213                                      <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
 214                                      <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
 215                                      <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
 216                                      <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
 217                                      <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
 218                                      <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
 219                                      <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
 220                                      <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
 221                                      <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
 222                                      <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
 223                                      <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
 224                                      <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 225                                      <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 226                                      <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
 227                                      <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
 228                                      <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
 229                                      <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
 230                                      <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
 231                                      <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
 232                                      <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
 233                                      <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 234                         interrupt-names = "ch0", "ch1", "ch2", "ch3",
 235                                           "ch4", "ch5", "ch6", "ch7",
 236                                           "ch8", "ch9", "ch10", "ch11",
 237                                           "ch12", "ch13", "ch14", "ch15",
 238                                           "ch16", "ch17", "ch18", "ch19",
 239                                           "ch20", "ch21", "ch22", "ch23",
 240                                           "ch24";
 241                         clocks = <&cpg CPG_MOD 812>;
 242                         power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
 243                         resets = <&cpg 812>;
 244                         phy-mode = "rgmii";
 245                         #address-cells = <1>;
 246                         #size-cells = <0>;
 247                         status = "disabled";
 248                 };
 249
 250                 scif0: serial@e6e60000 {
 251                         compatible = "renesas,scif-r8a77980",
 252                                      "renesas,rcar-gen3-scif",
 253                                      "renesas,scif";
 254                         reg = <0 0xe6e60000 0 0x40>;
 255                         interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
 256                         clocks = <&cpg CPG_MOD 207>,
 257                                  <&cpg CPG_CORE R8A77980_CLK_S3D1>,
 258                                  <&scif_clk>;
 259                         clock-names = "fck", "brg_int", "scif_clk";
 260                         dmas = <&dmac1 0x51>, <&dmac1 0x50>,
 261                                <&dmac2 0x51>, <&dmac2 0x50>;
 262                         dma-names = "tx", "rx", "tx", "rx";
 263                         power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
 264                         resets = <&cpg 207>;
 265                         status = "disabled";
 266                 };
 267
 268                 scif1: serial@e6e68000 {
 269                         compatible = "renesas,scif-r8a77980",
 270                                      "renesas,rcar-gen3-scif",
 271                                      "renesas,scif";
 272                         reg = <0 0xe6e68000 0 0x40>;
 273                         interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 274                         clocks = <&cpg CPG_MOD 206>,
 275                                  <&cpg CPG_CORE R8A77980_CLK_S3D1>,
 276                                  <&scif_clk>;
 277                         clock-names = "fck", "brg_int", "scif_clk";
 278                         dmas = <&dmac1 0x53>, <&dmac1 0x52>,
 279                                <&dmac2 0x53>, <&dmac2 0x52>;
 280                         dma-names = "tx", "rx", "tx", "rx";
 281                         power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
 282                         resets = <&cpg 206>;
 283                         status = "disabled";
 284                 };
 285
 286                 scif3: serial@e6c50000 {
 287                         compatible = "renesas,scif-r8a77980",
 288                                      "renesas,rcar-gen3-scif",
 289                                      "renesas,scif";
 290                         reg = <0 0xe6c50000 0 0x40>;
 291                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 292                         clocks = <&cpg CPG_MOD 204>,
 293                                  <&cpg CPG_CORE R8A77980_CLK_S3D1>,
 294                                  <&scif_clk>;
 295                         clock-names = "fck", "brg_int", "scif_clk";
 296                         dmas = <&dmac1 0x57>, <&dmac1 0x56>,
 297                                <&dmac2 0x57>, <&dmac2 0x56>;
 298                         dma-names = "tx", "rx", "tx", "rx";
 299                         power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
 300                         resets = <&cpg 204>;
 301                         status = "disabled";
 302                 };
 303
 304                 scif4: serial@e6c40000 {
 305                         compatible = "renesas,scif-r8a77980",
 306                                      "renesas,rcar-gen3-scif",
 307                                      "renesas,scif";
 308                         reg = <0 0xe6c40000 0 0x40>;
 309                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 310                         clocks = <&cpg CPG_MOD 203>,
 311                                  <&cpg CPG_CORE R8A77980_CLK_S3D1>,
 312                                  <&scif_clk>;
 313                         clock-names = "fck", "brg_int", "scif_clk";
 314                         dmas = <&dmac1 0x59>, <&dmac1 0x58>,
 315                                <&dmac2 0x59>, <&dmac2 0x58>;
 316                         dma-names = "tx", "rx", "tx", "rx";
 317                         power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
 318                         resets = <&cpg 203>;
 319                         status = "disabled";
 320                 };
 321
 322                 dmac1: dma-controller@e7300000 {
 323                         compatible = "renesas,dmac-r8a77980",
 324                                      "renesas,rcar-dmac";
 325                         reg = <0 0xe7300000 0 0x10000>;
 326                         interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
 327                                       GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
 328                                       GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
 329                                       GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
 330                                       GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
 331                                       GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
 332                                       GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
 333                                       GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
 334                                       GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
 335                                       GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH
 336                                       GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH
 337                                       GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH
 338                                       GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH
 339                                       GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH
 340                                       GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH
 341                                       GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH
 342                                       GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
 343                         interrupt-names = "error",
 344                                           "ch0", "ch1", "ch2", "ch3",
 345                                           "ch4", "ch5", "ch6", "ch7",
 346                                           "ch8", "ch9", "ch10", "ch11",
 347                                           "ch12", "ch13", "ch14", "ch15";
 348                         clocks = <&cpg CPG_MOD 218>;
 349                         clock-names = "fck";
 350                         power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
 351                         resets = <&cpg 218>;
 352                         #dma-cells = <1>;
 353                         dma-channels = <16>;
 354                 };
 355
 356                 dmac2: dma-controller@e7310000 {
 357                         compatible = "renesas,dmac-r8a77980",
 358                                      "renesas,rcar-dmac";
 359                         reg = <0 0xe7310000 0 0x10000>;
 360                         interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH
 361                                       GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
 362                                       GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
 363                                       GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
 364                                       GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
 365                                       GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
 366                                       GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
 367                                       GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
 368                                       GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH
 369                                       GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH
 370                                       GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH
 371                                       GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH
 372                                       GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH
 373                                       GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH
 374                                       GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH
 375                                       GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH
 376                                       GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
 377                         interrupt-names = "error",
 378                                           "ch0", "ch1", "ch2", "ch3",
 379                                           "ch4", "ch5", "ch6", "ch7",
 380                                           "ch8", "ch9", "ch10", "ch11",
 381                                           "ch12", "ch13", "ch14", "ch15";
 382                         clocks = <&cpg CPG_MOD 217>;
 383                         clock-names = "fck";
 384                         power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
 385                         resets = <&cpg 217>;
 386                         #dma-cells = <1>;
 387                         dma-channels = <16>;
 388                 };
 389
 390                 mmc0: mmc@ee140000 {
 391                         compatible = "renesas,sdhi-r8a77980",
 392                                      "renesas,rcar-gen3-sdhi";
 393                         reg = <0 0xee140000 0 0x2000>;
 394                         interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
 395                         clocks = <&cpg CPG_MOD 314>;
 396                         power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
 397                         resets = <&cpg 314>;
 398                         max-frequency = <200000000>;
 399                         status = "disabled";
 400                 };
 401
 402                 gic: interrupt-controller@f1010000 {
 403                         compatible = "arm,gic-400";
 404                         #interrupt-cells = <3>;
 405                         #address-cells = <0>;
 406                         interrupt-controller;
 407                         reg = <0x0 0xf1010000 0 0x1000>,
 408                               <0x0 0xf1020000 0 0x20000>,
 409                               <0x0 0xf1040000 0 0x20000>,
 410                               <0x0 0xf1060000 0 0x20000>;
 411                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) |
 412                                       IRQ_TYPE_LEVEL_HIGH)>;
 413                         clocks = <&cpg CPG_MOD 408>;
 414                         clock-names = "clk";
 415                         power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
 416                         resets = <&cpg 408>;
 417                 };
 418
 419                 prr: chipid@fff00044 {
 420                         compatible = "renesas,prr";
 421                         reg = <0 0xfff00044 0 4>;
 422                 };
 423         };
 424
 425         timer {
 426                 compatible = "arm,armv8-timer";
 427                 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) |
 428                                        IRQ_TYPE_LEVEL_LOW)>,
 429                                       <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) |
 430                                        IRQ_TYPE_LEVEL_LOW)>,
 431                                       <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) |
 432                                        IRQ_TYPE_LEVEL_LOW)>,
 433                                       <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) |
 434                                        IRQ_TYPE_LEVEL_LOW)>;
 435         };
 436 };